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ARM: dts: r8a77(43|9[013]): Add missing OPP properties for CPUs
The OPP properties, like "operating-points", should either be present
for all the CPUs of a cluster or none. If these are present only for a
subset of CPUs of a cluster then things will start falling apart as soon
as the CPUs are brought online in a different order. For example, this
will happen because the operating system looks for such properties in
the CPU node it is trying to bring up, so that it can create an OPP
table.
Add such missing properties.
Fix other missing properties (like, clock latency, voltage tolerance,
etc) as well to make it all work.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
authored by
Viresh Kumar
and committed by
Simon Horman
8199e49f
5058a96c
+66
-6
+9
arch/arm/boot/dts/r8a7743.dtsi
+9
arch/arm/boot/dts/r8a7743.dtsi
···
98
98
reg = <1>;
99
99
clock-frequency = <1500000000>;
100
100
clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
101
+
clock-latency = <300000>; /* 300 us */
101
102
power-domains = <&sysc R8A7743_PD_CA15_CPU1>;
102
103
next-level-cache = <&L2_CA15>;
104
+
105
+
/* kHz - uV - OPPs unknown yet */
106
+
operating-points = <1500000 1000000>,
107
+
<1312500 1000000>,
108
+
<1125000 1000000>,
109
+
< 937500 1000000>,
110
+
< 750000 1000000>,
111
+
< 375000 1000000>;
103
112
};
104
113
105
114
L2_CA15: cache-controller-0 {
+32
-2
arch/arm/boot/dts/r8a7790.dtsi
+32
-2
arch/arm/boot/dts/r8a7790.dtsi
···
79
79
compatible = "arm,cortex-a15";
80
80
reg = <0>;
81
81
clock-frequency = <1300000000>;
82
-
voltage-tolerance = <1>; /* 1% */
83
82
clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
84
-
clock-latency = <300000>; /* 300 us */
85
83
power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
86
84
next-level-cache = <&L2_CA15>;
87
85
capacity-dmips-mhz = <1024>;
86
+
voltage-tolerance = <1>; /* 1% */
87
+
clock-latency = <300000>; /* 300 us */
88
88
89
89
/* kHz - uV - OPPs unknown yet */
90
90
operating-points = <1400000 1000000>,
···
104
104
power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
105
105
next-level-cache = <&L2_CA15>;
106
106
capacity-dmips-mhz = <1024>;
107
+
voltage-tolerance = <1>; /* 1% */
108
+
clock-latency = <300000>; /* 300 us */
109
+
110
+
/* kHz - uV - OPPs unknown yet */
111
+
operating-points = <1400000 1000000>,
112
+
<1225000 1000000>,
113
+
<1050000 1000000>,
114
+
< 875000 1000000>,
115
+
< 700000 1000000>,
116
+
< 350000 1000000>;
107
117
};
108
118
109
119
cpu2: cpu@2 {
···
125
115
power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
126
116
next-level-cache = <&L2_CA15>;
127
117
capacity-dmips-mhz = <1024>;
118
+
voltage-tolerance = <1>; /* 1% */
119
+
clock-latency = <300000>; /* 300 us */
120
+
121
+
/* kHz - uV - OPPs unknown yet */
122
+
operating-points = <1400000 1000000>,
123
+
<1225000 1000000>,
124
+
<1050000 1000000>,
125
+
< 875000 1000000>,
126
+
< 700000 1000000>,
127
+
< 350000 1000000>;
128
128
};
129
129
130
130
cpu3: cpu@3 {
···
146
126
power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
147
127
next-level-cache = <&L2_CA15>;
148
128
capacity-dmips-mhz = <1024>;
129
+
voltage-tolerance = <1>; /* 1% */
130
+
clock-latency = <300000>; /* 300 us */
131
+
132
+
/* kHz - uV - OPPs unknown yet */
133
+
operating-points = <1400000 1000000>,
134
+
<1225000 1000000>,
135
+
<1050000 1000000>,
136
+
< 875000 1000000>,
137
+
< 700000 1000000>,
138
+
< 350000 1000000>;
149
139
};
150
140
151
141
cpu4: cpu@100 {
+12
-2
arch/arm/boot/dts/r8a7791.dtsi
+12
-2
arch/arm/boot/dts/r8a7791.dtsi
···
78
78
compatible = "arm,cortex-a15";
79
79
reg = <0>;
80
80
clock-frequency = <1500000000>;
81
-
voltage-tolerance = <1>; /* 1% */
82
81
clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
83
-
clock-latency = <300000>; /* 300 us */
84
82
power-domains = <&sysc R8A7791_PD_CA15_CPU0>;
85
83
next-level-cache = <&L2_CA15>;
84
+
voltage-tolerance = <1>; /* 1% */
85
+
clock-latency = <300000>; /* 300 us */
86
86
87
87
/* kHz - uV - OPPs unknown yet */
88
88
operating-points = <1500000 1000000>,
···
101
101
clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
102
102
power-domains = <&sysc R8A7791_PD_CA15_CPU1>;
103
103
next-level-cache = <&L2_CA15>;
104
+
voltage-tolerance = <1>; /* 1% */
105
+
clock-latency = <300000>; /* 300 us */
106
+
107
+
/* kHz - uV - OPPs unknown yet */
108
+
operating-points = <1500000 1000000>,
109
+
<1312500 1000000>,
110
+
<1125000 1000000>,
111
+
< 937500 1000000>,
112
+
< 750000 1000000>,
113
+
< 375000 1000000>;
104
114
};
105
115
106
116
L2_CA15: cache-controller-0 {
+13
-2
arch/arm/boot/dts/r8a7793.dtsi
+13
-2
arch/arm/boot/dts/r8a7793.dtsi
···
70
70
compatible = "arm,cortex-a15";
71
71
reg = <0>;
72
72
clock-frequency = <1500000000>;
73
-
voltage-tolerance = <1>; /* 1% */
74
73
clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
75
-
clock-latency = <300000>; /* 300 us */
76
74
power-domains = <&sysc R8A7793_PD_CA15_CPU0>;
75
+
voltage-tolerance = <1>; /* 1% */
76
+
clock-latency = <300000>; /* 300 us */
77
77
78
78
/* kHz - uV - OPPs unknown yet */
79
79
operating-points = <1500000 1000000>,
···
92
92
clock-frequency = <1500000000>;
93
93
clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
94
94
power-domains = <&sysc R8A7793_PD_CA15_CPU1>;
95
+
voltage-tolerance = <1>; /* 1% */
96
+
clock-latency = <300000>; /* 300 us */
97
+
98
+
/* kHz - uV - OPPs unknown yet */
99
+
operating-points = <1500000 1000000>,
100
+
<1312500 1000000>,
101
+
<1125000 1000000>,
102
+
< 937500 1000000>,
103
+
< 750000 1000000>,
104
+
< 375000 1000000>;
105
+
next-level-cache = <&L2_CA15>;
95
106
};
96
107
97
108
L2_CA15: cache-controller-0 {