tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

clk: qcom: Remove CLK_IS_ROOT

This flag is a no-op now. Remove usage of the flag.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

Stephen Boyd 81925c5e 782fa520

+2 -152
-1
drivers/clk/qcom/common.c
··· 119 119 fixed->hw.init = &init_data; 120 120 121 121 init_data.name = path; 122 - init_data.flags = CLK_IS_ROOT; 123 122 init_data.ops = &clk_fixed_rate_ops; 124 123 125 124 clk = devm_clk_register(dev, &fixed->hw);
-37
drivers/clk/qcom/gcc-ipq806x.c
··· 890 890 .hw.init = &(struct clk_init_data){ 891 891 .name = "gsbi1_h_clk", 892 892 .ops = &clk_branch_ops, 893 - .flags = CLK_IS_ROOT, 894 893 }, 895 894 }, 896 895 }; ··· 905 906 .hw.init = &(struct clk_init_data){ 906 907 .name = "gsbi2_h_clk", 907 908 .ops = &clk_branch_ops, 908 - .flags = CLK_IS_ROOT, 909 909 }, 910 910 }, 911 911 }; ··· 920 922 .hw.init = &(struct clk_init_data){ 921 923 .name = "gsbi4_h_clk", 922 924 .ops = &clk_branch_ops, 923 - .flags = CLK_IS_ROOT, 924 925 }, 925 926 }, 926 927 }; ··· 935 938 .hw.init = &(struct clk_init_data){ 936 939 .name = "gsbi5_h_clk", 937 940 .ops = &clk_branch_ops, 938 - .flags = CLK_IS_ROOT, 939 941 }, 940 942 }, 941 943 }; ··· 950 954 .hw.init = &(struct clk_init_data){ 951 955 .name = "gsbi6_h_clk", 952 956 .ops = &clk_branch_ops, 953 - .flags = CLK_IS_ROOT, 954 957 }, 955 958 }, 956 959 }; ··· 965 970 .hw.init = &(struct clk_init_data){ 966 971 .name = "gsbi7_h_clk", 967 972 .ops = &clk_branch_ops, 968 - .flags = CLK_IS_ROOT, 969 973 }, 970 974 }, 971 975 }; ··· 1138 1144 .hw.init = &(struct clk_init_data){ 1139 1145 .name = "pmem_clk", 1140 1146 .ops = &clk_branch_ops, 1141 - .flags = CLK_IS_ROOT, 1142 1147 }, 1143 1148 }, 1144 1149 }; ··· 1301 1308 .hw.init = &(struct clk_init_data){ 1302 1309 .name = "sdc1_h_clk", 1303 1310 .ops = &clk_branch_ops, 1304 - .flags = CLK_IS_ROOT, 1305 1311 }, 1306 1312 }, 1307 1313 }; ··· 1316 1324 .hw.init = &(struct clk_init_data){ 1317 1325 .name = "sdc3_h_clk", 1318 1326 .ops = &clk_branch_ops, 1319 - .flags = CLK_IS_ROOT, 1320 1327 }, 1321 1328 }, 1322 1329 }; ··· 1385 1394 .hw.init = &(struct clk_init_data){ 1386 1395 .name = "tsif_h_clk", 1387 1396 .ops = &clk_branch_ops, 1388 - .flags = CLK_IS_ROOT, 1389 1397 }, 1390 1398 }, 1391 1399 }; ··· 1400 1410 .hw.init = &(struct clk_init_data){ 1401 1411 .name = "dma_bam_h_clk", 1402 1412 .ops = &clk_branch_ops, 1403 - .flags = CLK_IS_ROOT, 1404 1413 }, 1405 1414 }, 1406 1415 }; ··· 1414 1425 .hw.init = &(struct clk_init_data){ 1415 1426 .name = "adm0_clk", 1416 1427 .ops = &clk_branch_ops, 1417 - .flags = CLK_IS_ROOT, 1418 1428 }, 1419 1429 }, 1420 1430 }; ··· 1430 1442 .hw.init = &(struct clk_init_data){ 1431 1443 .name = "adm0_pbus_clk", 1432 1444 .ops = &clk_branch_ops, 1433 - .flags = CLK_IS_ROOT, 1434 1445 }, 1435 1446 }, 1436 1447 }; ··· 1444 1457 .hw.init = &(struct clk_init_data){ 1445 1458 .name = "pmic_arb0_h_clk", 1446 1459 .ops = &clk_branch_ops, 1447 - .flags = CLK_IS_ROOT, 1448 1460 }, 1449 1461 }, 1450 1462 }; ··· 1458 1472 .hw.init = &(struct clk_init_data){ 1459 1473 .name = "pmic_arb1_h_clk", 1460 1474 .ops = &clk_branch_ops, 1461 - .flags = CLK_IS_ROOT, 1462 1475 }, 1463 1476 }, 1464 1477 }; ··· 1472 1487 .hw.init = &(struct clk_init_data){ 1473 1488 .name = "pmic_ssbi2_clk", 1474 1489 .ops = &clk_branch_ops, 1475 - .flags = CLK_IS_ROOT, 1476 1490 }, 1477 1491 }, 1478 1492 }; ··· 1488 1504 .hw.init = &(struct clk_init_data){ 1489 1505 .name = "rpm_msg_ram_h_clk", 1490 1506 .ops = &clk_branch_ops, 1491 - .flags = CLK_IS_ROOT, 1492 1507 }, 1493 1508 }, 1494 1509 }; ··· 1546 1563 .hw.init = &(struct clk_init_data){ 1547 1564 .name = "pcie_a_clk", 1548 1565 .ops = &clk_branch_ops, 1549 - .flags = CLK_IS_ROOT, 1550 1566 }, 1551 1567 }, 1552 1568 }; ··· 1559 1577 .hw.init = &(struct clk_init_data){ 1560 1578 .name = "pcie_aux_clk", 1561 1579 .ops = &clk_branch_ops, 1562 - .flags = CLK_IS_ROOT, 1563 1580 }, 1564 1581 }, 1565 1582 }; ··· 1572 1591 .hw.init = &(struct clk_init_data){ 1573 1592 .name = "pcie_h_clk", 1574 1593 .ops = &clk_branch_ops, 1575 - .flags = CLK_IS_ROOT, 1576 1594 }, 1577 1595 }, 1578 1596 }; ··· 1585 1605 .hw.init = &(struct clk_init_data){ 1586 1606 .name = "pcie_phy_clk", 1587 1607 .ops = &clk_branch_ops, 1588 - .flags = CLK_IS_ROOT, 1589 1608 }, 1590 1609 }, 1591 1610 }; ··· 1638 1659 .hw.init = &(struct clk_init_data){ 1639 1660 .name = "pcie1_a_clk", 1640 1661 .ops = &clk_branch_ops, 1641 - .flags = CLK_IS_ROOT, 1642 1662 }, 1643 1663 }, 1644 1664 }; ··· 1651 1673 .hw.init = &(struct clk_init_data){ 1652 1674 .name = "pcie1_aux_clk", 1653 1675 .ops = &clk_branch_ops, 1654 - .flags = CLK_IS_ROOT, 1655 1676 }, 1656 1677 }, 1657 1678 }; ··· 1664 1687 .hw.init = &(struct clk_init_data){ 1665 1688 .name = "pcie1_h_clk", 1666 1689 .ops = &clk_branch_ops, 1667 - .flags = CLK_IS_ROOT, 1668 1690 }, 1669 1691 }, 1670 1692 }; ··· 1677 1701 .hw.init = &(struct clk_init_data){ 1678 1702 .name = "pcie1_phy_clk", 1679 1703 .ops = &clk_branch_ops, 1680 - .flags = CLK_IS_ROOT, 1681 1704 }, 1682 1705 }, 1683 1706 }; ··· 1730 1755 .hw.init = &(struct clk_init_data){ 1731 1756 .name = "pcie2_a_clk", 1732 1757 .ops = &clk_branch_ops, 1733 - .flags = CLK_IS_ROOT, 1734 1758 }, 1735 1759 }, 1736 1760 }; ··· 1743 1769 .hw.init = &(struct clk_init_data){ 1744 1770 .name = "pcie2_aux_clk", 1745 1771 .ops = &clk_branch_ops, 1746 - .flags = CLK_IS_ROOT, 1747 1772 }, 1748 1773 }, 1749 1774 }; ··· 1756 1783 .hw.init = &(struct clk_init_data){ 1757 1784 .name = "pcie2_h_clk", 1758 1785 .ops = &clk_branch_ops, 1759 - .flags = CLK_IS_ROOT, 1760 1786 }, 1761 1787 }, 1762 1788 }; ··· 1769 1797 .hw.init = &(struct clk_init_data){ 1770 1798 .name = "pcie2_phy_clk", 1771 1799 .ops = &clk_branch_ops, 1772 - .flags = CLK_IS_ROOT, 1773 1800 }, 1774 1801 }, 1775 1802 }; ··· 1858 1887 .hw.init = &(struct clk_init_data){ 1859 1888 .name = "sata_a_clk", 1860 1889 .ops = &clk_branch_ops, 1861 - .flags = CLK_IS_ROOT, 1862 1890 }, 1863 1891 }, 1864 1892 }; ··· 1871 1901 .hw.init = &(struct clk_init_data){ 1872 1902 .name = "sata_h_clk", 1873 1903 .ops = &clk_branch_ops, 1874 - .flags = CLK_IS_ROOT, 1875 1904 }, 1876 1905 }, 1877 1906 }; ··· 1884 1915 .hw.init = &(struct clk_init_data){ 1885 1916 .name = "sfab_sata_s_h_clk", 1886 1917 .ops = &clk_branch_ops, 1887 - .flags = CLK_IS_ROOT, 1888 1918 }, 1889 1919 }, 1890 1920 }; ··· 1897 1929 .hw.init = &(struct clk_init_data){ 1898 1930 .name = "sata_phy_cfg_clk", 1899 1931 .ops = &clk_branch_ops, 1900 - .flags = CLK_IS_ROOT, 1901 1932 }, 1902 1933 }, 1903 1934 }; ··· 2106 2139 .hw.init = &(struct clk_init_data){ 2107 2140 .name = "usb_hs1_h_clk", 2108 2141 .ops = &clk_branch_ops, 2109 - .flags = CLK_IS_ROOT, 2110 2142 }, 2111 2143 }, 2112 2144 }; ··· 2184 2218 .hw.init = &(struct clk_init_data){ 2185 2219 .name = "usb_fs1_h_clk", 2186 2220 .ops = &clk_branch_ops, 2187 - .flags = CLK_IS_ROOT, 2188 2221 }, 2189 2222 }, 2190 2223 }; ··· 2199 2234 .hw.init = &(struct clk_init_data){ 2200 2235 .name = "ebi2_clk", 2201 2236 .ops = &clk_branch_ops, 2202 - .flags = CLK_IS_ROOT, 2203 2237 }, 2204 2238 }, 2205 2239 }; ··· 2212 2248 .hw.init = &(struct clk_init_data){ 2213 2249 .name = "ebi2_always_on_clk", 2214 2250 .ops = &clk_branch_ops, 2215 - .flags = CLK_IS_ROOT, 2216 2251 }, 2217 2252 }, 2218 2253 };
-32
drivers/clk/qcom/gcc-msm8660.c
··· 1479 1479 .hw.init = &(struct clk_init_data){ 1480 1480 .name = "pmem_clk", 1481 1481 .ops = &clk_branch_ops, 1482 - .flags = CLK_IS_ROOT, 1483 1482 }, 1484 1483 }, 1485 1484 }; ··· 2026 2027 .hw.init = &(struct clk_init_data){ 2027 2028 .name = "gsbi1_h_clk", 2028 2029 .ops = &clk_branch_ops, 2029 - .flags = CLK_IS_ROOT, 2030 2030 }, 2031 2031 }, 2032 2032 }; ··· 2039 2041 .hw.init = &(struct clk_init_data){ 2040 2042 .name = "gsbi2_h_clk", 2041 2043 .ops = &clk_branch_ops, 2042 - .flags = CLK_IS_ROOT, 2043 2044 }, 2044 2045 }, 2045 2046 }; ··· 2052 2055 .hw.init = &(struct clk_init_data){ 2053 2056 .name = "gsbi3_h_clk", 2054 2057 .ops = &clk_branch_ops, 2055 - .flags = CLK_IS_ROOT, 2056 2058 }, 2057 2059 }, 2058 2060 }; ··· 2065 2069 .hw.init = &(struct clk_init_data){ 2066 2070 .name = "gsbi4_h_clk", 2067 2071 .ops = &clk_branch_ops, 2068 - .flags = CLK_IS_ROOT, 2069 2072 }, 2070 2073 }, 2071 2074 }; ··· 2078 2083 .hw.init = &(struct clk_init_data){ 2079 2084 .name = "gsbi5_h_clk", 2080 2085 .ops = &clk_branch_ops, 2081 - .flags = CLK_IS_ROOT, 2082 2086 }, 2083 2087 }, 2084 2088 }; ··· 2091 2097 .hw.init = &(struct clk_init_data){ 2092 2098 .name = "gsbi6_h_clk", 2093 2099 .ops = &clk_branch_ops, 2094 - .flags = CLK_IS_ROOT, 2095 2100 }, 2096 2101 }, 2097 2102 }; ··· 2104 2111 .hw.init = &(struct clk_init_data){ 2105 2112 .name = "gsbi7_h_clk", 2106 2113 .ops = &clk_branch_ops, 2107 - .flags = CLK_IS_ROOT, 2108 2114 }, 2109 2115 }, 2110 2116 }; ··· 2117 2125 .hw.init = &(struct clk_init_data){ 2118 2126 .name = "gsbi8_h_clk", 2119 2127 .ops = &clk_branch_ops, 2120 - .flags = CLK_IS_ROOT, 2121 2128 }, 2122 2129 }, 2123 2130 }; ··· 2130 2139 .hw.init = &(struct clk_init_data){ 2131 2140 .name = "gsbi9_h_clk", 2132 2141 .ops = &clk_branch_ops, 2133 - .flags = CLK_IS_ROOT, 2134 2142 }, 2135 2143 }, 2136 2144 }; ··· 2143 2153 .hw.init = &(struct clk_init_data){ 2144 2154 .name = "gsbi10_h_clk", 2145 2155 .ops = &clk_branch_ops, 2146 - .flags = CLK_IS_ROOT, 2147 2156 }, 2148 2157 }, 2149 2158 }; ··· 2156 2167 .hw.init = &(struct clk_init_data){ 2157 2168 .name = "gsbi11_h_clk", 2158 2169 .ops = &clk_branch_ops, 2159 - .flags = CLK_IS_ROOT, 2160 2170 }, 2161 2171 }, 2162 2172 }; ··· 2169 2181 .hw.init = &(struct clk_init_data){ 2170 2182 .name = "gsbi12_h_clk", 2171 2183 .ops = &clk_branch_ops, 2172 - .flags = CLK_IS_ROOT, 2173 2184 }, 2174 2185 }, 2175 2186 }; ··· 2182 2195 .hw.init = &(struct clk_init_data){ 2183 2196 .name = "tsif_h_clk", 2184 2197 .ops = &clk_branch_ops, 2185 - .flags = CLK_IS_ROOT, 2186 2198 }, 2187 2199 }, 2188 2200 }; ··· 2195 2209 .hw.init = &(struct clk_init_data){ 2196 2210 .name = "usb_fs1_h_clk", 2197 2211 .ops = &clk_branch_ops, 2198 - .flags = CLK_IS_ROOT, 2199 2212 }, 2200 2213 }, 2201 2214 }; ··· 2208 2223 .hw.init = &(struct clk_init_data){ 2209 2224 .name = "usb_fs2_h_clk", 2210 2225 .ops = &clk_branch_ops, 2211 - .flags = CLK_IS_ROOT, 2212 2226 }, 2213 2227 }, 2214 2228 }; ··· 2221 2237 .hw.init = &(struct clk_init_data){ 2222 2238 .name = "usb_hs1_h_clk", 2223 2239 .ops = &clk_branch_ops, 2224 - .flags = CLK_IS_ROOT, 2225 2240 }, 2226 2241 }, 2227 2242 }; ··· 2234 2251 .hw.init = &(struct clk_init_data){ 2235 2252 .name = "sdc1_h_clk", 2236 2253 .ops = &clk_branch_ops, 2237 - .flags = CLK_IS_ROOT, 2238 2254 }, 2239 2255 }, 2240 2256 }; ··· 2247 2265 .hw.init = &(struct clk_init_data){ 2248 2266 .name = "sdc2_h_clk", 2249 2267 .ops = &clk_branch_ops, 2250 - .flags = CLK_IS_ROOT, 2251 2268 }, 2252 2269 }, 2253 2270 }; ··· 2260 2279 .hw.init = &(struct clk_init_data){ 2261 2280 .name = "sdc3_h_clk", 2262 2281 .ops = &clk_branch_ops, 2263 - .flags = CLK_IS_ROOT, 2264 2282 }, 2265 2283 }, 2266 2284 }; ··· 2273 2293 .hw.init = &(struct clk_init_data){ 2274 2294 .name = "sdc4_h_clk", 2275 2295 .ops = &clk_branch_ops, 2276 - .flags = CLK_IS_ROOT, 2277 2296 }, 2278 2297 }, 2279 2298 }; ··· 2286 2307 .hw.init = &(struct clk_init_data){ 2287 2308 .name = "sdc5_h_clk", 2288 2309 .ops = &clk_branch_ops, 2289 - .flags = CLK_IS_ROOT, 2290 2310 }, 2291 2311 }, 2292 2312 }; ··· 2300 2322 .hw.init = &(struct clk_init_data){ 2301 2323 .name = "adm0_clk", 2302 2324 .ops = &clk_branch_ops, 2303 - .flags = CLK_IS_ROOT, 2304 2325 }, 2305 2326 }, 2306 2327 }; ··· 2314 2337 .hw.init = &(struct clk_init_data){ 2315 2338 .name = "adm0_pbus_clk", 2316 2339 .ops = &clk_branch_ops, 2317 - .flags = CLK_IS_ROOT, 2318 2340 }, 2319 2341 }, 2320 2342 }; ··· 2328 2352 .hw.init = &(struct clk_init_data){ 2329 2353 .name = "adm1_clk", 2330 2354 .ops = &clk_branch_ops, 2331 - .flags = CLK_IS_ROOT, 2332 2355 }, 2333 2356 }, 2334 2357 }; ··· 2342 2367 .hw.init = &(struct clk_init_data){ 2343 2368 .name = "adm1_pbus_clk", 2344 2369 .ops = &clk_branch_ops, 2345 - .flags = CLK_IS_ROOT, 2346 2370 }, 2347 2371 }, 2348 2372 }; ··· 2356 2382 .hw.init = &(struct clk_init_data){ 2357 2383 .name = "modem_ahb1_h_clk", 2358 2384 .ops = &clk_branch_ops, 2359 - .flags = CLK_IS_ROOT, 2360 2385 }, 2361 2386 }, 2362 2387 }; ··· 2370 2397 .hw.init = &(struct clk_init_data){ 2371 2398 .name = "modem_ahb2_h_clk", 2372 2399 .ops = &clk_branch_ops, 2373 - .flags = CLK_IS_ROOT, 2374 2400 }, 2375 2401 }, 2376 2402 }; ··· 2384 2412 .hw.init = &(struct clk_init_data){ 2385 2413 .name = "pmic_arb0_h_clk", 2386 2414 .ops = &clk_branch_ops, 2387 - .flags = CLK_IS_ROOT, 2388 2415 }, 2389 2416 }, 2390 2417 }; ··· 2398 2427 .hw.init = &(struct clk_init_data){ 2399 2428 .name = "pmic_arb1_h_clk", 2400 2429 .ops = &clk_branch_ops, 2401 - .flags = CLK_IS_ROOT, 2402 2430 }, 2403 2431 }, 2404 2432 }; ··· 2412 2442 .hw.init = &(struct clk_init_data){ 2413 2443 .name = "pmic_ssbi2_clk", 2414 2444 .ops = &clk_branch_ops, 2415 - .flags = CLK_IS_ROOT, 2416 2445 }, 2417 2446 }, 2418 2447 }; ··· 2428 2459 .hw.init = &(struct clk_init_data){ 2429 2460 .name = "rpm_msg_ram_h_clk", 2430 2461 .ops = &clk_branch_ops, 2431 - .flags = CLK_IS_ROOT, 2432 2462 }, 2433 2463 }, 2434 2464 };
-42
drivers/clk/qcom/gcc-msm8960.c
··· 1546 1546 .hw.init = &(struct clk_init_data){ 1547 1547 .name = "pmem_clk", 1548 1548 .ops = &clk_branch_ops, 1549 - .flags = CLK_IS_ROOT, 1550 1549 }, 1551 1550 }, 1552 1551 }; ··· 2142 2143 .hw.init = &(struct clk_init_data){ 2143 2144 .name = "usb_hsic_hsio_cal_clk", 2144 2145 .ops = &clk_branch_ops, 2145 - .flags = CLK_IS_ROOT, 2146 2146 }, 2147 2147 }, 2148 2148 }; ··· 2291 2293 .hw.init = &(struct clk_init_data){ 2292 2294 .name = "ce1_core_clk", 2293 2295 .ops = &clk_branch_ops, 2294 - .flags = CLK_IS_ROOT, 2295 2296 }, 2296 2297 }, 2297 2298 }; ··· 2304 2307 .hw.init = &(struct clk_init_data){ 2305 2308 .name = "ce1_h_clk", 2306 2309 .ops = &clk_branch_ops, 2307 - .flags = CLK_IS_ROOT, 2308 2310 }, 2309 2311 }, 2310 2312 }; ··· 2319 2323 .hw.init = &(struct clk_init_data){ 2320 2324 .name = "dma_bam_h_clk", 2321 2325 .ops = &clk_branch_ops, 2322 - .flags = CLK_IS_ROOT, 2323 2326 }, 2324 2327 }, 2325 2328 }; ··· 2334 2339 .hw.init = &(struct clk_init_data){ 2335 2340 .name = "gsbi1_h_clk", 2336 2341 .ops = &clk_branch_ops, 2337 - .flags = CLK_IS_ROOT, 2338 2342 }, 2339 2343 }, 2340 2344 }; ··· 2349 2355 .hw.init = &(struct clk_init_data){ 2350 2356 .name = "gsbi2_h_clk", 2351 2357 .ops = &clk_branch_ops, 2352 - .flags = CLK_IS_ROOT, 2353 2358 }, 2354 2359 }, 2355 2360 }; ··· 2364 2371 .hw.init = &(struct clk_init_data){ 2365 2372 .name = "gsbi3_h_clk", 2366 2373 .ops = &clk_branch_ops, 2367 - .flags = CLK_IS_ROOT, 2368 2374 }, 2369 2375 }, 2370 2376 }; ··· 2379 2387 .hw.init = &(struct clk_init_data){ 2380 2388 .name = "gsbi4_h_clk", 2381 2389 .ops = &clk_branch_ops, 2382 - .flags = CLK_IS_ROOT, 2383 2390 }, 2384 2391 }, 2385 2392 }; ··· 2394 2403 .hw.init = &(struct clk_init_data){ 2395 2404 .name = "gsbi5_h_clk", 2396 2405 .ops = &clk_branch_ops, 2397 - .flags = CLK_IS_ROOT, 2398 2406 }, 2399 2407 }, 2400 2408 }; ··· 2409 2419 .hw.init = &(struct clk_init_data){ 2410 2420 .name = "gsbi6_h_clk", 2411 2421 .ops = &clk_branch_ops, 2412 - .flags = CLK_IS_ROOT, 2413 2422 }, 2414 2423 }, 2415 2424 }; ··· 2424 2435 .hw.init = &(struct clk_init_data){ 2425 2436 .name = "gsbi7_h_clk", 2426 2437 .ops = &clk_branch_ops, 2427 - .flags = CLK_IS_ROOT, 2428 2438 }, 2429 2439 }, 2430 2440 }; ··· 2439 2451 .hw.init = &(struct clk_init_data){ 2440 2452 .name = "gsbi8_h_clk", 2441 2453 .ops = &clk_branch_ops, 2442 - .flags = CLK_IS_ROOT, 2443 2454 }, 2444 2455 }, 2445 2456 }; ··· 2454 2467 .hw.init = &(struct clk_init_data){ 2455 2468 .name = "gsbi9_h_clk", 2456 2469 .ops = &clk_branch_ops, 2457 - .flags = CLK_IS_ROOT, 2458 2470 }, 2459 2471 }, 2460 2472 }; ··· 2469 2483 .hw.init = &(struct clk_init_data){ 2470 2484 .name = "gsbi10_h_clk", 2471 2485 .ops = &clk_branch_ops, 2472 - .flags = CLK_IS_ROOT, 2473 2486 }, 2474 2487 }, 2475 2488 }; ··· 2484 2499 .hw.init = &(struct clk_init_data){ 2485 2500 .name = "gsbi11_h_clk", 2486 2501 .ops = &clk_branch_ops, 2487 - .flags = CLK_IS_ROOT, 2488 2502 }, 2489 2503 }, 2490 2504 }; ··· 2499 2515 .hw.init = &(struct clk_init_data){ 2500 2516 .name = "gsbi12_h_clk", 2501 2517 .ops = &clk_branch_ops, 2502 - .flags = CLK_IS_ROOT, 2503 2518 }, 2504 2519 }, 2505 2520 }; ··· 2514 2531 .hw.init = &(struct clk_init_data){ 2515 2532 .name = "tsif_h_clk", 2516 2533 .ops = &clk_branch_ops, 2517 - .flags = CLK_IS_ROOT, 2518 2534 }, 2519 2535 }, 2520 2536 }; ··· 2527 2545 .hw.init = &(struct clk_init_data){ 2528 2546 .name = "usb_fs1_h_clk", 2529 2547 .ops = &clk_branch_ops, 2530 - .flags = CLK_IS_ROOT, 2531 2548 }, 2532 2549 }, 2533 2550 }; ··· 2540 2559 .hw.init = &(struct clk_init_data){ 2541 2560 .name = "usb_fs2_h_clk", 2542 2561 .ops = &clk_branch_ops, 2543 - .flags = CLK_IS_ROOT, 2544 2562 }, 2545 2563 }, 2546 2564 }; ··· 2555 2575 .hw.init = &(struct clk_init_data){ 2556 2576 .name = "usb_hs1_h_clk", 2557 2577 .ops = &clk_branch_ops, 2558 - .flags = CLK_IS_ROOT, 2559 2578 }, 2560 2579 }, 2561 2580 }; ··· 2568 2589 .hw.init = &(struct clk_init_data){ 2569 2590 .name = "usb_hs3_h_clk", 2570 2591 .ops = &clk_branch_ops, 2571 - .flags = CLK_IS_ROOT, 2572 2592 }, 2573 2593 }, 2574 2594 }; ··· 2581 2603 .hw.init = &(struct clk_init_data){ 2582 2604 .name = "usb_hs4_h_clk", 2583 2605 .ops = &clk_branch_ops, 2584 - .flags = CLK_IS_ROOT, 2585 2606 }, 2586 2607 }, 2587 2608 }; ··· 2594 2617 .hw.init = &(struct clk_init_data){ 2595 2618 .name = "usb_hsic_h_clk", 2596 2619 .ops = &clk_branch_ops, 2597 - .flags = CLK_IS_ROOT, 2598 2620 }, 2599 2621 }, 2600 2622 }; ··· 2609 2633 .hw.init = &(struct clk_init_data){ 2610 2634 .name = "sdc1_h_clk", 2611 2635 .ops = &clk_branch_ops, 2612 - .flags = CLK_IS_ROOT, 2613 2636 }, 2614 2637 }, 2615 2638 }; ··· 2624 2649 .hw.init = &(struct clk_init_data){ 2625 2650 .name = "sdc2_h_clk", 2626 2651 .ops = &clk_branch_ops, 2627 - .flags = CLK_IS_ROOT, 2628 2652 }, 2629 2653 }, 2630 2654 }; ··· 2639 2665 .hw.init = &(struct clk_init_data){ 2640 2666 .name = "sdc3_h_clk", 2641 2667 .ops = &clk_branch_ops, 2642 - .flags = CLK_IS_ROOT, 2643 2668 }, 2644 2669 }, 2645 2670 }; ··· 2654 2681 .hw.init = &(struct clk_init_data){ 2655 2682 .name = "sdc4_h_clk", 2656 2683 .ops = &clk_branch_ops, 2657 - .flags = CLK_IS_ROOT, 2658 2684 }, 2659 2685 }, 2660 2686 }; ··· 2669 2697 .hw.init = &(struct clk_init_data){ 2670 2698 .name = "sdc5_h_clk", 2671 2699 .ops = &clk_branch_ops, 2672 - .flags = CLK_IS_ROOT, 2673 2700 }, 2674 2701 }, 2675 2702 }; ··· 2683 2712 .hw.init = &(struct clk_init_data){ 2684 2713 .name = "adm0_clk", 2685 2714 .ops = &clk_branch_ops, 2686 - .flags = CLK_IS_ROOT, 2687 2715 }, 2688 2716 }, 2689 2717 }; ··· 2699 2729 .hw.init = &(struct clk_init_data){ 2700 2730 .name = "adm0_pbus_clk", 2701 2731 .ops = &clk_branch_ops, 2702 - .flags = CLK_IS_ROOT, 2703 2732 }, 2704 2733 }, 2705 2734 }; ··· 2852 2883 .hw.init = &(struct clk_init_data){ 2853 2884 .name = "sata_a_clk", 2854 2885 .ops = &clk_branch_ops, 2855 - .flags = CLK_IS_ROOT, 2856 2886 }, 2857 2887 }, 2858 2888 }; ··· 2865 2897 .hw.init = &(struct clk_init_data){ 2866 2898 .name = "sata_h_clk", 2867 2899 .ops = &clk_branch_ops, 2868 - .flags = CLK_IS_ROOT, 2869 2900 }, 2870 2901 }, 2871 2902 }; ··· 2878 2911 .hw.init = &(struct clk_init_data){ 2879 2912 .name = "sfab_sata_s_h_clk", 2880 2913 .ops = &clk_branch_ops, 2881 - .flags = CLK_IS_ROOT, 2882 2914 }, 2883 2915 }, 2884 2916 }; ··· 2891 2925 .hw.init = &(struct clk_init_data){ 2892 2926 .name = "sata_phy_cfg_clk", 2893 2927 .ops = &clk_branch_ops, 2894 - .flags = CLK_IS_ROOT, 2895 2928 }, 2896 2929 }, 2897 2930 }; ··· 2904 2939 .hw.init = &(struct clk_init_data){ 2905 2940 .name = "pcie_phy_ref_clk", 2906 2941 .ops = &clk_branch_ops, 2907 - .flags = CLK_IS_ROOT, 2908 2942 }, 2909 2943 }, 2910 2944 }; ··· 2917 2953 .hw.init = &(struct clk_init_data){ 2918 2954 .name = "pcie_h_clk", 2919 2955 .ops = &clk_branch_ops, 2920 - .flags = CLK_IS_ROOT, 2921 2956 }, 2922 2957 }, 2923 2958 }; ··· 2930 2967 .hw.init = &(struct clk_init_data){ 2931 2968 .name = "pcie_a_clk", 2932 2969 .ops = &clk_branch_ops, 2933 - .flags = CLK_IS_ROOT, 2934 2970 }, 2935 2971 }, 2936 2972 }; ··· 2944 2982 .hw.init = &(struct clk_init_data){ 2945 2983 .name = "pmic_arb0_h_clk", 2946 2984 .ops = &clk_branch_ops, 2947 - .flags = CLK_IS_ROOT, 2948 2985 }, 2949 2986 }, 2950 2987 }; ··· 2958 2997 .hw.init = &(struct clk_init_data){ 2959 2998 .name = "pmic_arb1_h_clk", 2960 2999 .ops = &clk_branch_ops, 2961 - .flags = CLK_IS_ROOT, 2962 3000 }, 2963 3001 }, 2964 3002 }; ··· 2972 3012 .hw.init = &(struct clk_init_data){ 2973 3013 .name = "pmic_ssbi2_clk", 2974 3014 .ops = &clk_branch_ops, 2975 - .flags = CLK_IS_ROOT, 2976 3015 }, 2977 3016 }, 2978 3017 }; ··· 2988 3029 .hw.init = &(struct clk_init_data){ 2989 3030 .name = "rpm_msg_ram_h_clk", 2990 3031 .ops = &clk_branch_ops, 2991 - .flags = CLK_IS_ROOT, 2992 3032 }, 2993 3033 }, 2994 3034 };
-1
drivers/clk/qcom/gcc-msm8974.c
··· 1965 1965 .enable_mask = BIT(0), 1966 1966 .hw.init = &(struct clk_init_data){ 1967 1967 .name = "gcc_mss_q6_bimc_axi_clk", 1968 - .flags = CLK_IS_ROOT, 1969 1968 .ops = &clk_branch2_ops, 1970 1969 }, 1971 1970 },
+2 -4
drivers/clk/qcom/gcc-msm8996.c
··· 1321 1321 .enable_mask = BIT(0), 1322 1322 .hw.init = &(struct clk_init_data){ 1323 1323 .name = "gcc_mmss_bimc_gfx_clk", 1324 - .flags = CLK_SET_RATE_PARENT | CLK_IS_ROOT, 1324 + .flags = CLK_SET_RATE_PARENT, 1325 1325 .ops = &clk_branch2_ops, 1326 1326 }, 1327 1327 }, ··· 2315 2315 .enable_mask = BIT(0), 2316 2316 .hw.init = &(struct clk_init_data){ 2317 2317 .name = "gcc_bimc_gfx_clk", 2318 - .flags = CLK_SET_RATE_PARENT | CLK_IS_ROOT, 2318 + .flags = CLK_SET_RATE_PARENT, 2319 2319 .ops = &clk_branch2_ops, 2320 2320 }, 2321 2321 }, ··· 2815 2815 .hw.init = &(struct clk_init_data){ 2816 2816 .name = "gcc_ufs_sys_clk_core_clk", 2817 2817 .ops = &clk_branch2_ops, 2818 - .flags = CLK_IS_ROOT, 2819 2818 }, 2820 2819 }, 2821 2820 }; ··· 2827 2828 .hw.init = &(struct clk_init_data){ 2828 2829 .name = "gcc_ufs_tx_symbol_clk_core_clk", 2829 2830 .ops = &clk_branch2_ops, 2830 - .flags = CLK_IS_ROOT, 2831 2831 }, 2832 2832 }, 2833 2833 };
-35
drivers/clk/qcom/mmcc-msm8960.c
··· 1789 1789 .hw.init = &(struct clk_init_data){ 1790 1790 .name = "gmem_axi_clk", 1791 1791 .ops = &clk_branch_ops, 1792 - .flags = CLK_IS_ROOT, 1793 1792 }, 1794 1793 }, 1795 1794 }; ··· 1804 1805 .hw.init = &(struct clk_init_data){ 1805 1806 .name = "ijpeg_axi_clk", 1806 1807 .ops = &clk_branch_ops, 1807 - .flags = CLK_IS_ROOT, 1808 1808 }, 1809 1809 }, 1810 1810 }; ··· 1819 1821 .hw.init = &(struct clk_init_data){ 1820 1822 .name = "mmss_imem_axi_clk", 1821 1823 .ops = &clk_branch_ops, 1822 - .flags = CLK_IS_ROOT, 1823 1824 }, 1824 1825 }, 1825 1826 }; ··· 1832 1835 .hw.init = &(struct clk_init_data){ 1833 1836 .name = "jpegd_axi_clk", 1834 1837 .ops = &clk_branch_ops, 1835 - .flags = CLK_IS_ROOT, 1836 1838 }, 1837 1839 }, 1838 1840 }; ··· 1847 1851 .hw.init = &(struct clk_init_data){ 1848 1852 .name = "vcodec_axi_b_clk", 1849 1853 .ops = &clk_branch_ops, 1850 - .flags = CLK_IS_ROOT, 1851 1854 }, 1852 1855 }, 1853 1856 }; ··· 1862 1867 .hw.init = &(struct clk_init_data){ 1863 1868 .name = "vcodec_axi_a_clk", 1864 1869 .ops = &clk_branch_ops, 1865 - .flags = CLK_IS_ROOT, 1866 1870 }, 1867 1871 }, 1868 1872 }; ··· 1877 1883 .hw.init = &(struct clk_init_data){ 1878 1884 .name = "vcodec_axi_clk", 1879 1885 .ops = &clk_branch_ops, 1880 - .flags = CLK_IS_ROOT, 1881 1886 }, 1882 1887 }, 1883 1888 }; ··· 1890 1897 .hw.init = &(struct clk_init_data){ 1891 1898 .name = "vfe_axi_clk", 1892 1899 .ops = &clk_branch_ops, 1893 - .flags = CLK_IS_ROOT, 1894 1900 }, 1895 1901 }, 1896 1902 }; ··· 1905 1913 .hw.init = &(struct clk_init_data){ 1906 1914 .name = "mdp_axi_clk", 1907 1915 .ops = &clk_branch_ops, 1908 - .flags = CLK_IS_ROOT, 1909 1916 }, 1910 1917 }, 1911 1918 }; ··· 1920 1929 .hw.init = &(struct clk_init_data){ 1921 1930 .name = "rot_axi_clk", 1922 1931 .ops = &clk_branch_ops, 1923 - .flags = CLK_IS_ROOT, 1924 1932 }, 1925 1933 }, 1926 1934 }; ··· 1935 1945 .hw.init = &(struct clk_init_data){ 1936 1946 .name = "vcap_axi_clk", 1937 1947 .ops = &clk_branch_ops, 1938 - .flags = CLK_IS_ROOT, 1939 1948 }, 1940 1949 }, 1941 1950 }; ··· 1950 1961 .hw.init = &(struct clk_init_data){ 1951 1962 .name = "vpe_axi_clk", 1952 1963 .ops = &clk_branch_ops, 1953 - .flags = CLK_IS_ROOT, 1954 1964 }, 1955 1965 }, 1956 1966 }; ··· 1965 1977 .hw.init = &(struct clk_init_data){ 1966 1978 .name = "gfx3d_axi_clk", 1967 1979 .ops = &clk_branch_ops, 1968 - .flags = CLK_IS_ROOT, 1969 1980 }, 1970 1981 }, 1971 1982 }; ··· 1978 1991 .hw.init = &(struct clk_init_data){ 1979 1992 .name = "amp_ahb_clk", 1980 1993 .ops = &clk_branch_ops, 1981 - .flags = CLK_IS_ROOT, 1982 1994 }, 1983 1995 }, 1984 1996 }; ··· 1991 2005 .hw.init = &(struct clk_init_data){ 1992 2006 .name = "csi_ahb_clk", 1993 2007 .ops = &clk_branch_ops, 1994 - .flags = CLK_IS_ROOT 1995 2008 }, 1996 2009 }, 1997 2010 }; ··· 2004 2019 .hw.init = &(struct clk_init_data){ 2005 2020 .name = "dsi_m_ahb_clk", 2006 2021 .ops = &clk_branch_ops, 2007 - .flags = CLK_IS_ROOT, 2008 2022 }, 2009 2023 }, 2010 2024 }; ··· 2019 2035 .hw.init = &(struct clk_init_data){ 2020 2036 .name = "dsi_s_ahb_clk", 2021 2037 .ops = &clk_branch_ops, 2022 - .flags = CLK_IS_ROOT, 2023 2038 }, 2024 2039 }, 2025 2040 }; ··· 2032 2049 .hw.init = &(struct clk_init_data){ 2033 2050 .name = "dsi2_m_ahb_clk", 2034 2051 .ops = &clk_branch_ops, 2035 - .flags = CLK_IS_ROOT 2036 2052 }, 2037 2053 }, 2038 2054 }; ··· 2047 2065 .hw.init = &(struct clk_init_data){ 2048 2066 .name = "dsi2_s_ahb_clk", 2049 2067 .ops = &clk_branch_ops, 2050 - .flags = CLK_IS_ROOT, 2051 2068 }, 2052 2069 }, 2053 2070 }; ··· 2406 2425 .hw.init = &(struct clk_init_data){ 2407 2426 .name = "gfx2d0_ahb_clk", 2408 2427 .ops = &clk_branch_ops, 2409 - .flags = CLK_IS_ROOT, 2410 2428 }, 2411 2429 }, 2412 2430 }; ··· 2421 2441 .hw.init = &(struct clk_init_data){ 2422 2442 .name = "gfx2d1_ahb_clk", 2423 2443 .ops = &clk_branch_ops, 2424 - .flags = CLK_IS_ROOT, 2425 2444 }, 2426 2445 }, 2427 2446 }; ··· 2436 2457 .hw.init = &(struct clk_init_data){ 2437 2458 .name = "gfx3d_ahb_clk", 2438 2459 .ops = &clk_branch_ops, 2439 - .flags = CLK_IS_ROOT, 2440 2460 }, 2441 2461 }, 2442 2462 }; ··· 2451 2473 .hw.init = &(struct clk_init_data){ 2452 2474 .name = "hdmi_m_ahb_clk", 2453 2475 .ops = &clk_branch_ops, 2454 - .flags = CLK_IS_ROOT, 2455 2476 }, 2456 2477 }, 2457 2478 }; ··· 2466 2489 .hw.init = &(struct clk_init_data){ 2467 2490 .name = "hdmi_s_ahb_clk", 2468 2491 .ops = &clk_branch_ops, 2469 - .flags = CLK_IS_ROOT, 2470 2492 }, 2471 2493 }, 2472 2494 }; ··· 2479 2503 .hw.init = &(struct clk_init_data){ 2480 2504 .name = "ijpeg_ahb_clk", 2481 2505 .ops = &clk_branch_ops, 2482 - .flags = CLK_IS_ROOT 2483 2506 }, 2484 2507 }, 2485 2508 }; ··· 2494 2519 .hw.init = &(struct clk_init_data){ 2495 2520 .name = "mmss_imem_ahb_clk", 2496 2521 .ops = &clk_branch_ops, 2497 - .flags = CLK_IS_ROOT 2498 2522 }, 2499 2523 }, 2500 2524 }; ··· 2507 2533 .hw.init = &(struct clk_init_data){ 2508 2534 .name = "jpegd_ahb_clk", 2509 2535 .ops = &clk_branch_ops, 2510 - .flags = CLK_IS_ROOT, 2511 2536 }, 2512 2537 }, 2513 2538 }; ··· 2520 2547 .hw.init = &(struct clk_init_data){ 2521 2548 .name = "mdp_ahb_clk", 2522 2549 .ops = &clk_branch_ops, 2523 - .flags = CLK_IS_ROOT, 2524 2550 }, 2525 2551 }, 2526 2552 }; ··· 2533 2561 .hw.init = &(struct clk_init_data){ 2534 2562 .name = "rot_ahb_clk", 2535 2563 .ops = &clk_branch_ops, 2536 - .flags = CLK_IS_ROOT 2537 2564 }, 2538 2565 }, 2539 2566 }; ··· 2548 2577 .hw.init = &(struct clk_init_data){ 2549 2578 .name = "smmu_ahb_clk", 2550 2579 .ops = &clk_branch_ops, 2551 - .flags = CLK_IS_ROOT, 2552 2580 }, 2553 2581 }, 2554 2582 }; ··· 2561 2591 .hw.init = &(struct clk_init_data){ 2562 2592 .name = "tv_enc_ahb_clk", 2563 2593 .ops = &clk_branch_ops, 2564 - .flags = CLK_IS_ROOT, 2565 2594 }, 2566 2595 }, 2567 2596 }; ··· 2574 2605 .hw.init = &(struct clk_init_data){ 2575 2606 .name = "vcap_ahb_clk", 2576 2607 .ops = &clk_branch_ops, 2577 - .flags = CLK_IS_ROOT, 2578 2608 }, 2579 2609 }, 2580 2610 }; ··· 2589 2621 .hw.init = &(struct clk_init_data){ 2590 2622 .name = "vcodec_ahb_clk", 2591 2623 .ops = &clk_branch_ops, 2592 - .flags = CLK_IS_ROOT, 2593 2624 }, 2594 2625 }, 2595 2626 }; ··· 2602 2635 .hw.init = &(struct clk_init_data){ 2603 2636 .name = "vfe_ahb_clk", 2604 2637 .ops = &clk_branch_ops, 2605 - .flags = CLK_IS_ROOT, 2606 2638 }, 2607 2639 }, 2608 2640 }; ··· 2615 2649 .hw.init = &(struct clk_init_data){ 2616 2650 .name = "vpe_ahb_clk", 2617 2651 .ops = &clk_branch_ops, 2618 - .flags = CLK_IS_ROOT, 2619 2652 }, 2620 2653 }, 2621 2654 };