ARM: dts: imx6qdl: make pinctrl nodes board specific

+104 -12

arch/arm/boot/dts/imx6q-arm2.dts

··· 55 55 56 56 &gpmi { 57 57 pinctrl-names = "default"; 58 - pinctrl-0 = <&pinctrl_gpmi_nand_1>; 58 + pinctrl-0 = <&pinctrl_gpmi_nand>; 59 59 status = "disabled"; /* gpmi nand conflicts with SD */ 60 60 }; 61 61 ··· 63 63 pinctrl-names = "default"; 64 64 pinctrl-0 = <&pinctrl_hog>; 65 65 66 - hog { 66 + imx6q-arm2 { 67 67 pinctrl_hog: hoggrp { 68 68 fsl,pins = < 69 69 MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000 70 70 >; 71 71 }; 72 - }; 73 72 74 - arm2 { 75 - pinctrl_usdhc3_arm2: usdhc3grp-arm2 { 73 + pinctrl_enet: enetgrp { 74 + fsl,pins = < 75 + MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 76 + MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 77 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 78 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 79 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 80 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 81 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 82 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 83 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 84 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 85 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 86 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 87 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 88 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 89 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 90 + >; 91 + }; 92 + 93 + pinctrl_gpmi_nand: gpminandgrp { 94 + fsl,pins = < 95 + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 96 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 97 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 98 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 99 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 100 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 101 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 102 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 103 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 104 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 105 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 106 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 107 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 108 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 109 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 110 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 111 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 112 + >; 113 + }; 114 + 115 + pinctrl_uart2: uart2grp { 116 + fsl,pins = < 117 + MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 118 + MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 119 + MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 120 + MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 121 + >; 122 + }; 123 + 124 + pinctrl_uart4: uart4grp { 125 + fsl,pins = < 126 + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 127 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 128 + >; 129 + }; 130 + 131 + pinctrl_usbotg: usbotggrp { 132 + fsl,pins = < 133 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 134 + >; 135 + }; 136 + 137 + pinctrl_usdhc3: usdhc3grp { 138 + fsl,pins = < 139 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 140 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 141 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 142 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 143 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 144 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 145 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 146 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 147 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 148 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 149 + >; 150 + }; 151 + 152 + pinctrl_usdhc3_cdwp: usdhc3cdwp { 76 153 fsl,pins = < 77 154 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 78 155 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 156 + >; 157 + }; 158 + 159 + pinctrl_usdhc4: usdhc4grp { 160 + fsl,pins = < 161 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 162 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 163 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 164 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 165 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 166 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 167 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 168 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 169 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 170 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 79 171 >; 80 172 }; 81 173 }; ··· 175 83 176 84 &fec { 177 85 pinctrl-names = "default"; 178 - pinctrl-0 = <&pinctrl_enet_2>; 86 + pinctrl-0 = <&pinctrl_enet>; 179 87 phy-mode = "rgmii"; 180 88 status = "okay"; 181 89 }; ··· 183 91 &usbotg { 184 92 vbus-supply = <&reg_usb_otg_vbus>; 185 93 pinctrl-names = "default"; 186 - pinctrl-0 = <&pinctrl_usbotg_1>; 94 + pinctrl-0 = <&pinctrl_usbotg>; 187 95 disable-over-current; 188 96 status = "okay"; 189 97 }; ··· 193 101 wp-gpios = <&gpio6 14 0>; 194 102 vmmc-supply = <&reg_3p3v>; 195 103 pinctrl-names = "default"; 196 - pinctrl-0 = <&pinctrl_usdhc3_1 197 - &pinctrl_usdhc3_arm2>; 104 + pinctrl-0 = <&pinctrl_usdhc3 105 + &pinctrl_usdhc3_cdwp>; 198 106 status = "okay"; 199 107 }; 200 108 ··· 202 110 non-removable; 203 111 vmmc-supply = <&reg_3p3v>; 204 112 pinctrl-names = "default"; 205 - pinctrl-0 = <&pinctrl_usdhc4_1>; 113 + pinctrl-0 = <&pinctrl_usdhc4>; 206 114 status = "okay"; 207 115 }; 208 116 209 117 &uart2 { 210 118 pinctrl-names = "default"; 211 - pinctrl-0 = <&pinctrl_uart2_2>; 119 + pinctrl-0 = <&pinctrl_uart2>; 212 120 fsl,dte-mode; 213 121 fsl,uart-has-rtscts; 214 122 status = "okay"; ··· 216 124 217 125 &uart4 { 218 126 pinctrl-names = "default"; 219 - pinctrl-0 = <&pinctrl_uart4_1>; 127 + pinctrl-0 = <&pinctrl_uart4>; 220 128 status = "okay"; 221 129 };

+74 -11

arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi

··· 22 22 23 23 &ecspi3 { 24 24 pinctrl-names = "default"; 25 - pinctrl-0 = <&pinctrl_ecspi3_1>; 25 + pinctrl-0 = <&pinctrl_ecspi3>; 26 26 status = "okay"; 27 27 fsl,spi-num-chipselects = <1>; 28 28 cs-gpios = <&gpio4 24 0>; ··· 36 36 37 37 &i2c1 { 38 38 pinctrl-names = "default"; 39 - pinctrl-0 = <&pinctrl_i2c1_1>; 39 + pinctrl-0 = <&pinctrl_i2c1>; 40 40 status = "okay"; 41 41 42 42 eeprom@50 { ··· 128 128 pinctrl-names = "default"; 129 129 pinctrl-0 = <&pinctrl_hog>; 130 130 131 - hog { 131 + imx6q-phytec-pfla02 { 132 132 pinctrl_hog: hoggrp { 133 133 fsl,pins = < 134 134 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 ··· 136 136 MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000 /* PMIC interrupt */ 137 137 >; 138 138 }; 139 - }; 140 139 141 - pfla02 { 142 - pinctrl_usdhc3_pfla02: usdhc3grp-pfla02 { 140 + pinctrl_ecspi3: ecspi3grp { 141 + fsl,pins = < 142 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 143 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 144 + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 145 + >; 146 + }; 147 + 148 + pinctrl_enet: enetgrp { 149 + fsl,pins = < 150 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 151 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 152 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 153 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 154 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 155 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 156 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 157 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 158 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 159 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 160 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 161 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 162 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 163 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 164 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 165 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 166 + >; 167 + }; 168 + 169 + pinctrl_i2c1: i2c1grp { 170 + fsl,pins = < 171 + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 172 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 173 + >; 174 + }; 175 + 176 + pinctrl_uart4: uart4grp { 177 + fsl,pins = < 178 + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 179 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 180 + >; 181 + }; 182 + 183 + pinctrl_usdhc2: usdhc2grp { 184 + fsl,pins = < 185 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 186 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 187 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 188 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 189 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 190 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 191 + >; 192 + }; 193 + 194 + pinctrl_usdhc3: usdhc3grp { 195 + fsl,pins = < 196 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 197 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 198 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 199 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 200 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 201 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 202 + >; 203 + }; 204 + 205 + pinctrl_usdhc3_cdwp: usdhc3cdwp { 143 206 fsl,pins = < 144 207 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 145 208 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 ··· 213 150 214 151 &fec { 215 152 pinctrl-names = "default"; 216 - pinctrl-0 = <&pinctrl_enet_3>; 153 + pinctrl-0 = <&pinctrl_enet>; 217 154 phy-mode = "rgmii"; 218 155 phy-reset-gpios = <&gpio3 23 0>; 219 156 status = "disabled"; ··· 221 158 222 159 &uart4 { 223 160 pinctrl-names = "default"; 224 - pinctrl-0 = <&pinctrl_uart4_1>; 161 + pinctrl-0 = <&pinctrl_uart4>; 225 162 status = "disabled"; 226 163 }; 227 164 228 165 &usdhc2 { 229 166 pinctrl-names = "default"; 230 - pinctrl-0 = <&pinctrl_usdhc2_2>; 167 + pinctrl-0 = <&pinctrl_usdhc2>; 231 168 cd-gpios = <&gpio1 4 0>; 232 169 wp-gpios = <&gpio1 2 0>; 233 170 status = "disabled"; ··· 235 172 236 173 &usdhc3 { 237 174 pinctrl-names = "default"; 238 - pinctrl-0 = <&pinctrl_usdhc3_2 239 - &pinctrl_usdhc3_pfla02>; 175 + pinctrl-0 = <&pinctrl_usdhc3 176 + &pinctrl_usdhc3_cdwp>; 240 177 cd-gpios = <&gpio1 27 0>; 241 178 wp-gpios = <&gpio1 29 0>; 242 179 status = "disabled";

+89 -9

arch/arm/boot/dts/imx6q-sabrelite.dts

··· 68 68 &audmux { 69 69 status = "okay"; 70 70 pinctrl-names = "default"; 71 - pinctrl-0 = <&pinctrl_audmux_1>; 71 + pinctrl-0 = <&pinctrl_audmux>; 72 72 }; 73 73 74 74 &ecspi1 { 75 75 fsl,spi-num-chipselects = <1>; 76 76 cs-gpios = <&gpio3 19 0>; 77 77 pinctrl-names = "default"; 78 - pinctrl-0 = <&pinctrl_ecspi1_1>; 78 + pinctrl-0 = <&pinctrl_ecspi1>; 79 79 status = "okay"; 80 80 81 81 flash: m25p80@0 { ··· 87 87 88 88 &fec { 89 89 pinctrl-names = "default"; 90 - pinctrl-0 = <&pinctrl_enet_1>; 90 + pinctrl-0 = <&pinctrl_enet>; 91 91 phy-mode = "rgmii"; 92 92 phy-reset-gpios = <&gpio3 23 0>; 93 93 status = "okay"; ··· 97 97 status = "okay"; 98 98 clock-frequency = <100000>; 99 99 pinctrl-names = "default"; 100 - pinctrl-0 = <&pinctrl_i2c1_1>; 100 + pinctrl-0 = <&pinctrl_i2c1>; 101 101 102 102 codec: sgtl5000@0a { 103 103 compatible = "fsl,sgtl5000"; ··· 112 112 pinctrl-names = "default"; 113 113 pinctrl-0 = <&pinctrl_hog>; 114 114 115 - hog { 115 + imx6q-sabrelite { 116 116 pinctrl_hog: hoggrp { 117 117 fsl,pins = < 118 118 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 ··· 124 124 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 125 125 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x80000000 126 126 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 127 + >; 128 + }; 129 + 130 + pinctrl_audmux: audmuxgrp { 131 + fsl,pins = < 132 + MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x80000000 133 + MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x80000000 134 + MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x80000000 135 + MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000 136 + >; 137 + }; 138 + 139 + pinctrl_ecspi1: ecspi1grp { 140 + fsl,pins = < 141 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 142 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 143 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 144 + >; 145 + }; 146 + 147 + pinctrl_enet: enetgrp { 148 + fsl,pins = < 149 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 150 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 151 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 152 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 153 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 154 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 155 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 156 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 157 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 158 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 159 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 160 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 161 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 162 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 163 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 164 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 165 + >; 166 + }; 167 + 168 + pinctrl_i2c1: i2c1grp { 169 + fsl,pins = < 170 + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 171 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 172 + >; 173 + }; 174 + 175 + pinctrl_uart2: uart2grp { 176 + fsl,pins = < 177 + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 178 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 179 + >; 180 + }; 181 + 182 + pinctrl_usbotg: usbotggrp { 183 + fsl,pins = < 184 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 185 + >; 186 + }; 187 + 188 + pinctrl_usdhc3: usdhc3grp { 189 + fsl,pins = < 190 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 191 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 192 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 193 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 194 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 195 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 196 + >; 197 + }; 198 + 199 + pinctrl_usdhc4: usdhc4grp { 200 + fsl,pins = < 201 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 202 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 203 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 204 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 205 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 206 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 127 207 >; 128 208 }; 129 209 }; ··· 246 166 &uart2 { 247 167 status = "okay"; 248 168 pinctrl-names = "default"; 249 - pinctrl-0 = <&pinctrl_uart2_1>; 169 + pinctrl-0 = <&pinctrl_uart2>; 250 170 }; 251 171 252 172 &usbh1 { ··· 256 176 &usbotg { 257 177 vbus-supply = <&reg_usb_otg_vbus>; 258 178 pinctrl-names = "default"; 259 - pinctrl-0 = <&pinctrl_usbotg_1>; 179 + pinctrl-0 = <&pinctrl_usbotg>; 260 180 disable-over-current; 261 181 status = "okay"; 262 182 }; 263 183 264 184 &usdhc3 { 265 185 pinctrl-names = "default"; 266 - pinctrl-0 = <&pinctrl_usdhc3_2>; 186 + pinctrl-0 = <&pinctrl_usdhc3>; 267 187 cd-gpios = <&gpio7 0 0>; 268 188 wp-gpios = <&gpio7 1 0>; 269 189 vmmc-supply = <&reg_3p3v>; ··· 272 192 273 193 &usdhc4 { 274 194 pinctrl-names = "default"; 275 - pinctrl-0 = <&pinctrl_usdhc4_2>; 195 + pinctrl-0 = <&pinctrl_usdhc4>; 276 196 cd-gpios = <&gpio2 6 0>; 277 197 wp-gpios = <&gpio2 7 0>; 278 198 vmmc-supply = <&reg_3p3v>;

+54 -4

arch/arm/boot/dts/imx6q-sbc6x.dts

··· 17 17 }; 18 18 }; 19 19 20 + 20 21 &fec { 21 22 pinctrl-names = "default"; 22 - pinctrl-0 = <&pinctrl_enet_1>; 23 + pinctrl-0 = <&pinctrl_enet>; 23 24 phy-mode = "rgmii"; 24 25 status = "okay"; 25 26 }; 26 27 28 + &iomuxc { 29 + imx6q-sbc6x { 30 + pinctrl_enet: enetgrp { 31 + fsl,pins = < 32 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 33 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 34 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 35 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 36 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 37 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 38 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 39 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 40 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 41 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 42 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 43 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 44 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 45 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 46 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 47 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 48 + >; 49 + }; 50 + 51 + pinctrl_uart1: uart1grp { 52 + fsl,pins = < 53 + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 54 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 55 + >; 56 + }; 57 + 58 + pinctrl_usbotg: usbotggrp { 59 + fsl,pins = < 60 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 61 + >; 62 + }; 63 + 64 + pinctrl_usdhc3: usdhc3grp { 65 + fsl,pins = < 66 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 67 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 68 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 69 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 70 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 71 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 72 + >; 73 + }; 74 + }; 75 + }; 76 + 27 77 &uart1 { 28 78 pinctrl-names = "default"; 29 - pinctrl-0 = <&pinctrl_uart1_1>; 79 + pinctrl-0 = <&pinctrl_uart1>; 30 80 status = "okay"; 31 81 }; 32 82 33 83 &usbotg { 34 84 pinctrl-names = "default"; 35 - pinctrl-0 = <&pinctrl_usbotg_1>; 85 + pinctrl-0 = <&pinctrl_usbotg>; 36 86 disable-over-current; 37 87 status = "okay"; 38 88 }; 39 89 40 90 &usdhc3 { 41 91 pinctrl-names = "default"; 42 - pinctrl-0 = <&pinctrl_usdhc3_2>; 92 + pinctrl-0 = <&pinctrl_usdhc3>; 43 93 status = "okay"; 44 94 };

+24 -2

arch/arm/boot/dts/imx6q-udoo.dts

··· 21 21 }; 22 22 }; 23 23 24 + &iomuxc { 25 + imx6q-udoo { 26 + pinctrl_uart2: uart2grp { 27 + fsl,pins = < 28 + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 29 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 30 + >; 31 + }; 32 + 33 + pinctrl_usdhc3: usdhc3grp { 34 + fsl,pins = < 35 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 36 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 37 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 38 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 39 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 40 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 41 + >; 42 + }; 43 + }; 44 + }; 45 + 24 46 &sata { 25 47 status = "okay"; 26 48 }; 27 49 28 50 &uart2 { 29 51 pinctrl-names = "default"; 30 - pinctrl-0 = <&pinctrl_uart2_1>; 52 + pinctrl-0 = <&pinctrl_uart2>; 31 53 status = "okay"; 32 54 }; 33 55 34 56 &usdhc3 { 35 57 pinctrl-names = "default"; 36 - pinctrl-0 = <&pinctrl_usdhc3_2>; 58 + pinctrl-0 = <&pinctrl_usdhc3>; 37 59 non-removable; 38 60 status = "okay"; 39 61 };

+166 -12

arch/arm/boot/dts/imx6qdl-sabreauto.dtsi

··· 20 20 fsl,spi-num-chipselects = <1>; 21 21 cs-gpios = <&gpio3 19 0>; 22 22 pinctrl-names = "default"; 23 - pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_sabreauto>; 23 + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; 24 24 status = "disabled"; /* pin conflict with WEIM NOR */ 25 25 26 26 flash: m25p80@0 { ··· 34 34 35 35 &fec { 36 36 pinctrl-names = "default"; 37 - pinctrl-0 = <&pinctrl_enet_2>; 37 + pinctrl-0 = <&pinctrl_enet>; 38 38 phy-mode = "rgmii"; 39 39 status = "okay"; 40 40 }; 41 41 42 42 &gpmi { 43 43 pinctrl-names = "default"; 44 - pinctrl-0 = <&pinctrl_gpmi_nand_1>; 44 + pinctrl-0 = <&pinctrl_gpmi_nand>; 45 45 status = "okay"; 46 46 }; 47 47 ··· 49 49 pinctrl-names = "default"; 50 50 pinctrl-0 = <&pinctrl_hog>; 51 51 52 - hog { 52 + imx6qdl-sabreauto { 53 53 pinctrl_hog: hoggrp { 54 54 fsl,pins = < 55 55 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 ··· 57 57 MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059 58 58 >; 59 59 }; 60 - }; 61 60 62 - ecspi1 { 63 - pinctrl_ecspi1_sabreauto: ecspi1-sabreauto { 61 + pinctrl_ecspi1: ecspi1grp { 62 + fsl,pins = < 63 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 64 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 65 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 66 + >; 67 + }; 68 + 69 + pinctrl_ecspi1_cs: ecspi1cs { 64 70 fsl,pins = < 65 71 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 72 + >; 73 + }; 74 + 75 + pinctrl_enet: enetgrp { 76 + fsl,pins = < 77 + MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 78 + MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 79 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 80 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 81 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 82 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 83 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 84 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 85 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 86 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 87 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 88 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 89 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 90 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 91 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 92 + >; 93 + }; 94 + 95 + pinctrl_gpmi_nand: gpminandgrp { 96 + fsl,pins = < 97 + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 98 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 99 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 100 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 101 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 102 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 103 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 104 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 105 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 106 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 107 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 108 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 109 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 110 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 111 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 112 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 113 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 114 + >; 115 + }; 116 + 117 + pinctrl_uart4: uart4grp { 118 + fsl,pins = < 119 + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 120 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 121 + >; 122 + }; 123 + 124 + pinctrl_usdhc3: usdhc3grp { 125 + fsl,pins = < 126 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 127 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 128 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 129 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 130 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 131 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 132 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 133 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 134 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 135 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 136 + >; 137 + }; 138 + 139 + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 140 + fsl,pins = < 141 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 142 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 143 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 144 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 145 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 146 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 147 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 148 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 149 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 150 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 151 + >; 152 + }; 153 + 154 + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 155 + fsl,pins = < 156 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 157 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 158 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 159 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 160 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 161 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 162 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 163 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 164 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 165 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 166 + >; 167 + }; 168 + 169 + pinctrl_weim_cs0: weimcs0grp { 170 + fsl,pins = < 171 + MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 172 + >; 173 + }; 174 + 175 + pinctrl_weim_nor: weimnorgrp { 176 + fsl,pins = < 177 + MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 178 + MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 179 + MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 180 + MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 181 + MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 182 + MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 183 + MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 184 + MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 185 + MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 186 + MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 187 + MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 188 + MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 189 + MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 190 + MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 191 + MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 192 + MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 193 + MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 194 + MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 195 + MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 196 + MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 197 + MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 198 + MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 199 + MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 200 + MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 201 + MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 202 + MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 203 + MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 204 + MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 205 + MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 206 + MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 207 + MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 208 + MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 209 + MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 210 + MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 211 + MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 212 + MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 213 + MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 214 + MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 215 + MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 216 + MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 217 + MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 218 + MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 219 + MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 66 220 >; 67 221 }; 68 222 }; ··· 224 70 225 71 &uart4 { 226 72 pinctrl-names = "default"; 227 - pinctrl-0 = <&pinctrl_uart4_1>; 73 + pinctrl-0 = <&pinctrl_uart4>; 228 74 status = "okay"; 229 75 }; 230 76 231 77 &usdhc3 { 232 78 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 233 - pinctrl-0 = <&pinctrl_usdhc3_1>; 234 - pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>; 235 - pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>; 79 + pinctrl-0 = <&pinctrl_usdhc3>; 80 + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 81 + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 236 82 cd-gpios = <&gpio6 15 0>; 237 83 wp-gpios = <&gpio1 13 0>; 238 84 status = "okay"; ··· 240 86 241 87 &weim { 242 88 pinctrl-names = "default"; 243 - pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>; 89 + pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>; 244 90 #address-cells = <2>; 245 91 #size-cells = <1>; 246 92 ranges = <0 0 0x08000000 0x08000000>;

+112 -11

arch/arm/boot/dts/imx6qdl-sabresd.dtsi

··· 92 92 93 93 &audmux { 94 94 pinctrl-names = "default"; 95 - pinctrl-0 = <&pinctrl_audmux_2>; 95 + pinctrl-0 = <&pinctrl_audmux>; 96 96 status = "okay"; 97 97 }; 98 98 ··· 100 100 fsl,spi-num-chipselects = <1>; 101 101 cs-gpios = <&gpio4 9 0>; 102 102 pinctrl-names = "default"; 103 - pinctrl-0 = <&pinctrl_ecspi1_2>; 103 + pinctrl-0 = <&pinctrl_ecspi1>; 104 104 status = "okay"; 105 105 106 106 flash: m25p80@0 { ··· 114 114 115 115 &fec { 116 116 pinctrl-names = "default"; 117 - pinctrl-0 = <&pinctrl_enet_1>; 117 + pinctrl-0 = <&pinctrl_enet>; 118 118 phy-mode = "rgmii"; 119 119 phy-reset-gpios = <&gpio1 25 0>; 120 120 status = "okay"; ··· 123 123 &i2c1 { 124 124 clock-frequency = <100000>; 125 125 pinctrl-names = "default"; 126 - pinctrl-0 = <&pinctrl_i2c1_2>; 126 + pinctrl-0 = <&pinctrl_i2c1>; 127 127 status = "okay"; 128 128 129 129 codec: wm8962@1a { ··· 152 152 &i2c3 { 153 153 clock-frequency = <100000>; 154 154 pinctrl-names = "default"; 155 - pinctrl-0 = <&pinctrl_i2c3_2>; 155 + pinctrl-0 = <&pinctrl_i2c3>; 156 156 status = "okay"; 157 157 158 158 egalax_ts@04 { ··· 168 168 pinctrl-names = "default"; 169 169 pinctrl-0 = <&pinctrl_hog>; 170 170 171 - hog { 171 + imx6qdl-sabresd { 172 172 pinctrl_hog: hoggrp { 173 173 fsl,pins = < 174 174 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 ··· 182 182 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 183 183 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 184 184 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 185 + >; 186 + }; 187 + 188 + pinctrl_audmux: audmuxgrp { 189 + fsl,pins = < 190 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000 191 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000 192 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000 193 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000 194 + >; 195 + }; 196 + 197 + pinctrl_ecspi1: ecspi1grp { 198 + fsl,pins = < 199 + MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 200 + MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 201 + MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 202 + >; 203 + }; 204 + 205 + pinctrl_enet: enetgrp { 206 + fsl,pins = < 207 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 208 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 209 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 210 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 211 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 212 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 213 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 214 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 215 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 216 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 217 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 218 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 219 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 220 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 221 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 222 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 223 + >; 224 + }; 225 + 226 + pinctrl_i2c1: i2c1grp { 227 + fsl,pins = < 228 + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 229 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 230 + >; 231 + }; 232 + 233 + pinctrl_i2c3: i2c3grp { 234 + fsl,pins = < 235 + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 236 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 237 + >; 238 + }; 239 + 240 + pinctrl_pwm1: pwm1grp { 241 + fsl,pins = < 242 + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 243 + >; 244 + }; 245 + 246 + pinctrl_uart1: uart1grp { 247 + fsl,pins = < 248 + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 249 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 250 + >; 251 + }; 252 + 253 + pinctrl_usbotg: usbotggrp { 254 + fsl,pins = < 255 + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 256 + >; 257 + }; 258 + 259 + pinctrl_usdhc2: usdhc2grp { 260 + fsl,pins = < 261 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 262 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 263 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 264 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 265 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 266 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 267 + MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 268 + MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 269 + MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 270 + MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 271 + >; 272 + }; 273 + 274 + pinctrl_usdhc3: usdhc3grp { 275 + fsl,pins = < 276 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 277 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 278 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 279 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 280 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 281 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 282 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 283 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 284 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 285 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 185 286 >; 186 287 }; 187 288 }; ··· 315 214 316 215 &pwm1 { 317 216 pinctrl-names = "default"; 318 - pinctrl-0 = <&pinctrl_pwm0_1>; 217 + pinctrl-0 = <&pinctrl_pwm1>; 319 218 status = "okay"; 320 219 }; 321 220 ··· 326 225 327 226 &uart1 { 328 227 pinctrl-names = "default"; 329 - pinctrl-0 = <&pinctrl_uart1_1>; 228 + pinctrl-0 = <&pinctrl_uart1>; 330 229 status = "okay"; 331 230 }; 332 231 ··· 338 237 &usbotg { 339 238 vbus-supply = <&reg_usb_otg_vbus>; 340 239 pinctrl-names = "default"; 341 - pinctrl-0 = <&pinctrl_usbotg_2>; 240 + pinctrl-0 = <&pinctrl_usbotg>; 342 241 disable-over-current; 343 242 status = "okay"; 344 243 }; 345 244 346 245 &usdhc2 { 347 246 pinctrl-names = "default"; 348 - pinctrl-0 = <&pinctrl_usdhc2_1>; 247 + pinctrl-0 = <&pinctrl_usdhc2>; 349 248 bus-width = <8>; 350 249 cd-gpios = <&gpio2 2 0>; 351 250 wp-gpios = <&gpio2 3 0>; ··· 354 253 355 254 &usdhc3 { 356 255 pinctrl-names = "default"; 357 - pinctrl-0 = <&pinctrl_usdhc3_1>; 256 + pinctrl-0 = <&pinctrl_usdhc3>; 358 257 bus-width = <8>; 359 258 cd-gpios = <&gpio2 0 0>; 360 259 wp-gpios = <&gpio2 1 0>;

+109 -11

arch/arm/boot/dts/imx6qdl-wandboard.dtsi

··· 54 54 55 55 &audmux { 56 56 pinctrl-names = "default"; 57 - pinctrl-0 = <&pinctrl_audmux_2>; 57 + pinctrl-0 = <&pinctrl_audmux>; 58 58 status = "okay"; 59 59 }; 60 60 61 61 &i2c2 { 62 62 clock-frequency = <100000>; 63 63 pinctrl-names = "default"; 64 - pinctrl-0 = <&pinctrl_i2c2_2>; 64 + pinctrl-0 = <&pinctrl_i2c2>; 65 65 status = "okay"; 66 66 67 67 codec: sgtl5000@0a { ··· 77 77 pinctrl-names = "default"; 78 78 pinctrl-0 = <&pinctrl_hog>; 79 79 80 - hog { 80 + imx6qdl-wandboard { 81 81 pinctrl_hog: hoggrp { 82 82 fsl,pins = < 83 83 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 ··· 91 91 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 92 92 >; 93 93 }; 94 + 95 + pinctrl_audmux: audmuxgrp { 96 + fsl,pins = < 97 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000 98 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000 99 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000 100 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000 101 + >; 102 + }; 103 + 104 + pinctrl_enet: enetgrp { 105 + fsl,pins = < 106 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 107 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 108 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 109 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 110 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 111 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 112 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 113 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 114 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 115 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 116 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 117 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 118 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 119 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 120 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 121 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 122 + >; 123 + }; 124 + 125 + pinctrl_i2c2: i2c2grp { 126 + fsl,pins = < 127 + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 128 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 129 + >; 130 + }; 131 + 132 + pinctrl_spdif: spdifgrp { 133 + fsl,pins = < 134 + MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0 135 + >; 136 + }; 137 + 138 + pinctrl_uart1: uart1grp { 139 + fsl,pins = < 140 + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 141 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 142 + >; 143 + }; 144 + 145 + pinctrl_uart3: uart3grp { 146 + fsl,pins = < 147 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 148 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 149 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 150 + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 151 + >; 152 + }; 153 + 154 + pinctrl_usbotg: usbotggrp { 155 + fsl,pins = < 156 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 157 + >; 158 + }; 159 + 160 + pinctrl_usdhc1: usdhc1grp { 161 + fsl,pins = < 162 + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 163 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 164 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 165 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 166 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 167 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 168 + >; 169 + }; 170 + 171 + pinctrl_usdhc2: usdhc2grp { 172 + fsl,pins = < 173 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 174 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 175 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 176 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 177 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 178 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 179 + >; 180 + }; 181 + 182 + pinctrl_usdhc3: usdhc3grp { 183 + fsl,pins = < 184 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 185 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 186 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 187 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 188 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 189 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 190 + >; 191 + }; 94 192 }; 95 193 }; 96 194 97 195 &fec { 98 196 pinctrl-names = "default"; 99 - pinctrl-0 = <&pinctrl_enet_1>; 197 + pinctrl-0 = <&pinctrl_enet>; 100 198 phy-mode = "rgmii"; 101 199 phy-reset-gpios = <&gpio3 29 0>; 102 200 status = "okay"; ··· 202 104 203 105 &spdif { 204 106 pinctrl-names = "default"; 205 - pinctrl-0 = <&pinctrl_spdif_3>; 107 + pinctrl-0 = <&pinctrl_spdif>; 206 108 status = "okay"; 207 109 }; 208 110 ··· 213 115 214 116 &uart1 { 215 117 pinctrl-names = "default"; 216 - pinctrl-0 = <&pinctrl_uart1_1>; 118 + pinctrl-0 = <&pinctrl_uart1>; 217 119 status = "okay"; 218 120 }; 219 121 220 122 &uart3 { 221 123 pinctrl-names = "default"; 222 - pinctrl-0 = <&pinctrl_uart3_2>; 124 + pinctrl-0 = <&pinctrl_uart3>; 223 125 fsl,uart-has-rtscts; 224 126 status = "okay"; 225 127 }; ··· 230 132 231 133 &usbotg { 232 134 pinctrl-names = "default"; 233 - pinctrl-0 = <&pinctrl_usbotg_1>; 135 + pinctrl-0 = <&pinctrl_usbotg>; 234 136 disable-over-current; 235 137 dr_mode = "peripheral"; 236 138 status = "okay"; ··· 238 140 239 141 &usdhc1 { 240 142 pinctrl-names = "default"; 241 - pinctrl-0 = <&pinctrl_usdhc1_2>; 143 + pinctrl-0 = <&pinctrl_usdhc1>; 242 144 cd-gpios = <&gpio1 2 0>; 243 145 status = "okay"; 244 146 }; 245 147 246 148 &usdhc2 { 247 149 pinctrl-names = "default"; 248 - pinctrl-0 = <&pinctrl_usdhc2_2>; 150 + pinctrl-0 = <&pinctrl_usdhc2>; 249 151 non-removable; 250 152 status = "okay"; 251 153 }; 252 154 253 155 &usdhc3 { 254 156 pinctrl-names = "default"; 255 - pinctrl-0 = <&pinctrl_usdhc3_2>; 157 + pinctrl-0 = <&pinctrl_usdhc3>; 256 158 cd-gpios = <&gpio3 9 0>; 257 159 status = "okay"; 258 160 };

-738

arch/arm/boot/dts/imx6qdl.dtsi

··· 612 612 iomuxc: iomuxc@020e0000 { 613 613 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; 614 614 reg = <0x020e0000 0x4000>; 615 - 616 - audmux { 617 - pinctrl_audmux_1: audmux-1 { 618 - fsl,pins = < 619 - MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x80000000 620 - MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x80000000 621 - MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x80000000 622 - MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000 623 - >; 624 - }; 625 - 626 - pinctrl_audmux_2: audmux-2 { 627 - fsl,pins = < 628 - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000 629 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000 630 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000 631 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000 632 - >; 633 - }; 634 - 635 - pinctrl_audmux_3: audmux-3 { 636 - fsl,pins = < 637 - MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x80000000 638 - MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000 639 - MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x80000000 640 - >; 641 - }; 642 - }; 643 - 644 - ecspi1 { 645 - pinctrl_ecspi1_1: ecspi1grp-1 { 646 - fsl,pins = < 647 - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 648 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 649 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 650 - >; 651 - }; 652 - 653 - pinctrl_ecspi1_2: ecspi1grp-2 { 654 - fsl,pins = < 655 - MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 656 - MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 657 - MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 658 - >; 659 - }; 660 - }; 661 - 662 - ecspi3 { 663 - pinctrl_ecspi3_1: ecspi3grp-1 { 664 - fsl,pins = < 665 - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 666 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 667 - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 668 - >; 669 - }; 670 - }; 671 - 672 - enet { 673 - pinctrl_enet_1: enetgrp-1 { 674 - fsl,pins = < 675 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 676 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 677 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 678 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 679 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 680 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 681 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 682 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 683 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 684 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 685 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 686 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 687 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 688 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 689 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 690 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 691 - >; 692 - }; 693 - 694 - pinctrl_enet_2: enetgrp-2 { 695 - fsl,pins = < 696 - MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 697 - MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 698 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 699 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 700 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 701 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 702 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 703 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 704 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 705 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 706 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 707 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 708 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 709 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 710 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 711 - >; 712 - }; 713 - 714 - pinctrl_enet_3: enetgrp-3 { 715 - fsl,pins = < 716 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 717 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 718 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 719 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 720 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 721 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 722 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 723 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 724 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 725 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 726 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 727 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 728 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 729 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 730 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 731 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 732 - >; 733 - }; 734 - }; 735 - 736 - esai { 737 - pinctrl_esai_1: esaigrp-1 { 738 - fsl,pins = < 739 - MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030 740 - MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 741 - MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 742 - MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 743 - MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030 744 - MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 745 - MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 746 - MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030 747 - MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 748 - >; 749 - }; 750 - 751 - pinctrl_esai_2: esaigrp-2 { 752 - fsl,pins = < 753 - MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 754 - MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 755 - MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 756 - MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030 757 - MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 758 - MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 759 - MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030 760 - MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 761 - MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030 762 - MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030 763 - >; 764 - }; 765 - }; 766 - 767 - flexcan1 { 768 - pinctrl_flexcan1_1: flexcan1grp-1 { 769 - fsl,pins = < 770 - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 771 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 772 - >; 773 - }; 774 - 775 - pinctrl_flexcan1_2: flexcan1grp-2 { 776 - fsl,pins = < 777 - MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000 778 - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 779 - >; 780 - }; 781 - }; 782 - 783 - flexcan2 { 784 - pinctrl_flexcan2_1: flexcan2grp-1 { 785 - fsl,pins = < 786 - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000 787 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000 788 - >; 789 - }; 790 - }; 791 - 792 - gpmi-nand { 793 - pinctrl_gpmi_nand_1: gpmi-nand-1 { 794 - fsl,pins = < 795 - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 796 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 797 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 798 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 799 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 800 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 801 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 802 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 803 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 804 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 805 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 806 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 807 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 808 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 809 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 810 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 811 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 812 - >; 813 - }; 814 - }; 815 - 816 - hdmi_hdcp { 817 - pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 { 818 - fsl,pins = < 819 - MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 820 - MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 821 - >; 822 - }; 823 - 824 - pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 { 825 - fsl,pins = < 826 - MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 827 - MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1 828 - >; 829 - }; 830 - 831 - pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 { 832 - fsl,pins = < 833 - MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 834 - MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 835 - >; 836 - }; 837 - }; 838 - 839 - hdmi_cec { 840 - pinctrl_hdmi_cec_1: hdmicecgrp-1 { 841 - fsl,pins = < 842 - MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 843 - >; 844 - }; 845 - 846 - pinctrl_hdmi_cec_2: hdmicecgrp-2 { 847 - fsl,pins = < 848 - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 849 - >; 850 - }; 851 - }; 852 - 853 - i2c1 { 854 - pinctrl_i2c1_1: i2c1grp-1 { 855 - fsl,pins = < 856 - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 857 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 858 - >; 859 - }; 860 - 861 - pinctrl_i2c1_2: i2c1grp-2 { 862 - fsl,pins = < 863 - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 864 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 865 - >; 866 - }; 867 - }; 868 - 869 - i2c2 { 870 - pinctrl_i2c2_1: i2c2grp-1 { 871 - fsl,pins = < 872 - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 873 - MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 874 - >; 875 - }; 876 - 877 - pinctrl_i2c2_2: i2c2grp-2 { 878 - fsl,pins = < 879 - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 880 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 881 - >; 882 - }; 883 - 884 - pinctrl_i2c2_3: i2c2grp-3 { 885 - fsl,pins = < 886 - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 887 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 888 - >; 889 - }; 890 - }; 891 - 892 - i2c3 { 893 - pinctrl_i2c3_1: i2c3grp-1 { 894 - fsl,pins = < 895 - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 896 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 897 - >; 898 - }; 899 - 900 - pinctrl_i2c3_2: i2c3grp-2 { 901 - fsl,pins = < 902 - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 903 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 904 - >; 905 - }; 906 - 907 - pinctrl_i2c3_3: i2c3grp-3 { 908 - fsl,pins = < 909 - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 910 - MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 911 - >; 912 - }; 913 - 914 - pinctrl_i2c3_4: i2c3grp-4 { 915 - fsl,pins = < 916 - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 917 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 918 - >; 919 - }; 920 - }; 921 - 922 - ipu1 { 923 - pinctrl_ipu1_1: ipu1grp-1 { 924 - fsl,pins = < 925 - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 926 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 927 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 928 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 929 - MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000 930 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 931 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 932 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 933 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 934 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 935 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 936 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 937 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 938 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 939 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 940 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 941 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 942 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 943 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 944 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 945 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 946 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 947 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 948 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 949 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 950 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 951 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 952 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 953 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 954 - >; 955 - }; 956 - 957 - pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */ 958 - fsl,pins = < 959 - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 960 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 961 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 962 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 963 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 964 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 965 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 966 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 967 - MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000 968 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 969 - MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 970 - MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 971 - >; 972 - }; 973 - 974 - pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */ 975 - fsl,pins = < 976 - MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000 977 - MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000 978 - MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000 979 - MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000 980 - MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000 981 - MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000 982 - MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000 983 - MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000 984 - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 985 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 986 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 987 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 988 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 989 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 990 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 991 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 992 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 993 - MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 994 - MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 995 - >; 996 - }; 997 - }; 998 - 999 - mlb { 1000 - pinctrl_mlb_1: mlbgrp-1 { 1001 - fsl,pins = < 1002 - MX6QDL_PAD_GPIO_3__MLB_CLK 0x71 1003 - MX6QDL_PAD_GPIO_6__MLB_SIG 0x71 1004 - MX6QDL_PAD_GPIO_2__MLB_DATA 0x71 1005 - >; 1006 - }; 1007 - 1008 - pinctrl_mlb_2: mlbgrp-2 { 1009 - fsl,pins = < 1010 - MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71 1011 - MX6QDL_PAD_GPIO_6__MLB_SIG 0x71 1012 - MX6QDL_PAD_GPIO_2__MLB_DATA 0x71 1013 - >; 1014 - }; 1015 - }; 1016 - 1017 - pwm0 { 1018 - pinctrl_pwm0_1: pwm0grp-1 { 1019 - fsl,pins = < 1020 - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 1021 - >; 1022 - }; 1023 - }; 1024 - 1025 - pwm3 { 1026 - pinctrl_pwm3_1: pwm3grp-1 { 1027 - fsl,pins = < 1028 - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 1029 - >; 1030 - }; 1031 - }; 1032 - 1033 - spdif { 1034 - pinctrl_spdif_1: spdifgrp-1 { 1035 - fsl,pins = < 1036 - MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0 1037 - >; 1038 - }; 1039 - 1040 - pinctrl_spdif_2: spdifgrp-2 { 1041 - fsl,pins = < 1042 - MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 1043 - MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 1044 - >; 1045 - }; 1046 - 1047 - pinctrl_spdif_3: spdifgrp-3 { 1048 - fsl,pins = < 1049 - MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0 1050 - >; 1051 - }; 1052 - }; 1053 - 1054 - uart1 { 1055 - pinctrl_uart1_1: uart1grp-1 { 1056 - fsl,pins = < 1057 - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 1058 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 1059 - >; 1060 - }; 1061 - }; 1062 - 1063 - uart2 { 1064 - pinctrl_uart2_1: uart2grp-1 { 1065 - fsl,pins = < 1066 - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 1067 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 1068 - >; 1069 - }; 1070 - 1071 - pinctrl_uart2_2: uart2grp-2 { /* DTE mode */ 1072 - fsl,pins = < 1073 - MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 1074 - MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 1075 - MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 1076 - MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 1077 - >; 1078 - }; 1079 - }; 1080 - 1081 - uart3 { 1082 - pinctrl_uart3_1: uart3grp-1 { 1083 - fsl,pins = < 1084 - MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 1085 - MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 1086 - MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 1087 - MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 1088 - >; 1089 - }; 1090 - 1091 - pinctrl_uart3_2: uart3grp-2 { 1092 - fsl,pins = < 1093 - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 1094 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 1095 - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 1096 - MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 1097 - >; 1098 - }; 1099 - }; 1100 - 1101 - uart4 { 1102 - pinctrl_uart4_1: uart4grp-1 { 1103 - fsl,pins = < 1104 - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 1105 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 1106 - >; 1107 - }; 1108 - }; 1109 - 1110 - usbotg { 1111 - pinctrl_usbotg_1: usbotggrp-1 { 1112 - fsl,pins = < 1113 - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 1114 - >; 1115 - }; 1116 - 1117 - pinctrl_usbotg_2: usbotggrp-2 { 1118 - fsl,pins = < 1119 - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 1120 - >; 1121 - }; 1122 - }; 1123 - 1124 - usbh2 { 1125 - pinctrl_usbh2_1: usbh2grp-1 { 1126 - fsl,pins = < 1127 - MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030 1128 - MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030 1129 - >; 1130 - }; 1131 - 1132 - pinctrl_usbh2_2: usbh2grp-2 { 1133 - fsl,pins = < 1134 - MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030 1135 - >; 1136 - }; 1137 - }; 1138 - 1139 - usbh3 { 1140 - pinctrl_usbh3_1: usbh3grp-1 { 1141 - fsl,pins = < 1142 - MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030 1143 - MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030 1144 - >; 1145 - }; 1146 - 1147 - pinctrl_usbh3_2: usbh3grp-2 { 1148 - fsl,pins = < 1149 - MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030 1150 - >; 1151 - }; 1152 - }; 1153 - 1154 - usdhc1 { 1155 - pinctrl_usdhc1_1: usdhc1grp-1 { 1156 - fsl,pins = < 1157 - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 1158 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 1159 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 1160 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 1161 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 1162 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 1163 - MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059 1164 - MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059 1165 - MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059 1166 - MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059 1167 - >; 1168 - }; 1169 - 1170 - pinctrl_usdhc1_2: usdhc1grp-2 { 1171 - fsl,pins = < 1172 - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 1173 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 1174 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 1175 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 1176 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 1177 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 1178 - >; 1179 - }; 1180 - }; 1181 - 1182 - usdhc2 { 1183 - pinctrl_usdhc2_1: usdhc2grp-1 { 1184 - fsl,pins = < 1185 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 1186 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 1187 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 1188 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 1189 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 1190 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 1191 - MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 1192 - MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 1193 - MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 1194 - MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 1195 - >; 1196 - }; 1197 - 1198 - pinctrl_usdhc2_2: usdhc2grp-2 { 1199 - fsl,pins = < 1200 - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 1201 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 1202 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 1203 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 1204 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 1205 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 1206 - >; 1207 - }; 1208 - }; 1209 - 1210 - usdhc3 { 1211 - pinctrl_usdhc3_1: usdhc3grp-1 { 1212 - fsl,pins = < 1213 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 1214 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 1215 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 1216 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 1217 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 1218 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 1219 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 1220 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 1221 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 1222 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 1223 - >; 1224 - }; 1225 - 1226 - pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { /* 100Mhz */ 1227 - fsl,pins = < 1228 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 1229 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 1230 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 1231 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 1232 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 1233 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 1234 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 1235 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 1236 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 1237 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 1238 - >; 1239 - }; 1240 - 1241 - pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { /* 200Mhz */ 1242 - fsl,pins = < 1243 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 1244 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 1245 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 1246 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 1247 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 1248 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 1249 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 1250 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 1251 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 1252 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 1253 - >; 1254 - }; 1255 - 1256 - pinctrl_usdhc3_2: usdhc3grp-2 { 1257 - fsl,pins = < 1258 - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 1259 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 1260 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 1261 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 1262 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 1263 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 1264 - >; 1265 - }; 1266 - }; 1267 - 1268 - usdhc4 { 1269 - pinctrl_usdhc4_1: usdhc4grp-1 { 1270 - fsl,pins = < 1271 - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 1272 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 1273 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 1274 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 1275 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 1276 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 1277 - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 1278 - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 1279 - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 1280 - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 1281 - >; 1282 - }; 1283 - 1284 - pinctrl_usdhc4_2: usdhc4grp-2 { 1285 - fsl,pins = < 1286 - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 1287 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 1288 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 1289 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 1290 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 1291 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 1292 - >; 1293 - }; 1294 - }; 1295 - 1296 - weim { 1297 - pinctrl_weim_cs0_1: weim_cs0grp-1 { 1298 - fsl,pins = < 1299 - MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 1300 - >; 1301 - }; 1302 - 1303 - pinctrl_weim_nor_1: weim_norgrp-1 { 1304 - fsl,pins = < 1305 - MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 1306 - MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 1307 - MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 1308 - /* data */ 1309 - MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 1310 - MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 1311 - MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 1312 - MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 1313 - MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 1314 - MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 1315 - MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 1316 - MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 1317 - MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 1318 - MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 1319 - MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 1320 - MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 1321 - MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 1322 - MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 1323 - MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 1324 - MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 1325 - /* address */ 1326 - MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 1327 - MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 1328 - MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 1329 - MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 1330 - MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 1331 - MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 1332 - MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 1333 - MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 1334 - MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 1335 - MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 1336 - MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 1337 - MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 1338 - MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 1339 - MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 1340 - MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 1341 - MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 1342 - MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 1343 - MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 1344 - MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 1345 - MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 1346 - MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 1347 - MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 1348 - MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 1349 - MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 1350 - >; 1351 - }; 1352 - }; 1353 615 }; 1354 616 1355 617 ldb: ldb@020e0008 {