r8169: factor out PHY configuration to r8169_phy_config.c

+1 -1

drivers/net/ethernet/realtek/Makefile

··· 6 6 obj-$(CONFIG_8139CP) += 8139cp.o 7 7 obj-$(CONFIG_8139TOO) += 8139too.o 8 8 obj-$(CONFIG_ATP) += atp.o 9 - r8169-objs += r8169_main.o r8169_firmware.o 9 + r8169-objs += r8169_main.o r8169_firmware.o r8169_phy_config.o 10 10 obj-$(CONFIG_R8169) += r8169.o

-1291

drivers/net/ethernet/realtek/r8169_main.c

··· 636 636 }; 637 637 638 638 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 639 - typedef void (*rtl_phy_cfg_fct)(struct rtl8169_private *tp, 640 - struct phy_device *phydev); 641 639 642 640 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 643 641 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); ··· 1020 1022 default: 1021 1023 return r8169_mdio_read(tp, location); 1022 1024 } 1023 - } 1024 - 1025 - static void r8168d_modify_extpage(struct phy_device *phydev, int extpage, 1026 - int reg, u16 mask, u16 val) 1027 - { 1028 - int oldpage = phy_select_page(phydev, 0x0007); 1029 - 1030 - __phy_write(phydev, 0x1e, extpage); 1031 - __phy_modify(phydev, reg, mask, val); 1032 - 1033 - phy_restore_page(phydev, oldpage, 0); 1034 - } 1035 - 1036 - static void r8168d_phy_param(struct phy_device *phydev, u16 parm, 1037 - u16 mask, u16 val) 1038 - { 1039 - int oldpage = phy_select_page(phydev, 0x0005); 1040 - 1041 - __phy_write(phydev, 0x05, parm); 1042 - __phy_modify(phydev, 0x06, mask, val); 1043 - 1044 - phy_restore_page(phydev, oldpage, 0); 1045 - } 1046 - 1047 - static void r8168g_phy_param(struct phy_device *phydev, u16 parm, 1048 - u16 mask, u16 val) 1049 - { 1050 - int oldpage = phy_select_page(phydev, 0x0a43); 1051 - 1052 - __phy_write(phydev, 0x13, parm); 1053 - __phy_modify(phydev, 0x14, mask, val); 1054 - 1055 - phy_restore_page(phydev, oldpage, 0); 1056 1025 } 1057 1026 1058 1027 DECLARE_RTL_COND(rtl_ephyar_cond) ··· 2166 2201 } 2167 2202 } 2168 2203 2169 - struct phy_reg { 2170 - u16 reg; 2171 - u16 val; 2172 - }; 2173 - 2174 - static void __rtl_writephy_batch(struct phy_device *phydev, 2175 - const struct phy_reg *regs, int len) 2176 - { 2177 - phy_lock_mdio_bus(phydev); 2178 - 2179 - while (len-- > 0) { 2180 - __phy_write(phydev, regs->reg, regs->val); 2181 - regs++; 2182 - } 2183 - 2184 - phy_unlock_mdio_bus(phydev); 2185 - } 2186 - 2187 - #define rtl_writephy_batch(p, a) __rtl_writephy_batch(p, a, ARRAY_SIZE(a)) 2188 - 2189 2204 static void rtl_release_firmware(struct rtl8169_private *tp) 2190 2205 { 2191 2206 if (tp->rtl_fw) { ··· 2197 2252 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2198 2253 } 2199 2254 2200 - static void rtl8168f_config_eee_phy(struct phy_device *phydev) 2201 - { 2202 - r8168d_modify_extpage(phydev, 0x0020, 0x15, 0, BIT(8)); 2203 - r8168d_phy_param(phydev, 0x8b85, 0, BIT(13)); 2204 - } 2205 - 2206 - static void rtl8168g_config_eee_phy(struct phy_device *phydev) 2207 - { 2208 - phy_modify_paged(phydev, 0x0a43, 0x11, 0, BIT(4)); 2209 - } 2210 - 2211 - static void rtl8168h_config_eee_phy(struct phy_device *phydev) 2212 - { 2213 - rtl8168g_config_eee_phy(phydev); 2214 - 2215 - phy_modify_paged(phydev, 0xa4a, 0x11, 0x0000, 0x0200); 2216 - phy_modify_paged(phydev, 0xa42, 0x14, 0x0000, 0x0080); 2217 - } 2218 - 2219 - static void rtl8125_config_eee_phy(struct phy_device *phydev) 2220 - { 2221 - rtl8168h_config_eee_phy(phydev); 2222 - 2223 - phy_modify_paged(phydev, 0xa6d, 0x12, 0x0001, 0x0000); 2224 - phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000); 2225 - } 2226 - 2227 - static void rtl8169s_hw_phy_config(struct rtl8169_private *tp, 2228 - struct phy_device *phydev) 2229 - { 2230 - static const struct phy_reg phy_reg_init[] = { 2231 - { 0x1f, 0x0001 }, 2232 - { 0x06, 0x006e }, 2233 - { 0x08, 0x0708 }, 2234 - { 0x15, 0x4000 }, 2235 - { 0x18, 0x65c7 }, 2236 - 2237 - { 0x1f, 0x0001 }, 2238 - { 0x03, 0x00a1 }, 2239 - { 0x02, 0x0008 }, 2240 - { 0x01, 0x0120 }, 2241 - { 0x00, 0x1000 }, 2242 - { 0x04, 0x0800 }, 2243 - { 0x04, 0x0000 }, 2244 - 2245 - { 0x03, 0xff41 }, 2246 - { 0x02, 0xdf60 }, 2247 - { 0x01, 0x0140 }, 2248 - { 0x00, 0x0077 }, 2249 - { 0x04, 0x7800 }, 2250 - { 0x04, 0x7000 }, 2251 - 2252 - { 0x03, 0x802f }, 2253 - { 0x02, 0x4f02 }, 2254 - { 0x01, 0x0409 }, 2255 - { 0x00, 0xf0f9 }, 2256 - { 0x04, 0x9800 }, 2257 - { 0x04, 0x9000 }, 2258 - 2259 - { 0x03, 0xdf01 }, 2260 - { 0x02, 0xdf20 }, 2261 - { 0x01, 0xff95 }, 2262 - { 0x00, 0xba00 }, 2263 - { 0x04, 0xa800 }, 2264 - { 0x04, 0xa000 }, 2265 - 2266 - { 0x03, 0xff41 }, 2267 - { 0x02, 0xdf20 }, 2268 - { 0x01, 0x0140 }, 2269 - { 0x00, 0x00bb }, 2270 - { 0x04, 0xb800 }, 2271 - { 0x04, 0xb000 }, 2272 - 2273 - { 0x03, 0xdf41 }, 2274 - { 0x02, 0xdc60 }, 2275 - { 0x01, 0x6340 }, 2276 - { 0x00, 0x007d }, 2277 - { 0x04, 0xd800 }, 2278 - { 0x04, 0xd000 }, 2279 - 2280 - { 0x03, 0xdf01 }, 2281 - { 0x02, 0xdf20 }, 2282 - { 0x01, 0x100a }, 2283 - { 0x00, 0xa0ff }, 2284 - { 0x04, 0xf800 }, 2285 - { 0x04, 0xf000 }, 2286 - 2287 - { 0x1f, 0x0000 }, 2288 - { 0x0b, 0x0000 }, 2289 - { 0x00, 0x9200 } 2290 - }; 2291 - 2292 - rtl_writephy_batch(phydev, phy_reg_init); 2293 - } 2294 - 2295 - static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp, 2296 - struct phy_device *phydev) 2297 - { 2298 - phy_write_paged(phydev, 0x0002, 0x01, 0x90d0); 2299 - } 2300 - 2301 - static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp, 2302 - struct phy_device *phydev) 2303 - { 2304 - static const struct phy_reg phy_reg_init[] = { 2305 - { 0x1f, 0x0001 }, 2306 - { 0x04, 0x0000 }, 2307 - { 0x03, 0x00a1 }, 2308 - { 0x02, 0x0008 }, 2309 - { 0x01, 0x0120 }, 2310 - { 0x00, 0x1000 }, 2311 - { 0x04, 0x0800 }, 2312 - { 0x04, 0x9000 }, 2313 - { 0x03, 0x802f }, 2314 - { 0x02, 0x4f02 }, 2315 - { 0x01, 0x0409 }, 2316 - { 0x00, 0xf099 }, 2317 - { 0x04, 0x9800 }, 2318 - { 0x04, 0xa000 }, 2319 - { 0x03, 0xdf01 }, 2320 - { 0x02, 0xdf20 }, 2321 - { 0x01, 0xff95 }, 2322 - { 0x00, 0xba00 }, 2323 - { 0x04, 0xa800 }, 2324 - { 0x04, 0xf000 }, 2325 - { 0x03, 0xdf01 }, 2326 - { 0x02, 0xdf20 }, 2327 - { 0x01, 0x101a }, 2328 - { 0x00, 0xa0ff }, 2329 - { 0x04, 0xf800 }, 2330 - { 0x04, 0x0000 }, 2331 - { 0x1f, 0x0000 }, 2332 - 2333 - { 0x1f, 0x0001 }, 2334 - { 0x10, 0xf41b }, 2335 - { 0x14, 0xfb54 }, 2336 - { 0x18, 0xf5c7 }, 2337 - { 0x1f, 0x0000 }, 2338 - 2339 - { 0x1f, 0x0001 }, 2340 - { 0x17, 0x0cc0 }, 2341 - { 0x1f, 0x0000 } 2342 - }; 2343 - 2344 - rtl_writephy_batch(phydev, phy_reg_init); 2345 - } 2346 - 2347 - static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp, 2348 - struct phy_device *phydev) 2349 - { 2350 - static const struct phy_reg phy_reg_init[] = { 2351 - { 0x1f, 0x0001 }, 2352 - { 0x04, 0x0000 }, 2353 - { 0x03, 0x00a1 }, 2354 - { 0x02, 0x0008 }, 2355 - { 0x01, 0x0120 }, 2356 - { 0x00, 0x1000 }, 2357 - { 0x04, 0x0800 }, 2358 - { 0x04, 0x9000 }, 2359 - { 0x03, 0x802f }, 2360 - { 0x02, 0x4f02 }, 2361 - { 0x01, 0x0409 }, 2362 - { 0x00, 0xf099 }, 2363 - { 0x04, 0x9800 }, 2364 - { 0x04, 0xa000 }, 2365 - { 0x03, 0xdf01 }, 2366 - { 0x02, 0xdf20 }, 2367 - { 0x01, 0xff95 }, 2368 - { 0x00, 0xba00 }, 2369 - { 0x04, 0xa800 }, 2370 - { 0x04, 0xf000 }, 2371 - { 0x03, 0xdf01 }, 2372 - { 0x02, 0xdf20 }, 2373 - { 0x01, 0x101a }, 2374 - { 0x00, 0xa0ff }, 2375 - { 0x04, 0xf800 }, 2376 - { 0x04, 0x0000 }, 2377 - { 0x1f, 0x0000 }, 2378 - 2379 - { 0x1f, 0x0001 }, 2380 - { 0x0b, 0x8480 }, 2381 - { 0x1f, 0x0000 }, 2382 - 2383 - { 0x1f, 0x0001 }, 2384 - { 0x18, 0x67c7 }, 2385 - { 0x04, 0x2000 }, 2386 - { 0x03, 0x002f }, 2387 - { 0x02, 0x4360 }, 2388 - { 0x01, 0x0109 }, 2389 - { 0x00, 0x3022 }, 2390 - { 0x04, 0x2800 }, 2391 - { 0x1f, 0x0000 }, 2392 - 2393 - { 0x1f, 0x0001 }, 2394 - { 0x17, 0x0cc0 }, 2395 - { 0x1f, 0x0000 } 2396 - }; 2397 - 2398 - rtl_writephy_batch(phydev, phy_reg_init); 2399 - } 2400 - 2401 - static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp, 2402 - struct phy_device *phydev) 2403 - { 2404 - phy_write(phydev, 0x1f, 0x0001); 2405 - phy_set_bits(phydev, 0x16, BIT(0)); 2406 - phy_write(phydev, 0x10, 0xf41b); 2407 - phy_write(phydev, 0x1f, 0x0000); 2408 - } 2409 - 2410 - static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp, 2411 - struct phy_device *phydev) 2412 - { 2413 - phy_write_paged(phydev, 0x0001, 0x10, 0xf41b); 2414 - } 2415 - 2416 - static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp, 2417 - struct phy_device *phydev) 2418 - { 2419 - phy_write(phydev, 0x1d, 0x0f00); 2420 - phy_write_paged(phydev, 0x0002, 0x0c, 0x1ec8); 2421 - } 2422 - 2423 - static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp, 2424 - struct phy_device *phydev) 2425 - { 2426 - phy_set_bits(phydev, 0x14, BIT(5)); 2427 - phy_set_bits(phydev, 0x0d, BIT(5)); 2428 - phy_write_paged(phydev, 0x0001, 0x1d, 0x3d98); 2429 - } 2430 - 2431 - static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp, 2432 - struct phy_device *phydev) 2433 - { 2434 - static const struct phy_reg phy_reg_init[] = { 2435 - { 0x1f, 0x0001 }, 2436 - { 0x12, 0x2300 }, 2437 - { 0x1f, 0x0002 }, 2438 - { 0x00, 0x88d4 }, 2439 - { 0x01, 0x82b1 }, 2440 - { 0x03, 0x7002 }, 2441 - { 0x08, 0x9e30 }, 2442 - { 0x09, 0x01f0 }, 2443 - { 0x0a, 0x5500 }, 2444 - { 0x0c, 0x00c8 }, 2445 - { 0x1f, 0x0003 }, 2446 - { 0x12, 0xc096 }, 2447 - { 0x16, 0x000a }, 2448 - { 0x1f, 0x0000 }, 2449 - { 0x1f, 0x0000 }, 2450 - { 0x09, 0x2000 }, 2451 - { 0x09, 0x0000 } 2452 - }; 2453 - 2454 - rtl_writephy_batch(phydev, phy_reg_init); 2455 - 2456 - phy_set_bits(phydev, 0x14, BIT(5)); 2457 - phy_set_bits(phydev, 0x0d, BIT(5)); 2458 - } 2459 - 2460 - static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp, 2461 - struct phy_device *phydev) 2462 - { 2463 - static const struct phy_reg phy_reg_init[] = { 2464 - { 0x1f, 0x0001 }, 2465 - { 0x12, 0x2300 }, 2466 - { 0x03, 0x802f }, 2467 - { 0x02, 0x4f02 }, 2468 - { 0x01, 0x0409 }, 2469 - { 0x00, 0xf099 }, 2470 - { 0x04, 0x9800 }, 2471 - { 0x04, 0x9000 }, 2472 - { 0x1d, 0x3d98 }, 2473 - { 0x1f, 0x0002 }, 2474 - { 0x0c, 0x7eb8 }, 2475 - { 0x06, 0x0761 }, 2476 - { 0x1f, 0x0003 }, 2477 - { 0x16, 0x0f0a }, 2478 - { 0x1f, 0x0000 } 2479 - }; 2480 - 2481 - rtl_writephy_batch(phydev, phy_reg_init); 2482 - 2483 - phy_set_bits(phydev, 0x16, BIT(0)); 2484 - phy_set_bits(phydev, 0x14, BIT(5)); 2485 - phy_set_bits(phydev, 0x0d, BIT(5)); 2486 - } 2487 - 2488 - static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp, 2489 - struct phy_device *phydev) 2490 - { 2491 - static const struct phy_reg phy_reg_init[] = { 2492 - { 0x1f, 0x0001 }, 2493 - { 0x12, 0x2300 }, 2494 - { 0x1d, 0x3d98 }, 2495 - { 0x1f, 0x0002 }, 2496 - { 0x0c, 0x7eb8 }, 2497 - { 0x06, 0x5461 }, 2498 - { 0x1f, 0x0003 }, 2499 - { 0x16, 0x0f0a }, 2500 - { 0x1f, 0x0000 } 2501 - }; 2502 - 2503 - rtl_writephy_batch(phydev, phy_reg_init); 2504 - 2505 - phy_set_bits(phydev, 0x16, BIT(0)); 2506 - phy_set_bits(phydev, 0x14, BIT(5)); 2507 - phy_set_bits(phydev, 0x0d, BIT(5)); 2508 - } 2509 - 2510 - static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = { 2511 - /* Channel Estimation */ 2512 - { 0x1f, 0x0001 }, 2513 - { 0x06, 0x4064 }, 2514 - { 0x07, 0x2863 }, 2515 - { 0x08, 0x059c }, 2516 - { 0x09, 0x26b4 }, 2517 - { 0x0a, 0x6a19 }, 2518 - { 0x0b, 0xdcc8 }, 2519 - { 0x10, 0xf06d }, 2520 - { 0x14, 0x7f68 }, 2521 - { 0x18, 0x7fd9 }, 2522 - { 0x1c, 0xf0ff }, 2523 - { 0x1d, 0x3d9c }, 2524 - { 0x1f, 0x0003 }, 2525 - { 0x12, 0xf49f }, 2526 - { 0x13, 0x070b }, 2527 - { 0x1a, 0x05ad }, 2528 - { 0x14, 0x94c0 }, 2529 - 2530 - /* 2531 - * Tx Error Issue 2532 - * Enhance line driver power 2533 - */ 2534 - { 0x1f, 0x0002 }, 2535 - { 0x06, 0x5561 }, 2536 - { 0x1f, 0x0005 }, 2537 - { 0x05, 0x8332 }, 2538 - { 0x06, 0x5561 }, 2539 - 2540 - /* 2541 - * Can not link to 1Gbps with bad cable 2542 - * Decrease SNR threshold form 21.07dB to 19.04dB 2543 - */ 2544 - { 0x1f, 0x0001 }, 2545 - { 0x17, 0x0cc0 }, 2546 - 2547 - { 0x1f, 0x0000 }, 2548 - { 0x0d, 0xf880 } 2549 - }; 2550 - 2551 - static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = { 2552 - { 0x1f, 0x0002 }, 2553 - { 0x05, 0x669a }, 2554 - { 0x1f, 0x0005 }, 2555 - { 0x05, 0x8330 }, 2556 - { 0x06, 0x669a }, 2557 - { 0x1f, 0x0002 } 2558 - }; 2559 - 2560 - static void rtl8168d_apply_firmware_cond(struct rtl8169_private *tp, 2561 - struct phy_device *phydev, 2562 - u16 val) 2563 - { 2564 - u16 reg_val; 2565 - 2566 - phy_write(phydev, 0x1f, 0x0005); 2567 - phy_write(phydev, 0x05, 0x001b); 2568 - reg_val = phy_read(phydev, 0x06); 2569 - phy_write(phydev, 0x1f, 0x0000); 2570 - 2571 - if (reg_val != val) 2572 - phydev_warn(phydev, "chipset not ready for firmware\n"); 2573 - else 2574 - r8169_apply_firmware(tp); 2575 - } 2576 - 2577 - static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp, 2578 - struct phy_device *phydev) 2579 - { 2580 - rtl_writephy_batch(phydev, rtl8168d_1_phy_reg_init_0); 2581 - 2582 - /* 2583 - * Rx Error Issue 2584 - * Fine Tune Switching regulator parameter 2585 - */ 2586 - phy_write(phydev, 0x1f, 0x0002); 2587 - phy_modify(phydev, 0x0b, 0x00ef, 0x0010); 2588 - phy_modify(phydev, 0x0c, 0x5d00, 0xa200); 2589 - 2590 - if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { 2591 - int val; 2592 - 2593 - rtl_writephy_batch(phydev, rtl8168d_1_phy_reg_init_1); 2594 - 2595 - val = phy_read(phydev, 0x0d); 2596 - 2597 - if ((val & 0x00ff) != 0x006c) { 2598 - static const u32 set[] = { 2599 - 0x0065, 0x0066, 0x0067, 0x0068, 2600 - 0x0069, 0x006a, 0x006b, 0x006c 2601 - }; 2602 - int i; 2603 - 2604 - phy_write(phydev, 0x1f, 0x0002); 2605 - 2606 - val &= 0xff00; 2607 - for (i = 0; i < ARRAY_SIZE(set); i++) 2608 - phy_write(phydev, 0x0d, val | set[i]); 2609 - } 2610 - } else { 2611 - phy_write_paged(phydev, 0x0002, 0x05, 0x6662); 2612 - r8168d_phy_param(phydev, 0x8330, 0xffff, 0x6662); 2613 - } 2614 - 2615 - /* RSET couple improve */ 2616 - phy_write(phydev, 0x1f, 0x0002); 2617 - phy_set_bits(phydev, 0x0d, 0x0300); 2618 - phy_set_bits(phydev, 0x0f, 0x0010); 2619 - 2620 - /* Fine tune PLL performance */ 2621 - phy_write(phydev, 0x1f, 0x0002); 2622 - phy_modify(phydev, 0x02, 0x0600, 0x0100); 2623 - phy_clear_bits(phydev, 0x03, 0xe000); 2624 - phy_write(phydev, 0x1f, 0x0000); 2625 - 2626 - rtl8168d_apply_firmware_cond(tp, phydev, 0xbf00); 2627 - } 2628 - 2629 - static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp, 2630 - struct phy_device *phydev) 2631 - { 2632 - rtl_writephy_batch(phydev, rtl8168d_1_phy_reg_init_0); 2633 - 2634 - if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { 2635 - int val; 2636 - 2637 - rtl_writephy_batch(phydev, rtl8168d_1_phy_reg_init_1); 2638 - 2639 - val = phy_read(phydev, 0x0d); 2640 - if ((val & 0x00ff) != 0x006c) { 2641 - static const u32 set[] = { 2642 - 0x0065, 0x0066, 0x0067, 0x0068, 2643 - 0x0069, 0x006a, 0x006b, 0x006c 2644 - }; 2645 - int i; 2646 - 2647 - phy_write(phydev, 0x1f, 0x0002); 2648 - 2649 - val &= 0xff00; 2650 - for (i = 0; i < ARRAY_SIZE(set); i++) 2651 - phy_write(phydev, 0x0d, val | set[i]); 2652 - } 2653 - } else { 2654 - phy_write_paged(phydev, 0x0002, 0x05, 0x2642); 2655 - r8168d_phy_param(phydev, 0x8330, 0xffff, 0x2642); 2656 - } 2657 - 2658 - /* Fine tune PLL performance */ 2659 - phy_write(phydev, 0x1f, 0x0002); 2660 - phy_modify(phydev, 0x02, 0x0600, 0x0100); 2661 - phy_clear_bits(phydev, 0x03, 0xe000); 2662 - phy_write(phydev, 0x1f, 0x0000); 2663 - 2664 - /* Switching regulator Slew rate */ 2665 - phy_modify_paged(phydev, 0x0002, 0x0f, 0x0000, 0x0017); 2666 - 2667 - rtl8168d_apply_firmware_cond(tp, phydev, 0xb300); 2668 - } 2669 - 2670 - static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp, 2671 - struct phy_device *phydev) 2672 - { 2673 - static const struct phy_reg phy_reg_init[] = { 2674 - { 0x1f, 0x0002 }, 2675 - { 0x10, 0x0008 }, 2676 - { 0x0d, 0x006c }, 2677 - 2678 - { 0x1f, 0x0000 }, 2679 - { 0x0d, 0xf880 }, 2680 - 2681 - { 0x1f, 0x0001 }, 2682 - { 0x17, 0x0cc0 }, 2683 - 2684 - { 0x1f, 0x0001 }, 2685 - { 0x0b, 0xa4d8 }, 2686 - { 0x09, 0x281c }, 2687 - { 0x07, 0x2883 }, 2688 - { 0x0a, 0x6b35 }, 2689 - { 0x1d, 0x3da4 }, 2690 - { 0x1c, 0xeffd }, 2691 - { 0x14, 0x7f52 }, 2692 - { 0x18, 0x7fc6 }, 2693 - { 0x08, 0x0601 }, 2694 - { 0x06, 0x4063 }, 2695 - { 0x10, 0xf074 }, 2696 - { 0x1f, 0x0003 }, 2697 - { 0x13, 0x0789 }, 2698 - { 0x12, 0xf4bd }, 2699 - { 0x1a, 0x04fd }, 2700 - { 0x14, 0x84b0 }, 2701 - { 0x1f, 0x0000 }, 2702 - { 0x00, 0x9200 }, 2703 - 2704 - { 0x1f, 0x0005 }, 2705 - { 0x01, 0x0340 }, 2706 - { 0x1f, 0x0001 }, 2707 - { 0x04, 0x4000 }, 2708 - { 0x03, 0x1d21 }, 2709 - { 0x02, 0x0c32 }, 2710 - { 0x01, 0x0200 }, 2711 - { 0x00, 0x5554 }, 2712 - { 0x04, 0x4800 }, 2713 - { 0x04, 0x4000 }, 2714 - { 0x04, 0xf000 }, 2715 - { 0x03, 0xdf01 }, 2716 - { 0x02, 0xdf20 }, 2717 - { 0x01, 0x101a }, 2718 - { 0x00, 0xa0ff }, 2719 - { 0x04, 0xf800 }, 2720 - { 0x04, 0xf000 }, 2721 - { 0x1f, 0x0000 }, 2722 - }; 2723 - 2724 - rtl_writephy_batch(phydev, phy_reg_init); 2725 - r8168d_modify_extpage(phydev, 0x0023, 0x16, 0xffff, 0x0000); 2726 - } 2727 - 2728 - static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp, 2729 - struct phy_device *phydev) 2730 - { 2731 - phy_write_paged(phydev, 0x0001, 0x17, 0x0cc0); 2732 - r8168d_modify_extpage(phydev, 0x002d, 0x18, 0xffff, 0x0040); 2733 - phy_set_bits(phydev, 0x0d, BIT(5)); 2734 - } 2735 - 2736 - static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp, 2737 - struct phy_device *phydev) 2738 - { 2739 - static const struct phy_reg phy_reg_init[] = { 2740 - /* Channel estimation fine tune */ 2741 - { 0x1f, 0x0001 }, 2742 - { 0x0b, 0x6c20 }, 2743 - { 0x07, 0x2872 }, 2744 - { 0x1c, 0xefff }, 2745 - { 0x1f, 0x0003 }, 2746 - { 0x14, 0x6420 }, 2747 - { 0x1f, 0x0000 }, 2748 - }; 2749 - 2750 - r8169_apply_firmware(tp); 2751 - 2752 - /* Enable Delay cap */ 2753 - r8168d_phy_param(phydev, 0x8b80, 0xffff, 0xc896); 2754 - 2755 - rtl_writephy_batch(phydev, phy_reg_init); 2756 - 2757 - /* Update PFM & 10M TX idle timer */ 2758 - r8168d_modify_extpage(phydev, 0x002f, 0x15, 0xffff, 0x1919); 2759 - 2760 - r8168d_modify_extpage(phydev, 0x00ac, 0x18, 0xffff, 0x0006); 2761 - 2762 - /* DCO enable for 10M IDLE Power */ 2763 - r8168d_modify_extpage(phydev, 0x0023, 0x17, 0x0000, 0x0006); 2764 - 2765 - /* For impedance matching */ 2766 - phy_modify_paged(phydev, 0x0002, 0x08, 0x7f00, 0x8000); 2767 - 2768 - /* PHY auto speed down */ 2769 - r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0050); 2770 - phy_set_bits(phydev, 0x14, BIT(15)); 2771 - 2772 - r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001); 2773 - r8168d_phy_param(phydev, 0x8b85, 0x2000, 0x0000); 2774 - 2775 - r8168d_modify_extpage(phydev, 0x0020, 0x15, 0x1100, 0x0000); 2776 - phy_write_paged(phydev, 0x0006, 0x00, 0x5a00); 2777 - 2778 - phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0000); 2779 - } 2780 - 2781 2255 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr) 2782 2256 { 2783 2257 const u16 w[] = { ··· 2209 2845 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]); 2210 2846 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16); 2211 2847 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16)); 2212 - } 2213 - 2214 - static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp, 2215 - struct phy_device *phydev) 2216 - { 2217 - r8169_apply_firmware(tp); 2218 - 2219 - /* Enable Delay cap */ 2220 - r8168d_modify_extpage(phydev, 0x00ac, 0x18, 0xffff, 0x0006); 2221 - 2222 - /* Channel estimation fine tune */ 2223 - phy_write_paged(phydev, 0x0003, 0x09, 0xa20f); 2224 - 2225 - /* Green Setting */ 2226 - r8168d_phy_param(phydev, 0x8b5b, 0xffff, 0x9222); 2227 - r8168d_phy_param(phydev, 0x8b6d, 0xffff, 0x8000); 2228 - r8168d_phy_param(phydev, 0x8b76, 0xffff, 0x8000); 2229 - 2230 - /* For 4-corner performance improve */ 2231 - phy_write(phydev, 0x1f, 0x0005); 2232 - phy_write(phydev, 0x05, 0x8b80); 2233 - phy_set_bits(phydev, 0x17, 0x0006); 2234 - phy_write(phydev, 0x1f, 0x0000); 2235 - 2236 - /* PHY auto speed down */ 2237 - r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0010); 2238 - phy_set_bits(phydev, 0x14, BIT(15)); 2239 - 2240 - /* improve 10M EEE waveform */ 2241 - r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001); 2242 - 2243 - /* Improve 2-pair detection performance */ 2244 - r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000); 2245 - 2246 - rtl8168f_config_eee_phy(phydev); 2247 - 2248 - /* Green feature */ 2249 - phy_write(phydev, 0x1f, 0x0003); 2250 - phy_set_bits(phydev, 0x19, BIT(0)); 2251 - phy_set_bits(phydev, 0x10, BIT(10)); 2252 - phy_write(phydev, 0x1f, 0x0000); 2253 - phy_modify_paged(phydev, 0x0005, 0x01, 0, BIT(8)); 2254 - } 2255 - 2256 - static void rtl8168f_hw_phy_config(struct rtl8169_private *tp, 2257 - struct phy_device *phydev) 2258 - { 2259 - /* For 4-corner performance improve */ 2260 - r8168d_phy_param(phydev, 0x8b80, 0x0000, 0x0006); 2261 - 2262 - /* PHY auto speed down */ 2263 - r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0010); 2264 - phy_set_bits(phydev, 0x14, BIT(15)); 2265 - 2266 - /* Improve 10M EEE waveform */ 2267 - r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001); 2268 - 2269 - rtl8168f_config_eee_phy(phydev); 2270 - } 2271 - 2272 - static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp, 2273 - struct phy_device *phydev) 2274 - { 2275 - r8169_apply_firmware(tp); 2276 - 2277 - /* Channel estimation fine tune */ 2278 - phy_write_paged(phydev, 0x0003, 0x09, 0xa20f); 2279 - 2280 - /* Modify green table for giga & fnet */ 2281 - r8168d_phy_param(phydev, 0x8b55, 0xffff, 0x0000); 2282 - r8168d_phy_param(phydev, 0x8b5e, 0xffff, 0x0000); 2283 - r8168d_phy_param(phydev, 0x8b67, 0xffff, 0x0000); 2284 - r8168d_phy_param(phydev, 0x8b70, 0xffff, 0x0000); 2285 - r8168d_modify_extpage(phydev, 0x0078, 0x17, 0xffff, 0x0000); 2286 - r8168d_modify_extpage(phydev, 0x0078, 0x19, 0xffff, 0x00fb); 2287 - 2288 - /* Modify green table for 10M */ 2289 - r8168d_phy_param(phydev, 0x8b79, 0xffff, 0xaa00); 2290 - 2291 - /* Disable hiimpedance detection (RTCT) */ 2292 - phy_write_paged(phydev, 0x0003, 0x01, 0x328a); 2293 - 2294 - rtl8168f_hw_phy_config(tp, phydev); 2295 - 2296 - /* Improve 2-pair detection performance */ 2297 - r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000); 2298 - } 2299 - 2300 - static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp, 2301 - struct phy_device *phydev) 2302 - { 2303 - r8169_apply_firmware(tp); 2304 - 2305 - rtl8168f_hw_phy_config(tp, phydev); 2306 - } 2307 - 2308 - static void rtl8411_hw_phy_config(struct rtl8169_private *tp, 2309 - struct phy_device *phydev) 2310 - { 2311 - r8169_apply_firmware(tp); 2312 - 2313 - rtl8168f_hw_phy_config(tp, phydev); 2314 - 2315 - /* Improve 2-pair detection performance */ 2316 - r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000); 2317 - 2318 - /* Channel estimation fine tune */ 2319 - phy_write_paged(phydev, 0x0003, 0x09, 0xa20f); 2320 - 2321 - /* Modify green table for giga & fnet */ 2322 - r8168d_phy_param(phydev, 0x8b55, 0xffff, 0x0000); 2323 - r8168d_phy_param(phydev, 0x8b5e, 0xffff, 0x0000); 2324 - r8168d_phy_param(phydev, 0x8b67, 0xffff, 0x0000); 2325 - r8168d_phy_param(phydev, 0x8b70, 0xffff, 0x0000); 2326 - r8168d_modify_extpage(phydev, 0x0078, 0x17, 0xffff, 0x0000); 2327 - r8168d_modify_extpage(phydev, 0x0078, 0x19, 0xffff, 0x00aa); 2328 - 2329 - /* Modify green table for 10M */ 2330 - r8168d_phy_param(phydev, 0x8b79, 0xffff, 0xaa00); 2331 - 2332 - /* Disable hiimpedance detection (RTCT) */ 2333 - phy_write_paged(phydev, 0x0003, 0x01, 0x328a); 2334 - 2335 - /* Modify green table for giga */ 2336 - r8168d_phy_param(phydev, 0x8b54, 0x0800, 0x0000); 2337 - r8168d_phy_param(phydev, 0x8b5d, 0x0800, 0x0000); 2338 - r8168d_phy_param(phydev, 0x8a7c, 0x0100, 0x0000); 2339 - r8168d_phy_param(phydev, 0x8a7f, 0x0000, 0x0100); 2340 - r8168d_phy_param(phydev, 0x8a82, 0x0100, 0x0000); 2341 - r8168d_phy_param(phydev, 0x8a85, 0x0100, 0x0000); 2342 - r8168d_phy_param(phydev, 0x8a88, 0x0100, 0x0000); 2343 - 2344 - /* uc same-seed solution */ 2345 - r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x8000); 2346 - 2347 - /* Green feature */ 2348 - phy_write(phydev, 0x1f, 0x0003); 2349 - phy_clear_bits(phydev, 0x19, BIT(0)); 2350 - phy_clear_bits(phydev, 0x10, BIT(10)); 2351 - phy_write(phydev, 0x1f, 0x0000); 2352 - } 2353 - 2354 - static void rtl8168g_disable_aldps(struct phy_device *phydev) 2355 - { 2356 - phy_modify_paged(phydev, 0x0a43, 0x10, BIT(2), 0); 2357 - } 2358 - 2359 - static void rtl8168g_phy_adjust_10m_aldps(struct phy_device *phydev) 2360 - { 2361 - phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0); 2362 - phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6)); 2363 - r8168g_phy_param(phydev, 0x8084, 0x6000, 0x0000); 2364 - phy_modify_paged(phydev, 0x0a43, 0x10, 0x0000, 0x1003); 2365 - } 2366 - 2367 - static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp, 2368 - struct phy_device *phydev) 2369 - { 2370 - int ret; 2371 - 2372 - r8169_apply_firmware(tp); 2373 - 2374 - ret = phy_read_paged(phydev, 0x0a46, 0x10); 2375 - if (ret & BIT(8)) 2376 - phy_modify_paged(phydev, 0x0bcc, 0x12, BIT(15), 0); 2377 - else 2378 - phy_modify_paged(phydev, 0x0bcc, 0x12, 0, BIT(15)); 2379 - 2380 - ret = phy_read_paged(phydev, 0x0a46, 0x13); 2381 - if (ret & BIT(8)) 2382 - phy_modify_paged(phydev, 0x0c41, 0x15, 0, BIT(1)); 2383 - else 2384 - phy_modify_paged(phydev, 0x0c41, 0x15, BIT(1), 0); 2385 - 2386 - /* Enable PHY auto speed down */ 2387 - phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2)); 2388 - 2389 - rtl8168g_phy_adjust_10m_aldps(phydev); 2390 - 2391 - /* EEE auto-fallback function */ 2392 - phy_modify_paged(phydev, 0x0a4b, 0x11, 0, BIT(2)); 2393 - 2394 - /* Enable UC LPF tune function */ 2395 - r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000); 2396 - 2397 - phy_modify_paged(phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 2398 - 2399 - /* Improve SWR Efficiency */ 2400 - phy_write(phydev, 0x1f, 0x0bcd); 2401 - phy_write(phydev, 0x14, 0x5065); 2402 - phy_write(phydev, 0x14, 0xd065); 2403 - phy_write(phydev, 0x1f, 0x0bc8); 2404 - phy_write(phydev, 0x11, 0x5655); 2405 - phy_write(phydev, 0x1f, 0x0bcd); 2406 - phy_write(phydev, 0x14, 0x1065); 2407 - phy_write(phydev, 0x14, 0x9065); 2408 - phy_write(phydev, 0x14, 0x1065); 2409 - phy_write(phydev, 0x1f, 0x0000); 2410 - 2411 - rtl8168g_disable_aldps(phydev); 2412 - rtl8168g_config_eee_phy(phydev); 2413 - } 2414 - 2415 - static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp, 2416 - struct phy_device *phydev) 2417 - { 2418 - r8169_apply_firmware(tp); 2419 - rtl8168g_config_eee_phy(phydev); 2420 - } 2421 - 2422 - static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp, 2423 - struct phy_device *phydev) 2424 - { 2425 - u16 dout_tapbin; 2426 - u32 data; 2427 - 2428 - r8169_apply_firmware(tp); 2429 - 2430 - /* CHN EST parameters adjust - giga master */ 2431 - r8168g_phy_param(phydev, 0x809b, 0xf800, 0x8000); 2432 - r8168g_phy_param(phydev, 0x80a2, 0xff00, 0x8000); 2433 - r8168g_phy_param(phydev, 0x80a4, 0xff00, 0x8500); 2434 - r8168g_phy_param(phydev, 0x809c, 0xff00, 0xbd00); 2435 - 2436 - /* CHN EST parameters adjust - giga slave */ 2437 - r8168g_phy_param(phydev, 0x80ad, 0xf800, 0x7000); 2438 - r8168g_phy_param(phydev, 0x80b4, 0xff00, 0x5000); 2439 - r8168g_phy_param(phydev, 0x80ac, 0xff00, 0x4000); 2440 - 2441 - /* CHN EST parameters adjust - fnet */ 2442 - r8168g_phy_param(phydev, 0x808e, 0xff00, 0x1200); 2443 - r8168g_phy_param(phydev, 0x8090, 0xff00, 0xe500); 2444 - r8168g_phy_param(phydev, 0x8092, 0xff00, 0x9f00); 2445 - 2446 - /* enable R-tune & PGA-retune function */ 2447 - dout_tapbin = 0; 2448 - data = phy_read_paged(phydev, 0x0a46, 0x13); 2449 - data &= 3; 2450 - data <<= 2; 2451 - dout_tapbin |= data; 2452 - data = phy_read_paged(phydev, 0x0a46, 0x12); 2453 - data &= 0xc000; 2454 - data >>= 14; 2455 - dout_tapbin |= data; 2456 - dout_tapbin = ~(dout_tapbin^0x08); 2457 - dout_tapbin <<= 12; 2458 - dout_tapbin &= 0xf000; 2459 - 2460 - r8168g_phy_param(phydev, 0x827a, 0xf000, dout_tapbin); 2461 - r8168g_phy_param(phydev, 0x827b, 0xf000, dout_tapbin); 2462 - r8168g_phy_param(phydev, 0x827c, 0xf000, dout_tapbin); 2463 - r8168g_phy_param(phydev, 0x827d, 0xf000, dout_tapbin); 2464 - r8168g_phy_param(phydev, 0x0811, 0x0000, 0x0800); 2465 - phy_modify_paged(phydev, 0x0a42, 0x16, 0x0000, 0x0002); 2466 - 2467 - /* enable GPHY 10M */ 2468 - phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(11)); 2469 - 2470 - /* SAR ADC performance */ 2471 - phy_modify_paged(phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14)); 2472 - 2473 - r8168g_phy_param(phydev, 0x803f, 0x3000, 0x0000); 2474 - r8168g_phy_param(phydev, 0x8047, 0x3000, 0x0000); 2475 - r8168g_phy_param(phydev, 0x804f, 0x3000, 0x0000); 2476 - r8168g_phy_param(phydev, 0x8057, 0x3000, 0x0000); 2477 - r8168g_phy_param(phydev, 0x805f, 0x3000, 0x0000); 2478 - r8168g_phy_param(phydev, 0x8067, 0x3000, 0x0000); 2479 - r8168g_phy_param(phydev, 0x806f, 0x3000, 0x0000); 2480 - 2481 - /* disable phy pfm mode */ 2482 - phy_modify_paged(phydev, 0x0a44, 0x11, BIT(7), 0); 2483 - 2484 - rtl8168g_disable_aldps(phydev); 2485 - rtl8168h_config_eee_phy(phydev); 2486 2848 } 2487 2849 2488 2850 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) ··· 2225 3135 ioffset |= BIT(15); 2226 3136 2227 3137 return ioffset; 2228 - } 2229 - 2230 - static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp, 2231 - struct phy_device *phydev) 2232 - { 2233 - u16 ioffset, rlen; 2234 - u32 data; 2235 - 2236 - r8169_apply_firmware(tp); 2237 - 2238 - /* CHIN EST parameter update */ 2239 - r8168g_phy_param(phydev, 0x808a, 0x003f, 0x000a); 2240 - 2241 - /* enable R-tune & PGA-retune function */ 2242 - r8168g_phy_param(phydev, 0x0811, 0x0000, 0x0800); 2243 - phy_modify_paged(phydev, 0x0a42, 0x16, 0x0000, 0x0002); 2244 - 2245 - /* enable GPHY 10M */ 2246 - phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(11)); 2247 - 2248 - ioffset = rtl8168h_2_get_adc_bias_ioffset(tp); 2249 - if (ioffset != 0xffff) 2250 - phy_write_paged(phydev, 0x0bcf, 0x16, ioffset); 2251 - 2252 - /* Modify rlen (TX LPF corner frequency) level */ 2253 - data = phy_read_paged(phydev, 0x0bcd, 0x16); 2254 - data &= 0x000f; 2255 - rlen = 0; 2256 - if (data > 3) 2257 - rlen = data - 3; 2258 - data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12); 2259 - phy_write_paged(phydev, 0x0bcd, 0x17, data); 2260 - 2261 - /* disable phy pfm mode */ 2262 - phy_modify_paged(phydev, 0x0a44, 0x11, BIT(7), 0); 2263 - 2264 - rtl8168g_disable_aldps(phydev); 2265 - rtl8168g_config_eee_phy(phydev); 2266 - } 2267 - 2268 - static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp, 2269 - struct phy_device *phydev) 2270 - { 2271 - /* Enable PHY auto speed down */ 2272 - phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2)); 2273 - 2274 - rtl8168g_phy_adjust_10m_aldps(phydev); 2275 - 2276 - /* Enable EEE auto-fallback function */ 2277 - phy_modify_paged(phydev, 0x0a4b, 0x11, 0, BIT(2)); 2278 - 2279 - /* Enable UC LPF tune function */ 2280 - r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000); 2281 - 2282 - /* set rg_sel_sdm_rate */ 2283 - phy_modify_paged(phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 2284 - 2285 - rtl8168g_disable_aldps(phydev); 2286 - rtl8168g_config_eee_phy(phydev); 2287 - } 2288 - 2289 - static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp, 2290 - struct phy_device *phydev) 2291 - { 2292 - rtl8168g_phy_adjust_10m_aldps(phydev); 2293 - 2294 - /* Enable UC LPF tune function */ 2295 - r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000); 2296 - 2297 - /* Set rg_sel_sdm_rate */ 2298 - phy_modify_paged(phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 2299 - 2300 - /* Channel estimation parameters */ 2301 - r8168g_phy_param(phydev, 0x80f3, 0xff00, 0x8b00); 2302 - r8168g_phy_param(phydev, 0x80f0, 0xff00, 0x3a00); 2303 - r8168g_phy_param(phydev, 0x80ef, 0xff00, 0x0500); 2304 - r8168g_phy_param(phydev, 0x80f6, 0xff00, 0x6e00); 2305 - r8168g_phy_param(phydev, 0x80ec, 0xff00, 0x6800); 2306 - r8168g_phy_param(phydev, 0x80ed, 0xff00, 0x7c00); 2307 - r8168g_phy_param(phydev, 0x80f2, 0xff00, 0xf400); 2308 - r8168g_phy_param(phydev, 0x80f4, 0xff00, 0x8500); 2309 - r8168g_phy_param(phydev, 0x8110, 0xff00, 0xa800); 2310 - r8168g_phy_param(phydev, 0x810f, 0xff00, 0x1d00); 2311 - r8168g_phy_param(phydev, 0x8111, 0xff00, 0xf500); 2312 - r8168g_phy_param(phydev, 0x8113, 0xff00, 0x6100); 2313 - r8168g_phy_param(phydev, 0x8115, 0xff00, 0x9200); 2314 - r8168g_phy_param(phydev, 0x810e, 0xff00, 0x0400); 2315 - r8168g_phy_param(phydev, 0x810c, 0xff00, 0x7c00); 2316 - r8168g_phy_param(phydev, 0x810b, 0xff00, 0x5a00); 2317 - r8168g_phy_param(phydev, 0x80d1, 0xff00, 0xff00); 2318 - r8168g_phy_param(phydev, 0x80cd, 0xff00, 0x9e00); 2319 - r8168g_phy_param(phydev, 0x80d3, 0xff00, 0x0e00); 2320 - r8168g_phy_param(phydev, 0x80d5, 0xff00, 0xca00); 2321 - r8168g_phy_param(phydev, 0x80d7, 0xff00, 0x8400); 2322 - 2323 - /* Force PWM-mode */ 2324 - phy_write(phydev, 0x1f, 0x0bcd); 2325 - phy_write(phydev, 0x14, 0x5065); 2326 - phy_write(phydev, 0x14, 0xd065); 2327 - phy_write(phydev, 0x1f, 0x0bc8); 2328 - phy_write(phydev, 0x12, 0x00ed); 2329 - phy_write(phydev, 0x1f, 0x0bcd); 2330 - phy_write(phydev, 0x14, 0x1065); 2331 - phy_write(phydev, 0x14, 0x9065); 2332 - phy_write(phydev, 0x14, 0x1065); 2333 - phy_write(phydev, 0x1f, 0x0000); 2334 - 2335 - rtl8168g_disable_aldps(phydev); 2336 - rtl8168g_config_eee_phy(phydev); 2337 - } 2338 - 2339 - static void rtl8117_hw_phy_config(struct rtl8169_private *tp, 2340 - struct phy_device *phydev) 2341 - { 2342 - /* CHN EST parameters adjust - fnet */ 2343 - r8168g_phy_param(phydev, 0x808e, 0xff00, 0x4800); 2344 - r8168g_phy_param(phydev, 0x8090, 0xff00, 0xcc00); 2345 - r8168g_phy_param(phydev, 0x8092, 0xff00, 0xb000); 2346 - 2347 - r8168g_phy_param(phydev, 0x8088, 0xff00, 0x6000); 2348 - r8168g_phy_param(phydev, 0x808b, 0x3f00, 0x0b00); 2349 - r8168g_phy_param(phydev, 0x808d, 0x1f00, 0x0600); 2350 - r8168g_phy_param(phydev, 0x808c, 0xff00, 0xb000); 2351 - r8168g_phy_param(phydev, 0x80a0, 0xff00, 0x2800); 2352 - r8168g_phy_param(phydev, 0x80a2, 0xff00, 0x5000); 2353 - r8168g_phy_param(phydev, 0x809b, 0xf800, 0xb000); 2354 - r8168g_phy_param(phydev, 0x809a, 0xff00, 0x4b00); 2355 - r8168g_phy_param(phydev, 0x809d, 0x3f00, 0x0800); 2356 - r8168g_phy_param(phydev, 0x80a1, 0xff00, 0x7000); 2357 - r8168g_phy_param(phydev, 0x809f, 0x1f00, 0x0300); 2358 - r8168g_phy_param(phydev, 0x809e, 0xff00, 0x8800); 2359 - r8168g_phy_param(phydev, 0x80b2, 0xff00, 0x2200); 2360 - r8168g_phy_param(phydev, 0x80ad, 0xf800, 0x9800); 2361 - r8168g_phy_param(phydev, 0x80af, 0x3f00, 0x0800); 2362 - r8168g_phy_param(phydev, 0x80b3, 0xff00, 0x6f00); 2363 - r8168g_phy_param(phydev, 0x80b1, 0x1f00, 0x0300); 2364 - r8168g_phy_param(phydev, 0x80b0, 0xff00, 0x9300); 2365 - 2366 - r8168g_phy_param(phydev, 0x8011, 0x0000, 0x0800); 2367 - 2368 - /* enable GPHY 10M */ 2369 - phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(11)); 2370 - 2371 - r8168g_phy_param(phydev, 0x8016, 0x0000, 0x0400); 2372 - 2373 - rtl8168g_disable_aldps(phydev); 2374 - rtl8168h_config_eee_phy(phydev); 2375 - } 2376 - 2377 - static void rtl8102e_hw_phy_config(struct rtl8169_private *tp, 2378 - struct phy_device *phydev) 2379 - { 2380 - static const struct phy_reg phy_reg_init[] = { 2381 - { 0x1f, 0x0003 }, 2382 - { 0x08, 0x441d }, 2383 - { 0x01, 0x9100 }, 2384 - { 0x1f, 0x0000 } 2385 - }; 2386 - 2387 - phy_set_bits(phydev, 0x11, BIT(12)); 2388 - phy_set_bits(phydev, 0x19, BIT(13)); 2389 - phy_set_bits(phydev, 0x10, BIT(15)); 2390 - 2391 - rtl_writephy_batch(phydev, phy_reg_init); 2392 - } 2393 - 2394 - static void rtl8105e_hw_phy_config(struct rtl8169_private *tp, 2395 - struct phy_device *phydev) 2396 - { 2397 - /* Disable ALDPS before ram code */ 2398 - phy_write(phydev, 0x18, 0x0310); 2399 - msleep(100); 2400 - 2401 - r8169_apply_firmware(tp); 2402 - 2403 - phy_write_paged(phydev, 0x0005, 0x1a, 0x0000); 2404 - phy_write_paged(phydev, 0x0004, 0x1c, 0x0000); 2405 - phy_write_paged(phydev, 0x0001, 0x15, 0x7701); 2406 - } 2407 - 2408 - static void rtl8402_hw_phy_config(struct rtl8169_private *tp, 2409 - struct phy_device *phydev) 2410 - { 2411 - /* Disable ALDPS before setting firmware */ 2412 - phy_write(phydev, 0x18, 0x0310); 2413 - msleep(20); 2414 - 2415 - r8169_apply_firmware(tp); 2416 - 2417 - /* EEE setting */ 2418 - phy_write(phydev, 0x1f, 0x0004); 2419 - phy_write(phydev, 0x10, 0x401f); 2420 - phy_write(phydev, 0x19, 0x7030); 2421 - phy_write(phydev, 0x1f, 0x0000); 2422 - } 2423 - 2424 - static void rtl8106e_hw_phy_config(struct rtl8169_private *tp, 2425 - struct phy_device *phydev) 2426 - { 2427 - static const struct phy_reg phy_reg_init[] = { 2428 - { 0x1f, 0x0004 }, 2429 - { 0x10, 0xc07f }, 2430 - { 0x19, 0x7030 }, 2431 - { 0x1f, 0x0000 } 2432 - }; 2433 - 2434 - /* Disable ALDPS before ram code */ 2435 - phy_write(phydev, 0x18, 0x0310); 2436 - msleep(100); 2437 - 2438 - r8169_apply_firmware(tp); 2439 - 2440 - rtl_writephy_batch(phydev, phy_reg_init); 2441 - } 2442 - 2443 - static void rtl8125_1_hw_phy_config(struct rtl8169_private *tp, 2444 - struct phy_device *phydev) 2445 - { 2446 - phy_modify_paged(phydev, 0xad4, 0x10, 0x03ff, 0x0084); 2447 - phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010); 2448 - phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x0006); 2449 - phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006); 2450 - phy_modify_paged(phydev, 0xac0, 0x14, 0x0000, 0x1100); 2451 - phy_modify_paged(phydev, 0xac8, 0x15, 0xf000, 0x7000); 2452 - phy_modify_paged(phydev, 0xad1, 0x14, 0x0000, 0x0400); 2453 - phy_modify_paged(phydev, 0xad1, 0x15, 0x0000, 0x03ff); 2454 - phy_modify_paged(phydev, 0xad1, 0x16, 0x0000, 0x03ff); 2455 - 2456 - r8168g_phy_param(phydev, 0x80ea, 0xff00, 0xc400); 2457 - r8168g_phy_param(phydev, 0x80eb, 0x0700, 0x0300); 2458 - r8168g_phy_param(phydev, 0x80f8, 0xff00, 0x1c00); 2459 - r8168g_phy_param(phydev, 0x80f1, 0xff00, 0x3000); 2460 - r8168g_phy_param(phydev, 0x80fe, 0xff00, 0xa500); 2461 - r8168g_phy_param(phydev, 0x8102, 0xff00, 0x5000); 2462 - r8168g_phy_param(phydev, 0x8105, 0xff00, 0x3300); 2463 - r8168g_phy_param(phydev, 0x8100, 0xff00, 0x7000); 2464 - r8168g_phy_param(phydev, 0x8104, 0xff00, 0xf000); 2465 - r8168g_phy_param(phydev, 0x8106, 0xff00, 0x6500); 2466 - r8168g_phy_param(phydev, 0x80dc, 0xff00, 0xed00); 2467 - r8168g_phy_param(phydev, 0x80df, 0x0000, 0x0100); 2468 - r8168g_phy_param(phydev, 0x80e1, 0x0100, 0x0000); 2469 - 2470 - phy_modify_paged(phydev, 0xbf0, 0x13, 0x003f, 0x0038); 2471 - r8168g_phy_param(phydev, 0x819f, 0xffff, 0xd0b6); 2472 - 2473 - phy_write_paged(phydev, 0xbc3, 0x12, 0x5555); 2474 - phy_modify_paged(phydev, 0xbf0, 0x15, 0x0e00, 0x0a00); 2475 - phy_modify_paged(phydev, 0xa5c, 0x10, 0x0400, 0x0000); 2476 - phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800); 2477 - 2478 - rtl8125_config_eee_phy(phydev); 2479 - } 2480 - 2481 - static void rtl8125_2_hw_phy_config(struct rtl8169_private *tp, 2482 - struct phy_device *phydev) 2483 - { 2484 - int i; 2485 - 2486 - phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010); 2487 - phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x03ff); 2488 - phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006); 2489 - phy_modify_paged(phydev, 0xac0, 0x14, 0x1100, 0x0000); 2490 - phy_modify_paged(phydev, 0xacc, 0x10, 0x0003, 0x0002); 2491 - phy_modify_paged(phydev, 0xad4, 0x10, 0x00e7, 0x0044); 2492 - phy_modify_paged(phydev, 0xac1, 0x12, 0x0080, 0x0000); 2493 - phy_modify_paged(phydev, 0xac8, 0x10, 0x0300, 0x0000); 2494 - phy_modify_paged(phydev, 0xac5, 0x17, 0x0007, 0x0002); 2495 - phy_write_paged(phydev, 0xad4, 0x16, 0x00a8); 2496 - phy_write_paged(phydev, 0xac5, 0x16, 0x01ff); 2497 - phy_modify_paged(phydev, 0xac8, 0x15, 0x00f0, 0x0030); 2498 - 2499 - phy_write(phydev, 0x1f, 0x0b87); 2500 - phy_write(phydev, 0x16, 0x80a2); 2501 - phy_write(phydev, 0x17, 0x0153); 2502 - phy_write(phydev, 0x16, 0x809c); 2503 - phy_write(phydev, 0x17, 0x0153); 2504 - phy_write(phydev, 0x1f, 0x0000); 2505 - 2506 - phy_write(phydev, 0x1f, 0x0a43); 2507 - phy_write(phydev, 0x13, 0x81B3); 2508 - phy_write(phydev, 0x14, 0x0043); 2509 - phy_write(phydev, 0x14, 0x00A7); 2510 - phy_write(phydev, 0x14, 0x00D6); 2511 - phy_write(phydev, 0x14, 0x00EC); 2512 - phy_write(phydev, 0x14, 0x00F6); 2513 - phy_write(phydev, 0x14, 0x00FB); 2514 - phy_write(phydev, 0x14, 0x00FD); 2515 - phy_write(phydev, 0x14, 0x00FF); 2516 - phy_write(phydev, 0x14, 0x00BB); 2517 - phy_write(phydev, 0x14, 0x0058); 2518 - phy_write(phydev, 0x14, 0x0029); 2519 - phy_write(phydev, 0x14, 0x0013); 2520 - phy_write(phydev, 0x14, 0x0009); 2521 - phy_write(phydev, 0x14, 0x0004); 2522 - phy_write(phydev, 0x14, 0x0002); 2523 - for (i = 0; i < 25; i++) 2524 - phy_write(phydev, 0x14, 0x0000); 2525 - phy_write(phydev, 0x1f, 0x0000); 2526 - 2527 - r8168g_phy_param(phydev, 0x8257, 0xffff, 0x020F); 2528 - r8168g_phy_param(phydev, 0x80ea, 0xffff, 0x7843); 2529 - 2530 - r8169_apply_firmware(tp); 2531 - 2532 - phy_modify_paged(phydev, 0xd06, 0x14, 0x0000, 0x2000); 2533 - 2534 - r8168g_phy_param(phydev, 0x81a2, 0x0000, 0x0100); 2535 - 2536 - phy_modify_paged(phydev, 0xb54, 0x16, 0xff00, 0xdb00); 2537 - phy_modify_paged(phydev, 0xa45, 0x12, 0x0001, 0x0000); 2538 - phy_modify_paged(phydev, 0xa5d, 0x12, 0x0000, 0x0020); 2539 - phy_modify_paged(phydev, 0xad4, 0x17, 0x0010, 0x0000); 2540 - phy_modify_paged(phydev, 0xa86, 0x15, 0x0001, 0x0000); 2541 - phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800); 2542 - 2543 - rtl8125_config_eee_phy(phydev); 2544 - } 2545 - 2546 - void r8169_hw_phy_config(struct rtl8169_private *tp, struct phy_device *phydev, 2547 - enum mac_version ver) 2548 - { 2549 - static const rtl_phy_cfg_fct phy_configs[] = { 2550 - /* PCI devices. */ 2551 - [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config, 2552 - [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config, 2553 - [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config, 2554 - [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config, 2555 - [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config, 2556 - /* PCI-E devices. */ 2557 - [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config, 2558 - [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config, 2559 - [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config, 2560 - [RTL_GIGA_MAC_VER_10] = NULL, 2561 - [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config, 2562 - [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config, 2563 - [RTL_GIGA_MAC_VER_13] = NULL, 2564 - [RTL_GIGA_MAC_VER_14] = NULL, 2565 - [RTL_GIGA_MAC_VER_15] = NULL, 2566 - [RTL_GIGA_MAC_VER_16] = NULL, 2567 - [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config, 2568 - [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config, 2569 - [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config, 2570 - [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config, 2571 - [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config, 2572 - [RTL_GIGA_MAC_VER_22] = rtl8168c_3_hw_phy_config, 2573 - [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config, 2574 - [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config, 2575 - [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config, 2576 - [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config, 2577 - [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config, 2578 - [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config, 2579 - [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config, 2580 - [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config, 2581 - [RTL_GIGA_MAC_VER_31] = NULL, 2582 - [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config, 2583 - [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config, 2584 - [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config, 2585 - [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config, 2586 - [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config, 2587 - [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config, 2588 - [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config, 2589 - [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config, 2590 - [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config, 2591 - [RTL_GIGA_MAC_VER_41] = NULL, 2592 - [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config, 2593 - [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config, 2594 - [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config, 2595 - [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config, 2596 - [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config, 2597 - [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config, 2598 - [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config, 2599 - [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config, 2600 - [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config, 2601 - [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config, 2602 - [RTL_GIGA_MAC_VER_52] = rtl8117_hw_phy_config, 2603 - [RTL_GIGA_MAC_VER_60] = rtl8125_1_hw_phy_config, 2604 - [RTL_GIGA_MAC_VER_61] = rtl8125_2_hw_phy_config, 2605 - }; 2606 - 2607 - if (phy_configs[ver]) 2608 - phy_configs[ver](tp, phydev); 2609 3138 } 2610 3139 2611 3140 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)

+1307

drivers/net/ethernet/realtek/r8169_phy_config.c

··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + /* 3 + * r8169_phy_config.c: RealTek 8169/8168/8101 ethernet driver. 4 + * 5 + * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 + * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 + * Copyright (c) a lot of people too. Please respect their work. 8 + * 9 + * See MAINTAINERS file for support contact information. 10 + */ 11 + 12 + #include <linux/delay.h> 13 + #include <linux/phy.h> 14 + 15 + #include "r8169.h" 16 + 17 + typedef void (*rtl_phy_cfg_fct)(struct rtl8169_private *tp, 18 + struct phy_device *phydev); 19 + 20 + static void r8168d_modify_extpage(struct phy_device *phydev, int extpage, 21 + int reg, u16 mask, u16 val) 22 + { 23 + int oldpage = phy_select_page(phydev, 0x0007); 24 + 25 + __phy_write(phydev, 0x1e, extpage); 26 + __phy_modify(phydev, reg, mask, val); 27 + 28 + phy_restore_page(phydev, oldpage, 0); 29 + } 30 + 31 + static void r8168d_phy_param(struct phy_device *phydev, u16 parm, 32 + u16 mask, u16 val) 33 + { 34 + int oldpage = phy_select_page(phydev, 0x0005); 35 + 36 + __phy_write(phydev, 0x05, parm); 37 + __phy_modify(phydev, 0x06, mask, val); 38 + 39 + phy_restore_page(phydev, oldpage, 0); 40 + } 41 + 42 + static void r8168g_phy_param(struct phy_device *phydev, u16 parm, 43 + u16 mask, u16 val) 44 + { 45 + int oldpage = phy_select_page(phydev, 0x0a43); 46 + 47 + __phy_write(phydev, 0x13, parm); 48 + __phy_modify(phydev, 0x14, mask, val); 49 + 50 + phy_restore_page(phydev, oldpage, 0); 51 + } 52 + 53 + struct phy_reg { 54 + u16 reg; 55 + u16 val; 56 + }; 57 + 58 + static void __rtl_writephy_batch(struct phy_device *phydev, 59 + const struct phy_reg *regs, int len) 60 + { 61 + phy_lock_mdio_bus(phydev); 62 + 63 + while (len-- > 0) { 64 + __phy_write(phydev, regs->reg, regs->val); 65 + regs++; 66 + } 67 + 68 + phy_unlock_mdio_bus(phydev); 69 + } 70 + 71 + #define rtl_writephy_batch(p, a) __rtl_writephy_batch(p, a, ARRAY_SIZE(a)) 72 + 73 + static void rtl8168f_config_eee_phy(struct phy_device *phydev) 74 + { 75 + r8168d_modify_extpage(phydev, 0x0020, 0x15, 0, BIT(8)); 76 + r8168d_phy_param(phydev, 0x8b85, 0, BIT(13)); 77 + } 78 + 79 + static void rtl8168g_config_eee_phy(struct phy_device *phydev) 80 + { 81 + phy_modify_paged(phydev, 0x0a43, 0x11, 0, BIT(4)); 82 + } 83 + 84 + static void rtl8168h_config_eee_phy(struct phy_device *phydev) 85 + { 86 + rtl8168g_config_eee_phy(phydev); 87 + 88 + phy_modify_paged(phydev, 0xa4a, 0x11, 0x0000, 0x0200); 89 + phy_modify_paged(phydev, 0xa42, 0x14, 0x0000, 0x0080); 90 + } 91 + 92 + static void rtl8125_config_eee_phy(struct phy_device *phydev) 93 + { 94 + rtl8168h_config_eee_phy(phydev); 95 + 96 + phy_modify_paged(phydev, 0xa6d, 0x12, 0x0001, 0x0000); 97 + phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000); 98 + } 99 + 100 + static void rtl8169s_hw_phy_config(struct rtl8169_private *tp, 101 + struct phy_device *phydev) 102 + { 103 + static const struct phy_reg phy_reg_init[] = { 104 + { 0x1f, 0x0001 }, 105 + { 0x06, 0x006e }, 106 + { 0x08, 0x0708 }, 107 + { 0x15, 0x4000 }, 108 + { 0x18, 0x65c7 }, 109 + 110 + { 0x1f, 0x0001 }, 111 + { 0x03, 0x00a1 }, 112 + { 0x02, 0x0008 }, 113 + { 0x01, 0x0120 }, 114 + { 0x00, 0x1000 }, 115 + { 0x04, 0x0800 }, 116 + { 0x04, 0x0000 }, 117 + 118 + { 0x03, 0xff41 }, 119 + { 0x02, 0xdf60 }, 120 + { 0x01, 0x0140 }, 121 + { 0x00, 0x0077 }, 122 + { 0x04, 0x7800 }, 123 + { 0x04, 0x7000 }, 124 + 125 + { 0x03, 0x802f }, 126 + { 0x02, 0x4f02 }, 127 + { 0x01, 0x0409 }, 128 + { 0x00, 0xf0f9 }, 129 + { 0x04, 0x9800 }, 130 + { 0x04, 0x9000 }, 131 + 132 + { 0x03, 0xdf01 }, 133 + { 0x02, 0xdf20 }, 134 + { 0x01, 0xff95 }, 135 + { 0x00, 0xba00 }, 136 + { 0x04, 0xa800 }, 137 + { 0x04, 0xa000 }, 138 + 139 + { 0x03, 0xff41 }, 140 + { 0x02, 0xdf20 }, 141 + { 0x01, 0x0140 }, 142 + { 0x00, 0x00bb }, 143 + { 0x04, 0xb800 }, 144 + { 0x04, 0xb000 }, 145 + 146 + { 0x03, 0xdf41 }, 147 + { 0x02, 0xdc60 }, 148 + { 0x01, 0x6340 }, 149 + { 0x00, 0x007d }, 150 + { 0x04, 0xd800 }, 151 + { 0x04, 0xd000 }, 152 + 153 + { 0x03, 0xdf01 }, 154 + { 0x02, 0xdf20 }, 155 + { 0x01, 0x100a }, 156 + { 0x00, 0xa0ff }, 157 + { 0x04, 0xf800 }, 158 + { 0x04, 0xf000 }, 159 + 160 + { 0x1f, 0x0000 }, 161 + { 0x0b, 0x0000 }, 162 + { 0x00, 0x9200 } 163 + }; 164 + 165 + rtl_writephy_batch(phydev, phy_reg_init); 166 + } 167 + 168 + static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp, 169 + struct phy_device *phydev) 170 + { 171 + phy_write_paged(phydev, 0x0002, 0x01, 0x90d0); 172 + } 173 + 174 + static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp, 175 + struct phy_device *phydev) 176 + { 177 + static const struct phy_reg phy_reg_init[] = { 178 + { 0x1f, 0x0001 }, 179 + { 0x04, 0x0000 }, 180 + { 0x03, 0x00a1 }, 181 + { 0x02, 0x0008 }, 182 + { 0x01, 0x0120 }, 183 + { 0x00, 0x1000 }, 184 + { 0x04, 0x0800 }, 185 + { 0x04, 0x9000 }, 186 + { 0x03, 0x802f }, 187 + { 0x02, 0x4f02 }, 188 + { 0x01, 0x0409 }, 189 + { 0x00, 0xf099 }, 190 + { 0x04, 0x9800 }, 191 + { 0x04, 0xa000 }, 192 + { 0x03, 0xdf01 }, 193 + { 0x02, 0xdf20 }, 194 + { 0x01, 0xff95 }, 195 + { 0x00, 0xba00 }, 196 + { 0x04, 0xa800 }, 197 + { 0x04, 0xf000 }, 198 + { 0x03, 0xdf01 }, 199 + { 0x02, 0xdf20 }, 200 + { 0x01, 0x101a }, 201 + { 0x00, 0xa0ff }, 202 + { 0x04, 0xf800 }, 203 + { 0x04, 0x0000 }, 204 + { 0x1f, 0x0000 }, 205 + 206 + { 0x1f, 0x0001 }, 207 + { 0x10, 0xf41b }, 208 + { 0x14, 0xfb54 }, 209 + { 0x18, 0xf5c7 }, 210 + { 0x1f, 0x0000 }, 211 + 212 + { 0x1f, 0x0001 }, 213 + { 0x17, 0x0cc0 }, 214 + { 0x1f, 0x0000 } 215 + }; 216 + 217 + rtl_writephy_batch(phydev, phy_reg_init); 218 + } 219 + 220 + static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp, 221 + struct phy_device *phydev) 222 + { 223 + static const struct phy_reg phy_reg_init[] = { 224 + { 0x1f, 0x0001 }, 225 + { 0x04, 0x0000 }, 226 + { 0x03, 0x00a1 }, 227 + { 0x02, 0x0008 }, 228 + { 0x01, 0x0120 }, 229 + { 0x00, 0x1000 }, 230 + { 0x04, 0x0800 }, 231 + { 0x04, 0x9000 }, 232 + { 0x03, 0x802f }, 233 + { 0x02, 0x4f02 }, 234 + { 0x01, 0x0409 }, 235 + { 0x00, 0xf099 }, 236 + { 0x04, 0x9800 }, 237 + { 0x04, 0xa000 }, 238 + { 0x03, 0xdf01 }, 239 + { 0x02, 0xdf20 }, 240 + { 0x01, 0xff95 }, 241 + { 0x00, 0xba00 }, 242 + { 0x04, 0xa800 }, 243 + { 0x04, 0xf000 }, 244 + { 0x03, 0xdf01 }, 245 + { 0x02, 0xdf20 }, 246 + { 0x01, 0x101a }, 247 + { 0x00, 0xa0ff }, 248 + { 0x04, 0xf800 }, 249 + { 0x04, 0x0000 }, 250 + { 0x1f, 0x0000 }, 251 + 252 + { 0x1f, 0x0001 }, 253 + { 0x0b, 0x8480 }, 254 + { 0x1f, 0x0000 }, 255 + 256 + { 0x1f, 0x0001 }, 257 + { 0x18, 0x67c7 }, 258 + { 0x04, 0x2000 }, 259 + { 0x03, 0x002f }, 260 + { 0x02, 0x4360 }, 261 + { 0x01, 0x0109 }, 262 + { 0x00, 0x3022 }, 263 + { 0x04, 0x2800 }, 264 + { 0x1f, 0x0000 }, 265 + 266 + { 0x1f, 0x0001 }, 267 + { 0x17, 0x0cc0 }, 268 + { 0x1f, 0x0000 } 269 + }; 270 + 271 + rtl_writephy_batch(phydev, phy_reg_init); 272 + } 273 + 274 + static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp, 275 + struct phy_device *phydev) 276 + { 277 + phy_write(phydev, 0x1f, 0x0001); 278 + phy_set_bits(phydev, 0x16, BIT(0)); 279 + phy_write(phydev, 0x10, 0xf41b); 280 + phy_write(phydev, 0x1f, 0x0000); 281 + } 282 + 283 + static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp, 284 + struct phy_device *phydev) 285 + { 286 + phy_write_paged(phydev, 0x0001, 0x10, 0xf41b); 287 + } 288 + 289 + static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp, 290 + struct phy_device *phydev) 291 + { 292 + phy_write(phydev, 0x1d, 0x0f00); 293 + phy_write_paged(phydev, 0x0002, 0x0c, 0x1ec8); 294 + } 295 + 296 + static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp, 297 + struct phy_device *phydev) 298 + { 299 + phy_set_bits(phydev, 0x14, BIT(5)); 300 + phy_set_bits(phydev, 0x0d, BIT(5)); 301 + phy_write_paged(phydev, 0x0001, 0x1d, 0x3d98); 302 + } 303 + 304 + static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp, 305 + struct phy_device *phydev) 306 + { 307 + static const struct phy_reg phy_reg_init[] = { 308 + { 0x1f, 0x0001 }, 309 + { 0x12, 0x2300 }, 310 + { 0x1f, 0x0002 }, 311 + { 0x00, 0x88d4 }, 312 + { 0x01, 0x82b1 }, 313 + { 0x03, 0x7002 }, 314 + { 0x08, 0x9e30 }, 315 + { 0x09, 0x01f0 }, 316 + { 0x0a, 0x5500 }, 317 + { 0x0c, 0x00c8 }, 318 + { 0x1f, 0x0003 }, 319 + { 0x12, 0xc096 }, 320 + { 0x16, 0x000a }, 321 + { 0x1f, 0x0000 }, 322 + { 0x1f, 0x0000 }, 323 + { 0x09, 0x2000 }, 324 + { 0x09, 0x0000 } 325 + }; 326 + 327 + rtl_writephy_batch(phydev, phy_reg_init); 328 + 329 + phy_set_bits(phydev, 0x14, BIT(5)); 330 + phy_set_bits(phydev, 0x0d, BIT(5)); 331 + } 332 + 333 + static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp, 334 + struct phy_device *phydev) 335 + { 336 + static const struct phy_reg phy_reg_init[] = { 337 + { 0x1f, 0x0001 }, 338 + { 0x12, 0x2300 }, 339 + { 0x03, 0x802f }, 340 + { 0x02, 0x4f02 }, 341 + { 0x01, 0x0409 }, 342 + { 0x00, 0xf099 }, 343 + { 0x04, 0x9800 }, 344 + { 0x04, 0x9000 }, 345 + { 0x1d, 0x3d98 }, 346 + { 0x1f, 0x0002 }, 347 + { 0x0c, 0x7eb8 }, 348 + { 0x06, 0x0761 }, 349 + { 0x1f, 0x0003 }, 350 + { 0x16, 0x0f0a }, 351 + { 0x1f, 0x0000 } 352 + }; 353 + 354 + rtl_writephy_batch(phydev, phy_reg_init); 355 + 356 + phy_set_bits(phydev, 0x16, BIT(0)); 357 + phy_set_bits(phydev, 0x14, BIT(5)); 358 + phy_set_bits(phydev, 0x0d, BIT(5)); 359 + } 360 + 361 + static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp, 362 + struct phy_device *phydev) 363 + { 364 + static const struct phy_reg phy_reg_init[] = { 365 + { 0x1f, 0x0001 }, 366 + { 0x12, 0x2300 }, 367 + { 0x1d, 0x3d98 }, 368 + { 0x1f, 0x0002 }, 369 + { 0x0c, 0x7eb8 }, 370 + { 0x06, 0x5461 }, 371 + { 0x1f, 0x0003 }, 372 + { 0x16, 0x0f0a }, 373 + { 0x1f, 0x0000 } 374 + }; 375 + 376 + rtl_writephy_batch(phydev, phy_reg_init); 377 + 378 + phy_set_bits(phydev, 0x16, BIT(0)); 379 + phy_set_bits(phydev, 0x14, BIT(5)); 380 + phy_set_bits(phydev, 0x0d, BIT(5)); 381 + } 382 + 383 + static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = { 384 + /* Channel Estimation */ 385 + { 0x1f, 0x0001 }, 386 + { 0x06, 0x4064 }, 387 + { 0x07, 0x2863 }, 388 + { 0x08, 0x059c }, 389 + { 0x09, 0x26b4 }, 390 + { 0x0a, 0x6a19 }, 391 + { 0x0b, 0xdcc8 }, 392 + { 0x10, 0xf06d }, 393 + { 0x14, 0x7f68 }, 394 + { 0x18, 0x7fd9 }, 395 + { 0x1c, 0xf0ff }, 396 + { 0x1d, 0x3d9c }, 397 + { 0x1f, 0x0003 }, 398 + { 0x12, 0xf49f }, 399 + { 0x13, 0x070b }, 400 + { 0x1a, 0x05ad }, 401 + { 0x14, 0x94c0 }, 402 + 403 + /* 404 + * Tx Error Issue 405 + * Enhance line driver power 406 + */ 407 + { 0x1f, 0x0002 }, 408 + { 0x06, 0x5561 }, 409 + { 0x1f, 0x0005 }, 410 + { 0x05, 0x8332 }, 411 + { 0x06, 0x5561 }, 412 + 413 + /* 414 + * Can not link to 1Gbps with bad cable 415 + * Decrease SNR threshold form 21.07dB to 19.04dB 416 + */ 417 + { 0x1f, 0x0001 }, 418 + { 0x17, 0x0cc0 }, 419 + 420 + { 0x1f, 0x0000 }, 421 + { 0x0d, 0xf880 } 422 + }; 423 + 424 + static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = { 425 + { 0x1f, 0x0002 }, 426 + { 0x05, 0x669a }, 427 + { 0x1f, 0x0005 }, 428 + { 0x05, 0x8330 }, 429 + { 0x06, 0x669a }, 430 + { 0x1f, 0x0002 } 431 + }; 432 + 433 + static void rtl8168d_apply_firmware_cond(struct rtl8169_private *tp, 434 + struct phy_device *phydev, 435 + u16 val) 436 + { 437 + u16 reg_val; 438 + 439 + phy_write(phydev, 0x1f, 0x0005); 440 + phy_write(phydev, 0x05, 0x001b); 441 + reg_val = phy_read(phydev, 0x06); 442 + phy_write(phydev, 0x1f, 0x0000); 443 + 444 + if (reg_val != val) 445 + phydev_warn(phydev, "chipset not ready for firmware\n"); 446 + else 447 + r8169_apply_firmware(tp); 448 + } 449 + 450 + static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp, 451 + struct phy_device *phydev) 452 + { 453 + rtl_writephy_batch(phydev, rtl8168d_1_phy_reg_init_0); 454 + 455 + /* 456 + * Rx Error Issue 457 + * Fine Tune Switching regulator parameter 458 + */ 459 + phy_write(phydev, 0x1f, 0x0002); 460 + phy_modify(phydev, 0x0b, 0x00ef, 0x0010); 461 + phy_modify(phydev, 0x0c, 0x5d00, 0xa200); 462 + 463 + if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { 464 + int val; 465 + 466 + rtl_writephy_batch(phydev, rtl8168d_1_phy_reg_init_1); 467 + 468 + val = phy_read(phydev, 0x0d); 469 + 470 + if ((val & 0x00ff) != 0x006c) { 471 + static const u32 set[] = { 472 + 0x0065, 0x0066, 0x0067, 0x0068, 473 + 0x0069, 0x006a, 0x006b, 0x006c 474 + }; 475 + int i; 476 + 477 + phy_write(phydev, 0x1f, 0x0002); 478 + 479 + val &= 0xff00; 480 + for (i = 0; i < ARRAY_SIZE(set); i++) 481 + phy_write(phydev, 0x0d, val | set[i]); 482 + } 483 + } else { 484 + phy_write_paged(phydev, 0x0002, 0x05, 0x6662); 485 + r8168d_phy_param(phydev, 0x8330, 0xffff, 0x6662); 486 + } 487 + 488 + /* RSET couple improve */ 489 + phy_write(phydev, 0x1f, 0x0002); 490 + phy_set_bits(phydev, 0x0d, 0x0300); 491 + phy_set_bits(phydev, 0x0f, 0x0010); 492 + 493 + /* Fine tune PLL performance */ 494 + phy_write(phydev, 0x1f, 0x0002); 495 + phy_modify(phydev, 0x02, 0x0600, 0x0100); 496 + phy_clear_bits(phydev, 0x03, 0xe000); 497 + phy_write(phydev, 0x1f, 0x0000); 498 + 499 + rtl8168d_apply_firmware_cond(tp, phydev, 0xbf00); 500 + } 501 + 502 + static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp, 503 + struct phy_device *phydev) 504 + { 505 + rtl_writephy_batch(phydev, rtl8168d_1_phy_reg_init_0); 506 + 507 + if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { 508 + int val; 509 + 510 + rtl_writephy_batch(phydev, rtl8168d_1_phy_reg_init_1); 511 + 512 + val = phy_read(phydev, 0x0d); 513 + if ((val & 0x00ff) != 0x006c) { 514 + static const u32 set[] = { 515 + 0x0065, 0x0066, 0x0067, 0x0068, 516 + 0x0069, 0x006a, 0x006b, 0x006c 517 + }; 518 + int i; 519 + 520 + phy_write(phydev, 0x1f, 0x0002); 521 + 522 + val &= 0xff00; 523 + for (i = 0; i < ARRAY_SIZE(set); i++) 524 + phy_write(phydev, 0x0d, val | set[i]); 525 + } 526 + } else { 527 + phy_write_paged(phydev, 0x0002, 0x05, 0x2642); 528 + r8168d_phy_param(phydev, 0x8330, 0xffff, 0x2642); 529 + } 530 + 531 + /* Fine tune PLL performance */ 532 + phy_write(phydev, 0x1f, 0x0002); 533 + phy_modify(phydev, 0x02, 0x0600, 0x0100); 534 + phy_clear_bits(phydev, 0x03, 0xe000); 535 + phy_write(phydev, 0x1f, 0x0000); 536 + 537 + /* Switching regulator Slew rate */ 538 + phy_modify_paged(phydev, 0x0002, 0x0f, 0x0000, 0x0017); 539 + 540 + rtl8168d_apply_firmware_cond(tp, phydev, 0xb300); 541 + } 542 + 543 + static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp, 544 + struct phy_device *phydev) 545 + { 546 + static const struct phy_reg phy_reg_init[] = { 547 + { 0x1f, 0x0002 }, 548 + { 0x10, 0x0008 }, 549 + { 0x0d, 0x006c }, 550 + 551 + { 0x1f, 0x0000 }, 552 + { 0x0d, 0xf880 }, 553 + 554 + { 0x1f, 0x0001 }, 555 + { 0x17, 0x0cc0 }, 556 + 557 + { 0x1f, 0x0001 }, 558 + { 0x0b, 0xa4d8 }, 559 + { 0x09, 0x281c }, 560 + { 0x07, 0x2883 }, 561 + { 0x0a, 0x6b35 }, 562 + { 0x1d, 0x3da4 }, 563 + { 0x1c, 0xeffd }, 564 + { 0x14, 0x7f52 }, 565 + { 0x18, 0x7fc6 }, 566 + { 0x08, 0x0601 }, 567 + { 0x06, 0x4063 }, 568 + { 0x10, 0xf074 }, 569 + { 0x1f, 0x0003 }, 570 + { 0x13, 0x0789 }, 571 + { 0x12, 0xf4bd }, 572 + { 0x1a, 0x04fd }, 573 + { 0x14, 0x84b0 }, 574 + { 0x1f, 0x0000 }, 575 + { 0x00, 0x9200 }, 576 + 577 + { 0x1f, 0x0005 }, 578 + { 0x01, 0x0340 }, 579 + { 0x1f, 0x0001 }, 580 + { 0x04, 0x4000 }, 581 + { 0x03, 0x1d21 }, 582 + { 0x02, 0x0c32 }, 583 + { 0x01, 0x0200 }, 584 + { 0x00, 0x5554 }, 585 + { 0x04, 0x4800 }, 586 + { 0x04, 0x4000 }, 587 + { 0x04, 0xf000 }, 588 + { 0x03, 0xdf01 }, 589 + { 0x02, 0xdf20 }, 590 + { 0x01, 0x101a }, 591 + { 0x00, 0xa0ff }, 592 + { 0x04, 0xf800 }, 593 + { 0x04, 0xf000 }, 594 + { 0x1f, 0x0000 }, 595 + }; 596 + 597 + rtl_writephy_batch(phydev, phy_reg_init); 598 + r8168d_modify_extpage(phydev, 0x0023, 0x16, 0xffff, 0x0000); 599 + } 600 + 601 + static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp, 602 + struct phy_device *phydev) 603 + { 604 + phy_write_paged(phydev, 0x0001, 0x17, 0x0cc0); 605 + r8168d_modify_extpage(phydev, 0x002d, 0x18, 0xffff, 0x0040); 606 + phy_set_bits(phydev, 0x0d, BIT(5)); 607 + } 608 + 609 + static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp, 610 + struct phy_device *phydev) 611 + { 612 + static const struct phy_reg phy_reg_init[] = { 613 + /* Channel estimation fine tune */ 614 + { 0x1f, 0x0001 }, 615 + { 0x0b, 0x6c20 }, 616 + { 0x07, 0x2872 }, 617 + { 0x1c, 0xefff }, 618 + { 0x1f, 0x0003 }, 619 + { 0x14, 0x6420 }, 620 + { 0x1f, 0x0000 }, 621 + }; 622 + 623 + r8169_apply_firmware(tp); 624 + 625 + /* Enable Delay cap */ 626 + r8168d_phy_param(phydev, 0x8b80, 0xffff, 0xc896); 627 + 628 + rtl_writephy_batch(phydev, phy_reg_init); 629 + 630 + /* Update PFM & 10M TX idle timer */ 631 + r8168d_modify_extpage(phydev, 0x002f, 0x15, 0xffff, 0x1919); 632 + 633 + r8168d_modify_extpage(phydev, 0x00ac, 0x18, 0xffff, 0x0006); 634 + 635 + /* DCO enable for 10M IDLE Power */ 636 + r8168d_modify_extpage(phydev, 0x0023, 0x17, 0x0000, 0x0006); 637 + 638 + /* For impedance matching */ 639 + phy_modify_paged(phydev, 0x0002, 0x08, 0x7f00, 0x8000); 640 + 641 + /* PHY auto speed down */ 642 + r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0050); 643 + phy_set_bits(phydev, 0x14, BIT(15)); 644 + 645 + r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001); 646 + r8168d_phy_param(phydev, 0x8b85, 0x2000, 0x0000); 647 + 648 + r8168d_modify_extpage(phydev, 0x0020, 0x15, 0x1100, 0x0000); 649 + phy_write_paged(phydev, 0x0006, 0x00, 0x5a00); 650 + 651 + phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0000); 652 + } 653 + 654 + static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp, 655 + struct phy_device *phydev) 656 + { 657 + r8169_apply_firmware(tp); 658 + 659 + /* Enable Delay cap */ 660 + r8168d_modify_extpage(phydev, 0x00ac, 0x18, 0xffff, 0x0006); 661 + 662 + /* Channel estimation fine tune */ 663 + phy_write_paged(phydev, 0x0003, 0x09, 0xa20f); 664 + 665 + /* Green Setting */ 666 + r8168d_phy_param(phydev, 0x8b5b, 0xffff, 0x9222); 667 + r8168d_phy_param(phydev, 0x8b6d, 0xffff, 0x8000); 668 + r8168d_phy_param(phydev, 0x8b76, 0xffff, 0x8000); 669 + 670 + /* For 4-corner performance improve */ 671 + phy_write(phydev, 0x1f, 0x0005); 672 + phy_write(phydev, 0x05, 0x8b80); 673 + phy_set_bits(phydev, 0x17, 0x0006); 674 + phy_write(phydev, 0x1f, 0x0000); 675 + 676 + /* PHY auto speed down */ 677 + r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0010); 678 + phy_set_bits(phydev, 0x14, BIT(15)); 679 + 680 + /* improve 10M EEE waveform */ 681 + r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001); 682 + 683 + /* Improve 2-pair detection performance */ 684 + r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000); 685 + 686 + rtl8168f_config_eee_phy(phydev); 687 + 688 + /* Green feature */ 689 + phy_write(phydev, 0x1f, 0x0003); 690 + phy_set_bits(phydev, 0x19, BIT(0)); 691 + phy_set_bits(phydev, 0x10, BIT(10)); 692 + phy_write(phydev, 0x1f, 0x0000); 693 + phy_modify_paged(phydev, 0x0005, 0x01, 0, BIT(8)); 694 + } 695 + 696 + static void rtl8168f_hw_phy_config(struct rtl8169_private *tp, 697 + struct phy_device *phydev) 698 + { 699 + /* For 4-corner performance improve */ 700 + r8168d_phy_param(phydev, 0x8b80, 0x0000, 0x0006); 701 + 702 + /* PHY auto speed down */ 703 + r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0010); 704 + phy_set_bits(phydev, 0x14, BIT(15)); 705 + 706 + /* Improve 10M EEE waveform */ 707 + r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001); 708 + 709 + rtl8168f_config_eee_phy(phydev); 710 + } 711 + 712 + static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp, 713 + struct phy_device *phydev) 714 + { 715 + r8169_apply_firmware(tp); 716 + 717 + /* Channel estimation fine tune */ 718 + phy_write_paged(phydev, 0x0003, 0x09, 0xa20f); 719 + 720 + /* Modify green table for giga & fnet */ 721 + r8168d_phy_param(phydev, 0x8b55, 0xffff, 0x0000); 722 + r8168d_phy_param(phydev, 0x8b5e, 0xffff, 0x0000); 723 + r8168d_phy_param(phydev, 0x8b67, 0xffff, 0x0000); 724 + r8168d_phy_param(phydev, 0x8b70, 0xffff, 0x0000); 725 + r8168d_modify_extpage(phydev, 0x0078, 0x17, 0xffff, 0x0000); 726 + r8168d_modify_extpage(phydev, 0x0078, 0x19, 0xffff, 0x00fb); 727 + 728 + /* Modify green table for 10M */ 729 + r8168d_phy_param(phydev, 0x8b79, 0xffff, 0xaa00); 730 + 731 + /* Disable hiimpedance detection (RTCT) */ 732 + phy_write_paged(phydev, 0x0003, 0x01, 0x328a); 733 + 734 + rtl8168f_hw_phy_config(tp, phydev); 735 + 736 + /* Improve 2-pair detection performance */ 737 + r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000); 738 + } 739 + 740 + static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp, 741 + struct phy_device *phydev) 742 + { 743 + r8169_apply_firmware(tp); 744 + 745 + rtl8168f_hw_phy_config(tp, phydev); 746 + } 747 + 748 + static void rtl8411_hw_phy_config(struct rtl8169_private *tp, 749 + struct phy_device *phydev) 750 + { 751 + r8169_apply_firmware(tp); 752 + 753 + rtl8168f_hw_phy_config(tp, phydev); 754 + 755 + /* Improve 2-pair detection performance */ 756 + r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000); 757 + 758 + /* Channel estimation fine tune */ 759 + phy_write_paged(phydev, 0x0003, 0x09, 0xa20f); 760 + 761 + /* Modify green table for giga & fnet */ 762 + r8168d_phy_param(phydev, 0x8b55, 0xffff, 0x0000); 763 + r8168d_phy_param(phydev, 0x8b5e, 0xffff, 0x0000); 764 + r8168d_phy_param(phydev, 0x8b67, 0xffff, 0x0000); 765 + r8168d_phy_param(phydev, 0x8b70, 0xffff, 0x0000); 766 + r8168d_modify_extpage(phydev, 0x0078, 0x17, 0xffff, 0x0000); 767 + r8168d_modify_extpage(phydev, 0x0078, 0x19, 0xffff, 0x00aa); 768 + 769 + /* Modify green table for 10M */ 770 + r8168d_phy_param(phydev, 0x8b79, 0xffff, 0xaa00); 771 + 772 + /* Disable hiimpedance detection (RTCT) */ 773 + phy_write_paged(phydev, 0x0003, 0x01, 0x328a); 774 + 775 + /* Modify green table for giga */ 776 + r8168d_phy_param(phydev, 0x8b54, 0x0800, 0x0000); 777 + r8168d_phy_param(phydev, 0x8b5d, 0x0800, 0x0000); 778 + r8168d_phy_param(phydev, 0x8a7c, 0x0100, 0x0000); 779 + r8168d_phy_param(phydev, 0x8a7f, 0x0000, 0x0100); 780 + r8168d_phy_param(phydev, 0x8a82, 0x0100, 0x0000); 781 + r8168d_phy_param(phydev, 0x8a85, 0x0100, 0x0000); 782 + r8168d_phy_param(phydev, 0x8a88, 0x0100, 0x0000); 783 + 784 + /* uc same-seed solution */ 785 + r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x8000); 786 + 787 + /* Green feature */ 788 + phy_write(phydev, 0x1f, 0x0003); 789 + phy_clear_bits(phydev, 0x19, BIT(0)); 790 + phy_clear_bits(phydev, 0x10, BIT(10)); 791 + phy_write(phydev, 0x1f, 0x0000); 792 + } 793 + 794 + static void rtl8168g_disable_aldps(struct phy_device *phydev) 795 + { 796 + phy_modify_paged(phydev, 0x0a43, 0x10, BIT(2), 0); 797 + } 798 + 799 + static void rtl8168g_phy_adjust_10m_aldps(struct phy_device *phydev) 800 + { 801 + phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0); 802 + phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6)); 803 + r8168g_phy_param(phydev, 0x8084, 0x6000, 0x0000); 804 + phy_modify_paged(phydev, 0x0a43, 0x10, 0x0000, 0x1003); 805 + } 806 + 807 + static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp, 808 + struct phy_device *phydev) 809 + { 810 + int ret; 811 + 812 + r8169_apply_firmware(tp); 813 + 814 + ret = phy_read_paged(phydev, 0x0a46, 0x10); 815 + if (ret & BIT(8)) 816 + phy_modify_paged(phydev, 0x0bcc, 0x12, BIT(15), 0); 817 + else 818 + phy_modify_paged(phydev, 0x0bcc, 0x12, 0, BIT(15)); 819 + 820 + ret = phy_read_paged(phydev, 0x0a46, 0x13); 821 + if (ret & BIT(8)) 822 + phy_modify_paged(phydev, 0x0c41, 0x15, 0, BIT(1)); 823 + else 824 + phy_modify_paged(phydev, 0x0c41, 0x15, BIT(1), 0); 825 + 826 + /* Enable PHY auto speed down */ 827 + phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2)); 828 + 829 + rtl8168g_phy_adjust_10m_aldps(phydev); 830 + 831 + /* EEE auto-fallback function */ 832 + phy_modify_paged(phydev, 0x0a4b, 0x11, 0, BIT(2)); 833 + 834 + /* Enable UC LPF tune function */ 835 + r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000); 836 + 837 + phy_modify_paged(phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 838 + 839 + /* Improve SWR Efficiency */ 840 + phy_write(phydev, 0x1f, 0x0bcd); 841 + phy_write(phydev, 0x14, 0x5065); 842 + phy_write(phydev, 0x14, 0xd065); 843 + phy_write(phydev, 0x1f, 0x0bc8); 844 + phy_write(phydev, 0x11, 0x5655); 845 + phy_write(phydev, 0x1f, 0x0bcd); 846 + phy_write(phydev, 0x14, 0x1065); 847 + phy_write(phydev, 0x14, 0x9065); 848 + phy_write(phydev, 0x14, 0x1065); 849 + phy_write(phydev, 0x1f, 0x0000); 850 + 851 + rtl8168g_disable_aldps(phydev); 852 + rtl8168g_config_eee_phy(phydev); 853 + } 854 + 855 + static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp, 856 + struct phy_device *phydev) 857 + { 858 + r8169_apply_firmware(tp); 859 + rtl8168g_config_eee_phy(phydev); 860 + } 861 + 862 + static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp, 863 + struct phy_device *phydev) 864 + { 865 + u16 dout_tapbin; 866 + u32 data; 867 + 868 + r8169_apply_firmware(tp); 869 + 870 + /* CHN EST parameters adjust - giga master */ 871 + r8168g_phy_param(phydev, 0x809b, 0xf800, 0x8000); 872 + r8168g_phy_param(phydev, 0x80a2, 0xff00, 0x8000); 873 + r8168g_phy_param(phydev, 0x80a4, 0xff00, 0x8500); 874 + r8168g_phy_param(phydev, 0x809c, 0xff00, 0xbd00); 875 + 876 + /* CHN EST parameters adjust - giga slave */ 877 + r8168g_phy_param(phydev, 0x80ad, 0xf800, 0x7000); 878 + r8168g_phy_param(phydev, 0x80b4, 0xff00, 0x5000); 879 + r8168g_phy_param(phydev, 0x80ac, 0xff00, 0x4000); 880 + 881 + /* CHN EST parameters adjust - fnet */ 882 + r8168g_phy_param(phydev, 0x808e, 0xff00, 0x1200); 883 + r8168g_phy_param(phydev, 0x8090, 0xff00, 0xe500); 884 + r8168g_phy_param(phydev, 0x8092, 0xff00, 0x9f00); 885 + 886 + /* enable R-tune & PGA-retune function */ 887 + dout_tapbin = 0; 888 + data = phy_read_paged(phydev, 0x0a46, 0x13); 889 + data &= 3; 890 + data <<= 2; 891 + dout_tapbin |= data; 892 + data = phy_read_paged(phydev, 0x0a46, 0x12); 893 + data &= 0xc000; 894 + data >>= 14; 895 + dout_tapbin |= data; 896 + dout_tapbin = ~(dout_tapbin ^ 0x08); 897 + dout_tapbin <<= 12; 898 + dout_tapbin &= 0xf000; 899 + 900 + r8168g_phy_param(phydev, 0x827a, 0xf000, dout_tapbin); 901 + r8168g_phy_param(phydev, 0x827b, 0xf000, dout_tapbin); 902 + r8168g_phy_param(phydev, 0x827c, 0xf000, dout_tapbin); 903 + r8168g_phy_param(phydev, 0x827d, 0xf000, dout_tapbin); 904 + r8168g_phy_param(phydev, 0x0811, 0x0000, 0x0800); 905 + phy_modify_paged(phydev, 0x0a42, 0x16, 0x0000, 0x0002); 906 + 907 + /* enable GPHY 10M */ 908 + phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(11)); 909 + 910 + /* SAR ADC performance */ 911 + phy_modify_paged(phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14)); 912 + 913 + r8168g_phy_param(phydev, 0x803f, 0x3000, 0x0000); 914 + r8168g_phy_param(phydev, 0x8047, 0x3000, 0x0000); 915 + r8168g_phy_param(phydev, 0x804f, 0x3000, 0x0000); 916 + r8168g_phy_param(phydev, 0x8057, 0x3000, 0x0000); 917 + r8168g_phy_param(phydev, 0x805f, 0x3000, 0x0000); 918 + r8168g_phy_param(phydev, 0x8067, 0x3000, 0x0000); 919 + r8168g_phy_param(phydev, 0x806f, 0x3000, 0x0000); 920 + 921 + /* disable phy pfm mode */ 922 + phy_modify_paged(phydev, 0x0a44, 0x11, BIT(7), 0); 923 + 924 + rtl8168g_disable_aldps(phydev); 925 + rtl8168h_config_eee_phy(phydev); 926 + } 927 + 928 + static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp, 929 + struct phy_device *phydev) 930 + { 931 + u16 ioffset, rlen; 932 + u32 data; 933 + 934 + r8169_apply_firmware(tp); 935 + 936 + /* CHIN EST parameter update */ 937 + r8168g_phy_param(phydev, 0x808a, 0x003f, 0x000a); 938 + 939 + /* enable R-tune & PGA-retune function */ 940 + r8168g_phy_param(phydev, 0x0811, 0x0000, 0x0800); 941 + phy_modify_paged(phydev, 0x0a42, 0x16, 0x0000, 0x0002); 942 + 943 + /* enable GPHY 10M */ 944 + phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(11)); 945 + 946 + ioffset = rtl8168h_2_get_adc_bias_ioffset(tp); 947 + if (ioffset != 0xffff) 948 + phy_write_paged(phydev, 0x0bcf, 0x16, ioffset); 949 + 950 + /* Modify rlen (TX LPF corner frequency) level */ 951 + data = phy_read_paged(phydev, 0x0bcd, 0x16); 952 + data &= 0x000f; 953 + rlen = 0; 954 + if (data > 3) 955 + rlen = data - 3; 956 + data = rlen | (rlen << 4) | (rlen << 8) | (rlen << 12); 957 + phy_write_paged(phydev, 0x0bcd, 0x17, data); 958 + 959 + /* disable phy pfm mode */ 960 + phy_modify_paged(phydev, 0x0a44, 0x11, BIT(7), 0); 961 + 962 + rtl8168g_disable_aldps(phydev); 963 + rtl8168g_config_eee_phy(phydev); 964 + } 965 + 966 + static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp, 967 + struct phy_device *phydev) 968 + { 969 + /* Enable PHY auto speed down */ 970 + phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2)); 971 + 972 + rtl8168g_phy_adjust_10m_aldps(phydev); 973 + 974 + /* Enable EEE auto-fallback function */ 975 + phy_modify_paged(phydev, 0x0a4b, 0x11, 0, BIT(2)); 976 + 977 + /* Enable UC LPF tune function */ 978 + r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000); 979 + 980 + /* set rg_sel_sdm_rate */ 981 + phy_modify_paged(phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 982 + 983 + rtl8168g_disable_aldps(phydev); 984 + rtl8168g_config_eee_phy(phydev); 985 + } 986 + 987 + static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp, 988 + struct phy_device *phydev) 989 + { 990 + rtl8168g_phy_adjust_10m_aldps(phydev); 991 + 992 + /* Enable UC LPF tune function */ 993 + r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000); 994 + 995 + /* Set rg_sel_sdm_rate */ 996 + phy_modify_paged(phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 997 + 998 + /* Channel estimation parameters */ 999 + r8168g_phy_param(phydev, 0x80f3, 0xff00, 0x8b00); 1000 + r8168g_phy_param(phydev, 0x80f0, 0xff00, 0x3a00); 1001 + r8168g_phy_param(phydev, 0x80ef, 0xff00, 0x0500); 1002 + r8168g_phy_param(phydev, 0x80f6, 0xff00, 0x6e00); 1003 + r8168g_phy_param(phydev, 0x80ec, 0xff00, 0x6800); 1004 + r8168g_phy_param(phydev, 0x80ed, 0xff00, 0x7c00); 1005 + r8168g_phy_param(phydev, 0x80f2, 0xff00, 0xf400); 1006 + r8168g_phy_param(phydev, 0x80f4, 0xff00, 0x8500); 1007 + r8168g_phy_param(phydev, 0x8110, 0xff00, 0xa800); 1008 + r8168g_phy_param(phydev, 0x810f, 0xff00, 0x1d00); 1009 + r8168g_phy_param(phydev, 0x8111, 0xff00, 0xf500); 1010 + r8168g_phy_param(phydev, 0x8113, 0xff00, 0x6100); 1011 + r8168g_phy_param(phydev, 0x8115, 0xff00, 0x9200); 1012 + r8168g_phy_param(phydev, 0x810e, 0xff00, 0x0400); 1013 + r8168g_phy_param(phydev, 0x810c, 0xff00, 0x7c00); 1014 + r8168g_phy_param(phydev, 0x810b, 0xff00, 0x5a00); 1015 + r8168g_phy_param(phydev, 0x80d1, 0xff00, 0xff00); 1016 + r8168g_phy_param(phydev, 0x80cd, 0xff00, 0x9e00); 1017 + r8168g_phy_param(phydev, 0x80d3, 0xff00, 0x0e00); 1018 + r8168g_phy_param(phydev, 0x80d5, 0xff00, 0xca00); 1019 + r8168g_phy_param(phydev, 0x80d7, 0xff00, 0x8400); 1020 + 1021 + /* Force PWM-mode */ 1022 + phy_write(phydev, 0x1f, 0x0bcd); 1023 + phy_write(phydev, 0x14, 0x5065); 1024 + phy_write(phydev, 0x14, 0xd065); 1025 + phy_write(phydev, 0x1f, 0x0bc8); 1026 + phy_write(phydev, 0x12, 0x00ed); 1027 + phy_write(phydev, 0x1f, 0x0bcd); 1028 + phy_write(phydev, 0x14, 0x1065); 1029 + phy_write(phydev, 0x14, 0x9065); 1030 + phy_write(phydev, 0x14, 0x1065); 1031 + phy_write(phydev, 0x1f, 0x0000); 1032 + 1033 + rtl8168g_disable_aldps(phydev); 1034 + rtl8168g_config_eee_phy(phydev); 1035 + } 1036 + 1037 + static void rtl8117_hw_phy_config(struct rtl8169_private *tp, 1038 + struct phy_device *phydev) 1039 + { 1040 + /* CHN EST parameters adjust - fnet */ 1041 + r8168g_phy_param(phydev, 0x808e, 0xff00, 0x4800); 1042 + r8168g_phy_param(phydev, 0x8090, 0xff00, 0xcc00); 1043 + r8168g_phy_param(phydev, 0x8092, 0xff00, 0xb000); 1044 + 1045 + r8168g_phy_param(phydev, 0x8088, 0xff00, 0x6000); 1046 + r8168g_phy_param(phydev, 0x808b, 0x3f00, 0x0b00); 1047 + r8168g_phy_param(phydev, 0x808d, 0x1f00, 0x0600); 1048 + r8168g_phy_param(phydev, 0x808c, 0xff00, 0xb000); 1049 + r8168g_phy_param(phydev, 0x80a0, 0xff00, 0x2800); 1050 + r8168g_phy_param(phydev, 0x80a2, 0xff00, 0x5000); 1051 + r8168g_phy_param(phydev, 0x809b, 0xf800, 0xb000); 1052 + r8168g_phy_param(phydev, 0x809a, 0xff00, 0x4b00); 1053 + r8168g_phy_param(phydev, 0x809d, 0x3f00, 0x0800); 1054 + r8168g_phy_param(phydev, 0x80a1, 0xff00, 0x7000); 1055 + r8168g_phy_param(phydev, 0x809f, 0x1f00, 0x0300); 1056 + r8168g_phy_param(phydev, 0x809e, 0xff00, 0x8800); 1057 + r8168g_phy_param(phydev, 0x80b2, 0xff00, 0x2200); 1058 + r8168g_phy_param(phydev, 0x80ad, 0xf800, 0x9800); 1059 + r8168g_phy_param(phydev, 0x80af, 0x3f00, 0x0800); 1060 + r8168g_phy_param(phydev, 0x80b3, 0xff00, 0x6f00); 1061 + r8168g_phy_param(phydev, 0x80b1, 0x1f00, 0x0300); 1062 + r8168g_phy_param(phydev, 0x80b0, 0xff00, 0x9300); 1063 + 1064 + r8168g_phy_param(phydev, 0x8011, 0x0000, 0x0800); 1065 + 1066 + /* enable GPHY 10M */ 1067 + phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(11)); 1068 + 1069 + r8168g_phy_param(phydev, 0x8016, 0x0000, 0x0400); 1070 + 1071 + rtl8168g_disable_aldps(phydev); 1072 + rtl8168h_config_eee_phy(phydev); 1073 + } 1074 + 1075 + static void rtl8102e_hw_phy_config(struct rtl8169_private *tp, 1076 + struct phy_device *phydev) 1077 + { 1078 + static const struct phy_reg phy_reg_init[] = { 1079 + { 0x1f, 0x0003 }, 1080 + { 0x08, 0x441d }, 1081 + { 0x01, 0x9100 }, 1082 + { 0x1f, 0x0000 } 1083 + }; 1084 + 1085 + phy_set_bits(phydev, 0x11, BIT(12)); 1086 + phy_set_bits(phydev, 0x19, BIT(13)); 1087 + phy_set_bits(phydev, 0x10, BIT(15)); 1088 + 1089 + rtl_writephy_batch(phydev, phy_reg_init); 1090 + } 1091 + 1092 + static void rtl8105e_hw_phy_config(struct rtl8169_private *tp, 1093 + struct phy_device *phydev) 1094 + { 1095 + /* Disable ALDPS before ram code */ 1096 + phy_write(phydev, 0x18, 0x0310); 1097 + msleep(100); 1098 + 1099 + r8169_apply_firmware(tp); 1100 + 1101 + phy_write_paged(phydev, 0x0005, 0x1a, 0x0000); 1102 + phy_write_paged(phydev, 0x0004, 0x1c, 0x0000); 1103 + phy_write_paged(phydev, 0x0001, 0x15, 0x7701); 1104 + } 1105 + 1106 + static void rtl8402_hw_phy_config(struct rtl8169_private *tp, 1107 + struct phy_device *phydev) 1108 + { 1109 + /* Disable ALDPS before setting firmware */ 1110 + phy_write(phydev, 0x18, 0x0310); 1111 + msleep(20); 1112 + 1113 + r8169_apply_firmware(tp); 1114 + 1115 + /* EEE setting */ 1116 + phy_write(phydev, 0x1f, 0x0004); 1117 + phy_write(phydev, 0x10, 0x401f); 1118 + phy_write(phydev, 0x19, 0x7030); 1119 + phy_write(phydev, 0x1f, 0x0000); 1120 + } 1121 + 1122 + static void rtl8106e_hw_phy_config(struct rtl8169_private *tp, 1123 + struct phy_device *phydev) 1124 + { 1125 + static const struct phy_reg phy_reg_init[] = { 1126 + { 0x1f, 0x0004 }, 1127 + { 0x10, 0xc07f }, 1128 + { 0x19, 0x7030 }, 1129 + { 0x1f, 0x0000 } 1130 + }; 1131 + 1132 + /* Disable ALDPS before ram code */ 1133 + phy_write(phydev, 0x18, 0x0310); 1134 + msleep(100); 1135 + 1136 + r8169_apply_firmware(tp); 1137 + 1138 + rtl_writephy_batch(phydev, phy_reg_init); 1139 + } 1140 + 1141 + static void rtl8125_1_hw_phy_config(struct rtl8169_private *tp, 1142 + struct phy_device *phydev) 1143 + { 1144 + phy_modify_paged(phydev, 0xad4, 0x10, 0x03ff, 0x0084); 1145 + phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010); 1146 + phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x0006); 1147 + phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006); 1148 + phy_modify_paged(phydev, 0xac0, 0x14, 0x0000, 0x1100); 1149 + phy_modify_paged(phydev, 0xac8, 0x15, 0xf000, 0x7000); 1150 + phy_modify_paged(phydev, 0xad1, 0x14, 0x0000, 0x0400); 1151 + phy_modify_paged(phydev, 0xad1, 0x15, 0x0000, 0x03ff); 1152 + phy_modify_paged(phydev, 0xad1, 0x16, 0x0000, 0x03ff); 1153 + 1154 + r8168g_phy_param(phydev, 0x80ea, 0xff00, 0xc400); 1155 + r8168g_phy_param(phydev, 0x80eb, 0x0700, 0x0300); 1156 + r8168g_phy_param(phydev, 0x80f8, 0xff00, 0x1c00); 1157 + r8168g_phy_param(phydev, 0x80f1, 0xff00, 0x3000); 1158 + r8168g_phy_param(phydev, 0x80fe, 0xff00, 0xa500); 1159 + r8168g_phy_param(phydev, 0x8102, 0xff00, 0x5000); 1160 + r8168g_phy_param(phydev, 0x8105, 0xff00, 0x3300); 1161 + r8168g_phy_param(phydev, 0x8100, 0xff00, 0x7000); 1162 + r8168g_phy_param(phydev, 0x8104, 0xff00, 0xf000); 1163 + r8168g_phy_param(phydev, 0x8106, 0xff00, 0x6500); 1164 + r8168g_phy_param(phydev, 0x80dc, 0xff00, 0xed00); 1165 + r8168g_phy_param(phydev, 0x80df, 0x0000, 0x0100); 1166 + r8168g_phy_param(phydev, 0x80e1, 0x0100, 0x0000); 1167 + 1168 + phy_modify_paged(phydev, 0xbf0, 0x13, 0x003f, 0x0038); 1169 + r8168g_phy_param(phydev, 0x819f, 0xffff, 0xd0b6); 1170 + 1171 + phy_write_paged(phydev, 0xbc3, 0x12, 0x5555); 1172 + phy_modify_paged(phydev, 0xbf0, 0x15, 0x0e00, 0x0a00); 1173 + phy_modify_paged(phydev, 0xa5c, 0x10, 0x0400, 0x0000); 1174 + phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800); 1175 + 1176 + rtl8125_config_eee_phy(phydev); 1177 + } 1178 + 1179 + static void rtl8125_2_hw_phy_config(struct rtl8169_private *tp, 1180 + struct phy_device *phydev) 1181 + { 1182 + int i; 1183 + 1184 + phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010); 1185 + phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x03ff); 1186 + phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006); 1187 + phy_modify_paged(phydev, 0xac0, 0x14, 0x1100, 0x0000); 1188 + phy_modify_paged(phydev, 0xacc, 0x10, 0x0003, 0x0002); 1189 + phy_modify_paged(phydev, 0xad4, 0x10, 0x00e7, 0x0044); 1190 + phy_modify_paged(phydev, 0xac1, 0x12, 0x0080, 0x0000); 1191 + phy_modify_paged(phydev, 0xac8, 0x10, 0x0300, 0x0000); 1192 + phy_modify_paged(phydev, 0xac5, 0x17, 0x0007, 0x0002); 1193 + phy_write_paged(phydev, 0xad4, 0x16, 0x00a8); 1194 + phy_write_paged(phydev, 0xac5, 0x16, 0x01ff); 1195 + phy_modify_paged(phydev, 0xac8, 0x15, 0x00f0, 0x0030); 1196 + 1197 + phy_write(phydev, 0x1f, 0x0b87); 1198 + phy_write(phydev, 0x16, 0x80a2); 1199 + phy_write(phydev, 0x17, 0x0153); 1200 + phy_write(phydev, 0x16, 0x809c); 1201 + phy_write(phydev, 0x17, 0x0153); 1202 + phy_write(phydev, 0x1f, 0x0000); 1203 + 1204 + phy_write(phydev, 0x1f, 0x0a43); 1205 + phy_write(phydev, 0x13, 0x81B3); 1206 + phy_write(phydev, 0x14, 0x0043); 1207 + phy_write(phydev, 0x14, 0x00A7); 1208 + phy_write(phydev, 0x14, 0x00D6); 1209 + phy_write(phydev, 0x14, 0x00EC); 1210 + phy_write(phydev, 0x14, 0x00F6); 1211 + phy_write(phydev, 0x14, 0x00FB); 1212 + phy_write(phydev, 0x14, 0x00FD); 1213 + phy_write(phydev, 0x14, 0x00FF); 1214 + phy_write(phydev, 0x14, 0x00BB); 1215 + phy_write(phydev, 0x14, 0x0058); 1216 + phy_write(phydev, 0x14, 0x0029); 1217 + phy_write(phydev, 0x14, 0x0013); 1218 + phy_write(phydev, 0x14, 0x0009); 1219 + phy_write(phydev, 0x14, 0x0004); 1220 + phy_write(phydev, 0x14, 0x0002); 1221 + for (i = 0; i < 25; i++) 1222 + phy_write(phydev, 0x14, 0x0000); 1223 + phy_write(phydev, 0x1f, 0x0000); 1224 + 1225 + r8168g_phy_param(phydev, 0x8257, 0xffff, 0x020F); 1226 + r8168g_phy_param(phydev, 0x80ea, 0xffff, 0x7843); 1227 + 1228 + r8169_apply_firmware(tp); 1229 + 1230 + phy_modify_paged(phydev, 0xd06, 0x14, 0x0000, 0x2000); 1231 + 1232 + r8168g_phy_param(phydev, 0x81a2, 0x0000, 0x0100); 1233 + 1234 + phy_modify_paged(phydev, 0xb54, 0x16, 0xff00, 0xdb00); 1235 + phy_modify_paged(phydev, 0xa45, 0x12, 0x0001, 0x0000); 1236 + phy_modify_paged(phydev, 0xa5d, 0x12, 0x0000, 0x0020); 1237 + phy_modify_paged(phydev, 0xad4, 0x17, 0x0010, 0x0000); 1238 + phy_modify_paged(phydev, 0xa86, 0x15, 0x0001, 0x0000); 1239 + phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800); 1240 + 1241 + rtl8125_config_eee_phy(phydev); 1242 + } 1243 + 1244 + void r8169_hw_phy_config(struct rtl8169_private *tp, struct phy_device *phydev, 1245 + enum mac_version ver) 1246 + { 1247 + static const rtl_phy_cfg_fct phy_configs[] = { 1248 + /* PCI devices. */ 1249 + [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config, 1250 + [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config, 1251 + [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config, 1252 + [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config, 1253 + [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config, 1254 + /* PCI-E devices. */ 1255 + [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config, 1256 + [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config, 1257 + [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config, 1258 + [RTL_GIGA_MAC_VER_10] = NULL, 1259 + [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config, 1260 + [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config, 1261 + [RTL_GIGA_MAC_VER_13] = NULL, 1262 + [RTL_GIGA_MAC_VER_14] = NULL, 1263 + [RTL_GIGA_MAC_VER_15] = NULL, 1264 + [RTL_GIGA_MAC_VER_16] = NULL, 1265 + [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config, 1266 + [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config, 1267 + [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config, 1268 + [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config, 1269 + [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config, 1270 + [RTL_GIGA_MAC_VER_22] = rtl8168c_3_hw_phy_config, 1271 + [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config, 1272 + [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config, 1273 + [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config, 1274 + [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config, 1275 + [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config, 1276 + [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config, 1277 + [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config, 1278 + [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config, 1279 + [RTL_GIGA_MAC_VER_31] = NULL, 1280 + [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config, 1281 + [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config, 1282 + [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config, 1283 + [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config, 1284 + [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config, 1285 + [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config, 1286 + [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config, 1287 + [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config, 1288 + [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config, 1289 + [RTL_GIGA_MAC_VER_41] = NULL, 1290 + [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config, 1291 + [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config, 1292 + [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config, 1293 + [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config, 1294 + [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config, 1295 + [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config, 1296 + [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config, 1297 + [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config, 1298 + [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config, 1299 + [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config, 1300 + [RTL_GIGA_MAC_VER_52] = rtl8117_hw_phy_config, 1301 + [RTL_GIGA_MAC_VER_60] = rtl8125_1_hw_phy_config, 1302 + [RTL_GIGA_MAC_VER_61] = rtl8125_2_hw_phy_config, 1303 + }; 1304 + 1305 + if (phy_configs[ver]) 1306 + phy_configs[ver](tp, phydev); 1307 + }