tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/amd/include:cleanup vega10 sdma0/1 header files.

To remove include/asic_reg/vega10 folder,create IP folders sdma0/1.
This patch cleanup asic_reg/vega10/SDMA folders.

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Feifei Xu and committed by
Alex Deucher 812f77b7 ce1b1b66

+5323 -5323
+1 -1
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
··· 35 35 #include "vega10/MP/mp_9_0_offset.h" 36 36 #include "vega10/MP/mp_9_0_sh_mask.h" 37 37 #include "vega10/GC/gc_9_0_offset.h" 38 - #include "vega10/SDMA0/sdma0_4_0_offset.h" 38 + #include "sdma0/sdma0_4_0_offset.h" 39 39 #include "vega10/NBIO/nbio_6_1_offset.h" 40 40 41 41 MODULE_FIRMWARE("amdgpu/vega10_sos.bin");
+4 -4
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
··· 28 28 #include "amdgpu_trace.h" 29 29 30 30 #include "vega10/soc15ip.h" 31 - #include "vega10/SDMA0/sdma0_4_0_offset.h" 32 - #include "vega10/SDMA0/sdma0_4_0_sh_mask.h" 33 - #include "vega10/SDMA1/sdma1_4_0_offset.h" 34 - #include "vega10/SDMA1/sdma1_4_0_sh_mask.h" 31 + #include "sdma0/sdma0_4_0_offset.h" 32 + #include "sdma0/sdma0_4_0_sh_mask.h" 33 + #include "sdma1/sdma1_4_0_offset.h" 34 + #include "sdma1/sdma1_4_0_sh_mask.h" 35 35 #include "vega10/MMHUB/mmhub_1_0_offset.h" 36 36 #include "vega10/MMHUB/mmhub_1_0_sh_mask.h" 37 37 #include "vega10/HDP/hdp_4_0_offset.h"
+2 -2
drivers/gpu/drm/amd/amdgpu/soc15.c
··· 38 38 #include "vega10/UVD/uvd_7_0_offset.h" 39 39 #include "vega10/GC/gc_9_0_offset.h" 40 40 #include "vega10/GC/gc_9_0_sh_mask.h" 41 - #include "vega10/SDMA0/sdma0_4_0_offset.h" 42 - #include "vega10/SDMA1/sdma1_4_0_offset.h" 41 + #include "sdma0/sdma0_4_0_offset.h" 42 + #include "sdma1/sdma1_4_0_offset.h" 43 43 #include "vega10/HDP/hdp_4_0_offset.h" 44 44 #include "vega10/HDP/hdp_4_0_sh_mask.h" 45 45 #include "vega10/MP/mp_9_0_offset.h"
+286
drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_default.h
··· 1 + /* 2 + * Copyright (C) 2017 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included 12 + * in all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 + */ 21 + #ifndef _sdma0_4_0_DEFAULT_HEADER 22 + #define _sdma0_4_0_DEFAULT_HEADER 23 + 24 + 25 + // addressBlock: sdma0_sdma0dec 26 + #define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000 27 + #define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000 28 + #define mmSDMA0_VM_CNTL_DEFAULT 0x00000000 29 + #define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000 30 + #define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000 31 + #define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000 32 + #define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000 33 + #define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000 34 + #define mmSDMA0_VF_ENABLE_DEFAULT 0x00000000 35 + #define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f 36 + #define mmSDMA0_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff 37 + #define mmSDMA0_CONTEXT_REG_TYPE2_DEFAULT 0x000003ff 38 + #define mmSDMA0_CONTEXT_REG_TYPE3_DEFAULT 0x00000000 39 + #define mmSDMA0_PUB_REG_TYPE0_DEFAULT 0x3c000000 40 + #define mmSDMA0_PUB_REG_TYPE1_DEFAULT 0x30003882 41 + #define mmSDMA0_PUB_REG_TYPE2_DEFAULT 0x0fc6e880 42 + #define mmSDMA0_PUB_REG_TYPE3_DEFAULT 0x00000000 43 + #define mmSDMA0_MMHUB_CNTL_DEFAULT 0x00000000 44 + #define mmSDMA0_CONTEXT_GROUP_BOUNDARY_DEFAULT 0x00000000 45 + #define mmSDMA0_POWER_CNTL_DEFAULT 0x0003c000 46 + #define mmSDMA0_CLK_CTRL_DEFAULT 0xff000100 47 + #define mmSDMA0_CNTL_DEFAULT 0x00000002 48 + #define mmSDMA0_CHICKEN_BITS_DEFAULT 0x00831f07 49 + #define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00100012 50 + #define mmSDMA0_GB_ADDR_CONFIG_READ_DEFAULT 0x00100012 51 + #define mmSDMA0_RB_RPTR_FETCH_HI_DEFAULT 0x00000000 52 + #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT 0x00000000 53 + #define mmSDMA0_RB_RPTR_FETCH_DEFAULT 0x00000000 54 + #define mmSDMA0_IB_OFFSET_FETCH_DEFAULT 0x00000000 55 + #define mmSDMA0_PROGRAM_DEFAULT 0x00000000 56 + #define mmSDMA0_STATUS_REG_DEFAULT 0x46dee557 57 + #define mmSDMA0_STATUS1_REG_DEFAULT 0x000003ff 58 + #define mmSDMA0_RD_BURST_CNTL_DEFAULT 0x00000003 59 + #define mmSDMA0_HBM_PAGE_CONFIG_DEFAULT 0x00000000 60 + #define mmSDMA0_UCODE_CHECKSUM_DEFAULT 0x00000000 61 + #define mmSDMA0_F32_CNTL_DEFAULT 0x00000001 62 + #define mmSDMA0_FREEZE_DEFAULT 0x00000000 63 + #define mmSDMA0_PHASE0_QUANTUM_DEFAULT 0x00010002 64 + #define mmSDMA0_PHASE1_QUANTUM_DEFAULT 0x00010002 65 + #define mmSDMA_POWER_GATING_DEFAULT 0x00000000 66 + #define mmSDMA_PGFSM_CONFIG_DEFAULT 0x00000000 67 + #define mmSDMA_PGFSM_WRITE_DEFAULT 0x00000000 68 + #define mmSDMA_PGFSM_READ_DEFAULT 0x00000000 69 + #define mmSDMA0_EDC_CONFIG_DEFAULT 0x00000002 70 + #define mmSDMA0_BA_THRESHOLD_DEFAULT 0x03ff03ff 71 + #define mmSDMA0_ID_DEFAULT 0x00000001 72 + #define mmSDMA0_VERSION_DEFAULT 0x00000400 73 + #define mmSDMA0_EDC_COUNTER_DEFAULT 0x00000000 74 + #define mmSDMA0_EDC_COUNTER_CLEAR_DEFAULT 0x00000000 75 + #define mmSDMA0_STATUS2_REG_DEFAULT 0x00000000 76 + #define mmSDMA0_ATOMIC_CNTL_DEFAULT 0x00000200 77 + #define mmSDMA0_ATOMIC_PREOP_LO_DEFAULT 0x00000000 78 + #define mmSDMA0_ATOMIC_PREOP_HI_DEFAULT 0x00000000 79 + #define mmSDMA0_UTCL1_CNTL_DEFAULT 0xd0003019 80 + #define mmSDMA0_UTCL1_WATERMK_DEFAULT 0xfffbe1fe 81 + #define mmSDMA0_UTCL1_RD_STATUS_DEFAULT 0x201001ff 82 + #define mmSDMA0_UTCL1_WR_STATUS_DEFAULT 0x503001ff 83 + #define mmSDMA0_UTCL1_INV0_DEFAULT 0x00000600 84 + #define mmSDMA0_UTCL1_INV1_DEFAULT 0x00000000 85 + #define mmSDMA0_UTCL1_INV2_DEFAULT 0x00000000 86 + #define mmSDMA0_UTCL1_RD_XNACK0_DEFAULT 0x00000000 87 + #define mmSDMA0_UTCL1_RD_XNACK1_DEFAULT 0x00000000 88 + #define mmSDMA0_UTCL1_WR_XNACK0_DEFAULT 0x00000000 89 + #define mmSDMA0_UTCL1_WR_XNACK1_DEFAULT 0x00000000 90 + #define mmSDMA0_UTCL1_TIMEOUT_DEFAULT 0x00010001 91 + #define mmSDMA0_UTCL1_PAGE_DEFAULT 0x000003e0 92 + #define mmSDMA0_POWER_CNTL_IDLE_DEFAULT 0x06060200 93 + #define mmSDMA0_RELAX_ORDERING_LUT_DEFAULT 0xc0000006 94 + #define mmSDMA0_CHICKEN_BITS_2_DEFAULT 0x00000005 95 + #define mmSDMA0_STATUS3_REG_DEFAULT 0x00100000 96 + #define mmSDMA0_PHYSICAL_ADDR_LO_DEFAULT 0x00000000 97 + #define mmSDMA0_PHYSICAL_ADDR_HI_DEFAULT 0x00000000 98 + #define mmSDMA0_PHASE2_QUANTUM_DEFAULT 0x00010002 99 + #define mmSDMA0_ERROR_LOG_DEFAULT 0x0000000f 100 + #define mmSDMA0_PUB_DUMMY_REG0_DEFAULT 0x00000000 101 + #define mmSDMA0_PUB_DUMMY_REG1_DEFAULT 0x00000000 102 + #define mmSDMA0_PUB_DUMMY_REG2_DEFAULT 0x00000000 103 + #define mmSDMA0_PUB_DUMMY_REG3_DEFAULT 0x00000000 104 + #define mmSDMA0_F32_COUNTER_DEFAULT 0x00000000 105 + #define mmSDMA0_UNBREAKABLE_DEFAULT 0x00000000 106 + #define mmSDMA0_PERFMON_CNTL_DEFAULT 0x000ff7fd 107 + #define mmSDMA0_PERFCOUNTER0_RESULT_DEFAULT 0x00000000 108 + #define mmSDMA0_PERFCOUNTER1_RESULT_DEFAULT 0x00000000 109 + #define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_DEFAULT 0x00640000 110 + #define mmSDMA0_CRD_CNTL_DEFAULT 0x000085c0 111 + #define mmSDMA0_MMHUB_TRUSTLVL_DEFAULT 0x00000000 112 + #define mmSDMA0_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000 113 + #define mmSDMA0_ULV_CNTL_DEFAULT 0x00000000 114 + #define mmSDMA0_EA_DBIT_ADDR_DATA_DEFAULT 0x00000000 115 + #define mmSDMA0_EA_DBIT_ADDR_INDEX_DEFAULT 0x00000000 116 + #define mmSDMA0_GFX_RB_CNTL_DEFAULT 0x00040000 117 + #define mmSDMA0_GFX_RB_BASE_DEFAULT 0x00000000 118 + #define mmSDMA0_GFX_RB_BASE_HI_DEFAULT 0x00000000 119 + #define mmSDMA0_GFX_RB_RPTR_DEFAULT 0x00000000 120 + #define mmSDMA0_GFX_RB_RPTR_HI_DEFAULT 0x00000000 121 + #define mmSDMA0_GFX_RB_WPTR_DEFAULT 0x00000000 122 + #define mmSDMA0_GFX_RB_WPTR_HI_DEFAULT 0x00000000 123 + #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 124 + #define mmSDMA0_GFX_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 125 + #define mmSDMA0_GFX_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 126 + #define mmSDMA0_GFX_IB_CNTL_DEFAULT 0x00000100 127 + #define mmSDMA0_GFX_IB_RPTR_DEFAULT 0x00000000 128 + #define mmSDMA0_GFX_IB_OFFSET_DEFAULT 0x00000000 129 + #define mmSDMA0_GFX_IB_BASE_LO_DEFAULT 0x00000000 130 + #define mmSDMA0_GFX_IB_BASE_HI_DEFAULT 0x00000000 131 + #define mmSDMA0_GFX_IB_SIZE_DEFAULT 0x00000000 132 + #define mmSDMA0_GFX_SKIP_CNTL_DEFAULT 0x00000000 133 + #define mmSDMA0_GFX_CONTEXT_STATUS_DEFAULT 0x00000005 134 + #define mmSDMA0_GFX_DOORBELL_DEFAULT 0x00000000 135 + #define mmSDMA0_GFX_CONTEXT_CNTL_DEFAULT 0x00000000 136 + #define mmSDMA0_GFX_STATUS_DEFAULT 0x00000000 137 + #define mmSDMA0_GFX_DOORBELL_LOG_DEFAULT 0x00000000 138 + #define mmSDMA0_GFX_WATERMARK_DEFAULT 0x00000000 139 + #define mmSDMA0_GFX_DOORBELL_OFFSET_DEFAULT 0x00000000 140 + #define mmSDMA0_GFX_CSA_ADDR_LO_DEFAULT 0x00000000 141 + #define mmSDMA0_GFX_CSA_ADDR_HI_DEFAULT 0x00000000 142 + #define mmSDMA0_GFX_IB_SUB_REMAIN_DEFAULT 0x00000000 143 + #define mmSDMA0_GFX_PREEMPT_DEFAULT 0x00000000 144 + #define mmSDMA0_GFX_DUMMY_REG_DEFAULT 0x0000000f 145 + #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 146 + #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 147 + #define mmSDMA0_GFX_RB_AQL_CNTL_DEFAULT 0x00004000 148 + #define mmSDMA0_GFX_MINOR_PTR_UPDATE_DEFAULT 0x00000000 149 + #define mmSDMA0_GFX_MIDCMD_DATA0_DEFAULT 0x00000000 150 + #define mmSDMA0_GFX_MIDCMD_DATA1_DEFAULT 0x00000000 151 + #define mmSDMA0_GFX_MIDCMD_DATA2_DEFAULT 0x00000000 152 + #define mmSDMA0_GFX_MIDCMD_DATA3_DEFAULT 0x00000000 153 + #define mmSDMA0_GFX_MIDCMD_DATA4_DEFAULT 0x00000000 154 + #define mmSDMA0_GFX_MIDCMD_DATA5_DEFAULT 0x00000000 155 + #define mmSDMA0_GFX_MIDCMD_DATA6_DEFAULT 0x00000000 156 + #define mmSDMA0_GFX_MIDCMD_DATA7_DEFAULT 0x00000000 157 + #define mmSDMA0_GFX_MIDCMD_DATA8_DEFAULT 0x00000000 158 + #define mmSDMA0_GFX_MIDCMD_CNTL_DEFAULT 0x00000000 159 + #define mmSDMA0_PAGE_RB_CNTL_DEFAULT 0x00040000 160 + #define mmSDMA0_PAGE_RB_BASE_DEFAULT 0x00000000 161 + #define mmSDMA0_PAGE_RB_BASE_HI_DEFAULT 0x00000000 162 + #define mmSDMA0_PAGE_RB_RPTR_DEFAULT 0x00000000 163 + #define mmSDMA0_PAGE_RB_RPTR_HI_DEFAULT 0x00000000 164 + #define mmSDMA0_PAGE_RB_WPTR_DEFAULT 0x00000000 165 + #define mmSDMA0_PAGE_RB_WPTR_HI_DEFAULT 0x00000000 166 + #define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 167 + #define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 168 + #define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 169 + #define mmSDMA0_PAGE_IB_CNTL_DEFAULT 0x00000100 170 + #define mmSDMA0_PAGE_IB_RPTR_DEFAULT 0x00000000 171 + #define mmSDMA0_PAGE_IB_OFFSET_DEFAULT 0x00000000 172 + #define mmSDMA0_PAGE_IB_BASE_LO_DEFAULT 0x00000000 173 + #define mmSDMA0_PAGE_IB_BASE_HI_DEFAULT 0x00000000 174 + #define mmSDMA0_PAGE_IB_SIZE_DEFAULT 0x00000000 175 + #define mmSDMA0_PAGE_SKIP_CNTL_DEFAULT 0x00000000 176 + #define mmSDMA0_PAGE_CONTEXT_STATUS_DEFAULT 0x00000004 177 + #define mmSDMA0_PAGE_DOORBELL_DEFAULT 0x00000000 178 + #define mmSDMA0_PAGE_STATUS_DEFAULT 0x00000000 179 + #define mmSDMA0_PAGE_DOORBELL_LOG_DEFAULT 0x00000000 180 + #define mmSDMA0_PAGE_WATERMARK_DEFAULT 0x00000000 181 + #define mmSDMA0_PAGE_DOORBELL_OFFSET_DEFAULT 0x00000000 182 + #define mmSDMA0_PAGE_CSA_ADDR_LO_DEFAULT 0x00000000 183 + #define mmSDMA0_PAGE_CSA_ADDR_HI_DEFAULT 0x00000000 184 + #define mmSDMA0_PAGE_IB_SUB_REMAIN_DEFAULT 0x00000000 185 + #define mmSDMA0_PAGE_PREEMPT_DEFAULT 0x00000000 186 + #define mmSDMA0_PAGE_DUMMY_REG_DEFAULT 0x0000000f 187 + #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 188 + #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 189 + #define mmSDMA0_PAGE_RB_AQL_CNTL_DEFAULT 0x00004000 190 + #define mmSDMA0_PAGE_MINOR_PTR_UPDATE_DEFAULT 0x00000000 191 + #define mmSDMA0_PAGE_MIDCMD_DATA0_DEFAULT 0x00000000 192 + #define mmSDMA0_PAGE_MIDCMD_DATA1_DEFAULT 0x00000000 193 + #define mmSDMA0_PAGE_MIDCMD_DATA2_DEFAULT 0x00000000 194 + #define mmSDMA0_PAGE_MIDCMD_DATA3_DEFAULT 0x00000000 195 + #define mmSDMA0_PAGE_MIDCMD_DATA4_DEFAULT 0x00000000 196 + #define mmSDMA0_PAGE_MIDCMD_DATA5_DEFAULT 0x00000000 197 + #define mmSDMA0_PAGE_MIDCMD_DATA6_DEFAULT 0x00000000 198 + #define mmSDMA0_PAGE_MIDCMD_DATA7_DEFAULT 0x00000000 199 + #define mmSDMA0_PAGE_MIDCMD_DATA8_DEFAULT 0x00000000 200 + #define mmSDMA0_PAGE_MIDCMD_CNTL_DEFAULT 0x00000000 201 + #define mmSDMA0_RLC0_RB_CNTL_DEFAULT 0x00040000 202 + #define mmSDMA0_RLC0_RB_BASE_DEFAULT 0x00000000 203 + #define mmSDMA0_RLC0_RB_BASE_HI_DEFAULT 0x00000000 204 + #define mmSDMA0_RLC0_RB_RPTR_DEFAULT 0x00000000 205 + #define mmSDMA0_RLC0_RB_RPTR_HI_DEFAULT 0x00000000 206 + #define mmSDMA0_RLC0_RB_WPTR_DEFAULT 0x00000000 207 + #define mmSDMA0_RLC0_RB_WPTR_HI_DEFAULT 0x00000000 208 + #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 209 + #define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 210 + #define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 211 + #define mmSDMA0_RLC0_IB_CNTL_DEFAULT 0x00000100 212 + #define mmSDMA0_RLC0_IB_RPTR_DEFAULT 0x00000000 213 + #define mmSDMA0_RLC0_IB_OFFSET_DEFAULT 0x00000000 214 + #define mmSDMA0_RLC0_IB_BASE_LO_DEFAULT 0x00000000 215 + #define mmSDMA0_RLC0_IB_BASE_HI_DEFAULT 0x00000000 216 + #define mmSDMA0_RLC0_IB_SIZE_DEFAULT 0x00000000 217 + #define mmSDMA0_RLC0_SKIP_CNTL_DEFAULT 0x00000000 218 + #define mmSDMA0_RLC0_CONTEXT_STATUS_DEFAULT 0x00000004 219 + #define mmSDMA0_RLC0_DOORBELL_DEFAULT 0x00000000 220 + #define mmSDMA0_RLC0_STATUS_DEFAULT 0x00000000 221 + #define mmSDMA0_RLC0_DOORBELL_LOG_DEFAULT 0x00000000 222 + #define mmSDMA0_RLC0_WATERMARK_DEFAULT 0x00000000 223 + #define mmSDMA0_RLC0_DOORBELL_OFFSET_DEFAULT 0x00000000 224 + #define mmSDMA0_RLC0_CSA_ADDR_LO_DEFAULT 0x00000000 225 + #define mmSDMA0_RLC0_CSA_ADDR_HI_DEFAULT 0x00000000 226 + #define mmSDMA0_RLC0_IB_SUB_REMAIN_DEFAULT 0x00000000 227 + #define mmSDMA0_RLC0_PREEMPT_DEFAULT 0x00000000 228 + #define mmSDMA0_RLC0_DUMMY_REG_DEFAULT 0x0000000f 229 + #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 230 + #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 231 + #define mmSDMA0_RLC0_RB_AQL_CNTL_DEFAULT 0x00004000 232 + #define mmSDMA0_RLC0_MINOR_PTR_UPDATE_DEFAULT 0x00000000 233 + #define mmSDMA0_RLC0_MIDCMD_DATA0_DEFAULT 0x00000000 234 + #define mmSDMA0_RLC0_MIDCMD_DATA1_DEFAULT 0x00000000 235 + #define mmSDMA0_RLC0_MIDCMD_DATA2_DEFAULT 0x00000000 236 + #define mmSDMA0_RLC0_MIDCMD_DATA3_DEFAULT 0x00000000 237 + #define mmSDMA0_RLC0_MIDCMD_DATA4_DEFAULT 0x00000000 238 + #define mmSDMA0_RLC0_MIDCMD_DATA5_DEFAULT 0x00000000 239 + #define mmSDMA0_RLC0_MIDCMD_DATA6_DEFAULT 0x00000000 240 + #define mmSDMA0_RLC0_MIDCMD_DATA7_DEFAULT 0x00000000 241 + #define mmSDMA0_RLC0_MIDCMD_DATA8_DEFAULT 0x00000000 242 + #define mmSDMA0_RLC0_MIDCMD_CNTL_DEFAULT 0x00000000 243 + #define mmSDMA0_RLC1_RB_CNTL_DEFAULT 0x00040000 244 + #define mmSDMA0_RLC1_RB_BASE_DEFAULT 0x00000000 245 + #define mmSDMA0_RLC1_RB_BASE_HI_DEFAULT 0x00000000 246 + #define mmSDMA0_RLC1_RB_RPTR_DEFAULT 0x00000000 247 + #define mmSDMA0_RLC1_RB_RPTR_HI_DEFAULT 0x00000000 248 + #define mmSDMA0_RLC1_RB_WPTR_DEFAULT 0x00000000 249 + #define mmSDMA0_RLC1_RB_WPTR_HI_DEFAULT 0x00000000 250 + #define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 251 + #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 252 + #define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 253 + #define mmSDMA0_RLC1_IB_CNTL_DEFAULT 0x00000100 254 + #define mmSDMA0_RLC1_IB_RPTR_DEFAULT 0x00000000 255 + #define mmSDMA0_RLC1_IB_OFFSET_DEFAULT 0x00000000 256 + #define mmSDMA0_RLC1_IB_BASE_LO_DEFAULT 0x00000000 257 + #define mmSDMA0_RLC1_IB_BASE_HI_DEFAULT 0x00000000 258 + #define mmSDMA0_RLC1_IB_SIZE_DEFAULT 0x00000000 259 + #define mmSDMA0_RLC1_SKIP_CNTL_DEFAULT 0x00000000 260 + #define mmSDMA0_RLC1_CONTEXT_STATUS_DEFAULT 0x00000004 261 + #define mmSDMA0_RLC1_DOORBELL_DEFAULT 0x00000000 262 + #define mmSDMA0_RLC1_STATUS_DEFAULT 0x00000000 263 + #define mmSDMA0_RLC1_DOORBELL_LOG_DEFAULT 0x00000000 264 + #define mmSDMA0_RLC1_WATERMARK_DEFAULT 0x00000000 265 + #define mmSDMA0_RLC1_DOORBELL_OFFSET_DEFAULT 0x00000000 266 + #define mmSDMA0_RLC1_CSA_ADDR_LO_DEFAULT 0x00000000 267 + #define mmSDMA0_RLC1_CSA_ADDR_HI_DEFAULT 0x00000000 268 + #define mmSDMA0_RLC1_IB_SUB_REMAIN_DEFAULT 0x00000000 269 + #define mmSDMA0_RLC1_PREEMPT_DEFAULT 0x00000000 270 + #define mmSDMA0_RLC1_DUMMY_REG_DEFAULT 0x0000000f 271 + #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 272 + #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 273 + #define mmSDMA0_RLC1_RB_AQL_CNTL_DEFAULT 0x00004000 274 + #define mmSDMA0_RLC1_MINOR_PTR_UPDATE_DEFAULT 0x00000000 275 + #define mmSDMA0_RLC1_MIDCMD_DATA0_DEFAULT 0x00000000 276 + #define mmSDMA0_RLC1_MIDCMD_DATA1_DEFAULT 0x00000000 277 + #define mmSDMA0_RLC1_MIDCMD_DATA2_DEFAULT 0x00000000 278 + #define mmSDMA0_RLC1_MIDCMD_DATA3_DEFAULT 0x00000000 279 + #define mmSDMA0_RLC1_MIDCMD_DATA4_DEFAULT 0x00000000 280 + #define mmSDMA0_RLC1_MIDCMD_DATA5_DEFAULT 0x00000000 281 + #define mmSDMA0_RLC1_MIDCMD_DATA6_DEFAULT 0x00000000 282 + #define mmSDMA0_RLC1_MIDCMD_DATA7_DEFAULT 0x00000000 283 + #define mmSDMA0_RLC1_MIDCMD_DATA8_DEFAULT 0x00000000 284 + #define mmSDMA0_RLC1_MIDCMD_CNTL_DEFAULT 0x00000000 285 + 286 + #endif
+547
drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h
··· 1 + /* 2 + * Copyright (C) 2017 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included 12 + * in all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 + */ 21 + #ifndef _sdma0_4_0_OFFSET_HEADER 22 + #define _sdma0_4_0_OFFSET_HEADER 23 + 24 + 25 + 26 + // addressBlock: sdma0_sdma0dec 27 + // base address: 0x4980 28 + #define mmSDMA0_UCODE_ADDR 0x0000 29 + #define mmSDMA0_UCODE_ADDR_BASE_IDX 0 30 + #define mmSDMA0_UCODE_DATA 0x0001 31 + #define mmSDMA0_UCODE_DATA_BASE_IDX 0 32 + #define mmSDMA0_VM_CNTL 0x0004 33 + #define mmSDMA0_VM_CNTL_BASE_IDX 0 34 + #define mmSDMA0_VM_CTX_LO 0x0005 35 + #define mmSDMA0_VM_CTX_LO_BASE_IDX 0 36 + #define mmSDMA0_VM_CTX_HI 0x0006 37 + #define mmSDMA0_VM_CTX_HI_BASE_IDX 0 38 + #define mmSDMA0_ACTIVE_FCN_ID 0x0007 39 + #define mmSDMA0_ACTIVE_FCN_ID_BASE_IDX 0 40 + #define mmSDMA0_VM_CTX_CNTL 0x0008 41 + #define mmSDMA0_VM_CTX_CNTL_BASE_IDX 0 42 + #define mmSDMA0_VIRT_RESET_REQ 0x0009 43 + #define mmSDMA0_VIRT_RESET_REQ_BASE_IDX 0 44 + #define mmSDMA0_VF_ENABLE 0x000a 45 + #define mmSDMA0_VF_ENABLE_BASE_IDX 0 46 + #define mmSDMA0_CONTEXT_REG_TYPE0 0x000b 47 + #define mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX 0 48 + #define mmSDMA0_CONTEXT_REG_TYPE1 0x000c 49 + #define mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX 0 50 + #define mmSDMA0_CONTEXT_REG_TYPE2 0x000d 51 + #define mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX 0 52 + #define mmSDMA0_CONTEXT_REG_TYPE3 0x000e 53 + #define mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX 0 54 + #define mmSDMA0_PUB_REG_TYPE0 0x000f 55 + #define mmSDMA0_PUB_REG_TYPE0_BASE_IDX 0 56 + #define mmSDMA0_PUB_REG_TYPE1 0x0010 57 + #define mmSDMA0_PUB_REG_TYPE1_BASE_IDX 0 58 + #define mmSDMA0_PUB_REG_TYPE2 0x0011 59 + #define mmSDMA0_PUB_REG_TYPE2_BASE_IDX 0 60 + #define mmSDMA0_PUB_REG_TYPE3 0x0012 61 + #define mmSDMA0_PUB_REG_TYPE3_BASE_IDX 0 62 + #define mmSDMA0_MMHUB_CNTL 0x0013 63 + #define mmSDMA0_MMHUB_CNTL_BASE_IDX 0 64 + #define mmSDMA0_CONTEXT_GROUP_BOUNDARY 0x0019 65 + #define mmSDMA0_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 66 + #define mmSDMA0_POWER_CNTL 0x001a 67 + #define mmSDMA0_POWER_CNTL_BASE_IDX 0 68 + #define mmSDMA0_CLK_CTRL 0x001b 69 + #define mmSDMA0_CLK_CTRL_BASE_IDX 0 70 + #define mmSDMA0_CNTL 0x001c 71 + #define mmSDMA0_CNTL_BASE_IDX 0 72 + #define mmSDMA0_CHICKEN_BITS 0x001d 73 + #define mmSDMA0_CHICKEN_BITS_BASE_IDX 0 74 + #define mmSDMA0_GB_ADDR_CONFIG 0x001e 75 + #define mmSDMA0_GB_ADDR_CONFIG_BASE_IDX 0 76 + #define mmSDMA0_GB_ADDR_CONFIG_READ 0x001f 77 + #define mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX 0 78 + #define mmSDMA0_RB_RPTR_FETCH_HI 0x0020 79 + #define mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX 0 80 + #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 81 + #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 82 + #define mmSDMA0_RB_RPTR_FETCH 0x0022 83 + #define mmSDMA0_RB_RPTR_FETCH_BASE_IDX 0 84 + #define mmSDMA0_IB_OFFSET_FETCH 0x0023 85 + #define mmSDMA0_IB_OFFSET_FETCH_BASE_IDX 0 86 + #define mmSDMA0_PROGRAM 0x0024 87 + #define mmSDMA0_PROGRAM_BASE_IDX 0 88 + #define mmSDMA0_STATUS_REG 0x0025 89 + #define mmSDMA0_STATUS_REG_BASE_IDX 0 90 + #define mmSDMA0_STATUS1_REG 0x0026 91 + #define mmSDMA0_STATUS1_REG_BASE_IDX 0 92 + #define mmSDMA0_RD_BURST_CNTL 0x0027 93 + #define mmSDMA0_RD_BURST_CNTL_BASE_IDX 0 94 + #define mmSDMA0_HBM_PAGE_CONFIG 0x0028 95 + #define mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX 0 96 + #define mmSDMA0_UCODE_CHECKSUM 0x0029 97 + #define mmSDMA0_UCODE_CHECKSUM_BASE_IDX 0 98 + #define mmSDMA0_F32_CNTL 0x002a 99 + #define mmSDMA0_F32_CNTL_BASE_IDX 0 100 + #define mmSDMA0_FREEZE 0x002b 101 + #define mmSDMA0_FREEZE_BASE_IDX 0 102 + #define mmSDMA0_PHASE0_QUANTUM 0x002c 103 + #define mmSDMA0_PHASE0_QUANTUM_BASE_IDX 0 104 + #define mmSDMA0_PHASE1_QUANTUM 0x002d 105 + #define mmSDMA0_PHASE1_QUANTUM_BASE_IDX 0 106 + #define mmSDMA_POWER_GATING 0x002e 107 + #define mmSDMA_POWER_GATING_BASE_IDX 0 108 + #define mmSDMA_PGFSM_CONFIG 0x002f 109 + #define mmSDMA_PGFSM_CONFIG_BASE_IDX 0 110 + #define mmSDMA_PGFSM_WRITE 0x0030 111 + #define mmSDMA_PGFSM_WRITE_BASE_IDX 0 112 + #define mmSDMA_PGFSM_READ 0x0031 113 + #define mmSDMA_PGFSM_READ_BASE_IDX 0 114 + #define mmSDMA0_EDC_CONFIG 0x0032 115 + #define mmSDMA0_EDC_CONFIG_BASE_IDX 0 116 + #define mmSDMA0_BA_THRESHOLD 0x0033 117 + #define mmSDMA0_BA_THRESHOLD_BASE_IDX 0 118 + #define mmSDMA0_ID 0x0034 119 + #define mmSDMA0_ID_BASE_IDX 0 120 + #define mmSDMA0_VERSION 0x0035 121 + #define mmSDMA0_VERSION_BASE_IDX 0 122 + #define mmSDMA0_EDC_COUNTER 0x0036 123 + #define mmSDMA0_EDC_COUNTER_BASE_IDX 0 124 + #define mmSDMA0_EDC_COUNTER_CLEAR 0x0037 125 + #define mmSDMA0_EDC_COUNTER_CLEAR_BASE_IDX 0 126 + #define mmSDMA0_STATUS2_REG 0x0038 127 + #define mmSDMA0_STATUS2_REG_BASE_IDX 0 128 + #define mmSDMA0_ATOMIC_CNTL 0x0039 129 + #define mmSDMA0_ATOMIC_CNTL_BASE_IDX 0 130 + #define mmSDMA0_ATOMIC_PREOP_LO 0x003a 131 + #define mmSDMA0_ATOMIC_PREOP_LO_BASE_IDX 0 132 + #define mmSDMA0_ATOMIC_PREOP_HI 0x003b 133 + #define mmSDMA0_ATOMIC_PREOP_HI_BASE_IDX 0 134 + #define mmSDMA0_UTCL1_CNTL 0x003c 135 + #define mmSDMA0_UTCL1_CNTL_BASE_IDX 0 136 + #define mmSDMA0_UTCL1_WATERMK 0x003d 137 + #define mmSDMA0_UTCL1_WATERMK_BASE_IDX 0 138 + #define mmSDMA0_UTCL1_RD_STATUS 0x003e 139 + #define mmSDMA0_UTCL1_RD_STATUS_BASE_IDX 0 140 + #define mmSDMA0_UTCL1_WR_STATUS 0x003f 141 + #define mmSDMA0_UTCL1_WR_STATUS_BASE_IDX 0 142 + #define mmSDMA0_UTCL1_INV0 0x0040 143 + #define mmSDMA0_UTCL1_INV0_BASE_IDX 0 144 + #define mmSDMA0_UTCL1_INV1 0x0041 145 + #define mmSDMA0_UTCL1_INV1_BASE_IDX 0 146 + #define mmSDMA0_UTCL1_INV2 0x0042 147 + #define mmSDMA0_UTCL1_INV2_BASE_IDX 0 148 + #define mmSDMA0_UTCL1_RD_XNACK0 0x0043 149 + #define mmSDMA0_UTCL1_RD_XNACK0_BASE_IDX 0 150 + #define mmSDMA0_UTCL1_RD_XNACK1 0x0044 151 + #define mmSDMA0_UTCL1_RD_XNACK1_BASE_IDX 0 152 + #define mmSDMA0_UTCL1_WR_XNACK0 0x0045 153 + #define mmSDMA0_UTCL1_WR_XNACK0_BASE_IDX 0 154 + #define mmSDMA0_UTCL1_WR_XNACK1 0x0046 155 + #define mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX 0 156 + #define mmSDMA0_UTCL1_TIMEOUT 0x0047 157 + #define mmSDMA0_UTCL1_TIMEOUT_BASE_IDX 0 158 + #define mmSDMA0_UTCL1_PAGE 0x0048 159 + #define mmSDMA0_UTCL1_PAGE_BASE_IDX 0 160 + #define mmSDMA0_POWER_CNTL_IDLE 0x0049 161 + #define mmSDMA0_POWER_CNTL_IDLE_BASE_IDX 0 162 + #define mmSDMA0_RELAX_ORDERING_LUT 0x004a 163 + #define mmSDMA0_RELAX_ORDERING_LUT_BASE_IDX 0 164 + #define mmSDMA0_CHICKEN_BITS_2 0x004b 165 + #define mmSDMA0_CHICKEN_BITS_2_BASE_IDX 0 166 + #define mmSDMA0_STATUS3_REG 0x004c 167 + #define mmSDMA0_STATUS3_REG_BASE_IDX 0 168 + #define mmSDMA0_PHYSICAL_ADDR_LO 0x004d 169 + #define mmSDMA0_PHYSICAL_ADDR_LO_BASE_IDX 0 170 + #define mmSDMA0_PHYSICAL_ADDR_HI 0x004e 171 + #define mmSDMA0_PHYSICAL_ADDR_HI_BASE_IDX 0 172 + #define mmSDMA0_PHASE2_QUANTUM 0x004f 173 + #define mmSDMA0_PHASE2_QUANTUM_BASE_IDX 0 174 + #define mmSDMA0_ERROR_LOG 0x0050 175 + #define mmSDMA0_ERROR_LOG_BASE_IDX 0 176 + #define mmSDMA0_PUB_DUMMY_REG0 0x0051 177 + #define mmSDMA0_PUB_DUMMY_REG0_BASE_IDX 0 178 + #define mmSDMA0_PUB_DUMMY_REG1 0x0052 179 + #define mmSDMA0_PUB_DUMMY_REG1_BASE_IDX 0 180 + #define mmSDMA0_PUB_DUMMY_REG2 0x0053 181 + #define mmSDMA0_PUB_DUMMY_REG2_BASE_IDX 0 182 + #define mmSDMA0_PUB_DUMMY_REG3 0x0054 183 + #define mmSDMA0_PUB_DUMMY_REG3_BASE_IDX 0 184 + #define mmSDMA0_F32_COUNTER 0x0055 185 + #define mmSDMA0_F32_COUNTER_BASE_IDX 0 186 + #define mmSDMA0_UNBREAKABLE 0x0056 187 + #define mmSDMA0_UNBREAKABLE_BASE_IDX 0 188 + #define mmSDMA0_PERFMON_CNTL 0x0057 189 + #define mmSDMA0_PERFMON_CNTL_BASE_IDX 0 190 + #define mmSDMA0_PERFCOUNTER0_RESULT 0x0058 191 + #define mmSDMA0_PERFCOUNTER0_RESULT_BASE_IDX 0 192 + #define mmSDMA0_PERFCOUNTER1_RESULT 0x0059 193 + #define mmSDMA0_PERFCOUNTER1_RESULT_BASE_IDX 0 194 + #define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE 0x005a 195 + #define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0 196 + #define mmSDMA0_CRD_CNTL 0x005b 197 + #define mmSDMA0_CRD_CNTL_BASE_IDX 0 198 + #define mmSDMA0_MMHUB_TRUSTLVL 0x005c 199 + #define mmSDMA0_MMHUB_TRUSTLVL_BASE_IDX 0 200 + #define mmSDMA0_GPU_IOV_VIOLATION_LOG 0x005d 201 + #define mmSDMA0_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 202 + #define mmSDMA0_ULV_CNTL 0x005e 203 + #define mmSDMA0_ULV_CNTL_BASE_IDX 0 204 + #define mmSDMA0_EA_DBIT_ADDR_DATA 0x0060 205 + #define mmSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX 0 206 + #define mmSDMA0_EA_DBIT_ADDR_INDEX 0x0061 207 + #define mmSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX 0 208 + #define mmSDMA0_GFX_RB_CNTL 0x0080 209 + #define mmSDMA0_GFX_RB_CNTL_BASE_IDX 0 210 + #define mmSDMA0_GFX_RB_BASE 0x0081 211 + #define mmSDMA0_GFX_RB_BASE_BASE_IDX 0 212 + #define mmSDMA0_GFX_RB_BASE_HI 0x0082 213 + #define mmSDMA0_GFX_RB_BASE_HI_BASE_IDX 0 214 + #define mmSDMA0_GFX_RB_RPTR 0x0083 215 + #define mmSDMA0_GFX_RB_RPTR_BASE_IDX 0 216 + #define mmSDMA0_GFX_RB_RPTR_HI 0x0084 217 + #define mmSDMA0_GFX_RB_RPTR_HI_BASE_IDX 0 218 + #define mmSDMA0_GFX_RB_WPTR 0x0085 219 + #define mmSDMA0_GFX_RB_WPTR_BASE_IDX 0 220 + #define mmSDMA0_GFX_RB_WPTR_HI 0x0086 221 + #define mmSDMA0_GFX_RB_WPTR_HI_BASE_IDX 0 222 + #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x0087 223 + #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 224 + #define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x0088 225 + #define mmSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 226 + #define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x0089 227 + #define mmSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 228 + #define mmSDMA0_GFX_IB_CNTL 0x008a 229 + #define mmSDMA0_GFX_IB_CNTL_BASE_IDX 0 230 + #define mmSDMA0_GFX_IB_RPTR 0x008b 231 + #define mmSDMA0_GFX_IB_RPTR_BASE_IDX 0 232 + #define mmSDMA0_GFX_IB_OFFSET 0x008c 233 + #define mmSDMA0_GFX_IB_OFFSET_BASE_IDX 0 234 + #define mmSDMA0_GFX_IB_BASE_LO 0x008d 235 + #define mmSDMA0_GFX_IB_BASE_LO_BASE_IDX 0 236 + #define mmSDMA0_GFX_IB_BASE_HI 0x008e 237 + #define mmSDMA0_GFX_IB_BASE_HI_BASE_IDX 0 238 + #define mmSDMA0_GFX_IB_SIZE 0x008f 239 + #define mmSDMA0_GFX_IB_SIZE_BASE_IDX 0 240 + #define mmSDMA0_GFX_SKIP_CNTL 0x0090 241 + #define mmSDMA0_GFX_SKIP_CNTL_BASE_IDX 0 242 + #define mmSDMA0_GFX_CONTEXT_STATUS 0x0091 243 + #define mmSDMA0_GFX_CONTEXT_STATUS_BASE_IDX 0 244 + #define mmSDMA0_GFX_DOORBELL 0x0092 245 + #define mmSDMA0_GFX_DOORBELL_BASE_IDX 0 246 + #define mmSDMA0_GFX_CONTEXT_CNTL 0x0093 247 + #define mmSDMA0_GFX_CONTEXT_CNTL_BASE_IDX 0 248 + #define mmSDMA0_GFX_STATUS 0x00a8 249 + #define mmSDMA0_GFX_STATUS_BASE_IDX 0 250 + #define mmSDMA0_GFX_DOORBELL_LOG 0x00a9 251 + #define mmSDMA0_GFX_DOORBELL_LOG_BASE_IDX 0 252 + #define mmSDMA0_GFX_WATERMARK 0x00aa 253 + #define mmSDMA0_GFX_WATERMARK_BASE_IDX 0 254 + #define mmSDMA0_GFX_DOORBELL_OFFSET 0x00ab 255 + #define mmSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX 0 256 + #define mmSDMA0_GFX_CSA_ADDR_LO 0x00ac 257 + #define mmSDMA0_GFX_CSA_ADDR_LO_BASE_IDX 0 258 + #define mmSDMA0_GFX_CSA_ADDR_HI 0x00ad 259 + #define mmSDMA0_GFX_CSA_ADDR_HI_BASE_IDX 0 260 + #define mmSDMA0_GFX_IB_SUB_REMAIN 0x00af 261 + #define mmSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX 0 262 + #define mmSDMA0_GFX_PREEMPT 0x00b0 263 + #define mmSDMA0_GFX_PREEMPT_BASE_IDX 0 264 + #define mmSDMA0_GFX_DUMMY_REG 0x00b1 265 + #define mmSDMA0_GFX_DUMMY_REG_BASE_IDX 0 266 + #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 267 + #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 268 + #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 269 + #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 270 + #define mmSDMA0_GFX_RB_AQL_CNTL 0x00b4 271 + #define mmSDMA0_GFX_RB_AQL_CNTL_BASE_IDX 0 272 + #define mmSDMA0_GFX_MINOR_PTR_UPDATE 0x00b5 273 + #define mmSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 274 + #define mmSDMA0_GFX_MIDCMD_DATA0 0x00c0 275 + #define mmSDMA0_GFX_MIDCMD_DATA0_BASE_IDX 0 276 + #define mmSDMA0_GFX_MIDCMD_DATA1 0x00c1 277 + #define mmSDMA0_GFX_MIDCMD_DATA1_BASE_IDX 0 278 + #define mmSDMA0_GFX_MIDCMD_DATA2 0x00c2 279 + #define mmSDMA0_GFX_MIDCMD_DATA2_BASE_IDX 0 280 + #define mmSDMA0_GFX_MIDCMD_DATA3 0x00c3 281 + #define mmSDMA0_GFX_MIDCMD_DATA3_BASE_IDX 0 282 + #define mmSDMA0_GFX_MIDCMD_DATA4 0x00c4 283 + #define mmSDMA0_GFX_MIDCMD_DATA4_BASE_IDX 0 284 + #define mmSDMA0_GFX_MIDCMD_DATA5 0x00c5 285 + #define mmSDMA0_GFX_MIDCMD_DATA5_BASE_IDX 0 286 + #define mmSDMA0_GFX_MIDCMD_DATA6 0x00c6 287 + #define mmSDMA0_GFX_MIDCMD_DATA6_BASE_IDX 0 288 + #define mmSDMA0_GFX_MIDCMD_DATA7 0x00c7 289 + #define mmSDMA0_GFX_MIDCMD_DATA7_BASE_IDX 0 290 + #define mmSDMA0_GFX_MIDCMD_DATA8 0x00c8 291 + #define mmSDMA0_GFX_MIDCMD_DATA8_BASE_IDX 0 292 + #define mmSDMA0_GFX_MIDCMD_CNTL 0x00c9 293 + #define mmSDMA0_GFX_MIDCMD_CNTL_BASE_IDX 0 294 + #define mmSDMA0_PAGE_RB_CNTL 0x00e0 295 + #define mmSDMA0_PAGE_RB_CNTL_BASE_IDX 0 296 + #define mmSDMA0_PAGE_RB_BASE 0x00e1 297 + #define mmSDMA0_PAGE_RB_BASE_BASE_IDX 0 298 + #define mmSDMA0_PAGE_RB_BASE_HI 0x00e2 299 + #define mmSDMA0_PAGE_RB_BASE_HI_BASE_IDX 0 300 + #define mmSDMA0_PAGE_RB_RPTR 0x00e3 301 + #define mmSDMA0_PAGE_RB_RPTR_BASE_IDX 0 302 + #define mmSDMA0_PAGE_RB_RPTR_HI 0x00e4 303 + #define mmSDMA0_PAGE_RB_RPTR_HI_BASE_IDX 0 304 + #define mmSDMA0_PAGE_RB_WPTR 0x00e5 305 + #define mmSDMA0_PAGE_RB_WPTR_BASE_IDX 0 306 + #define mmSDMA0_PAGE_RB_WPTR_HI 0x00e6 307 + #define mmSDMA0_PAGE_RB_WPTR_HI_BASE_IDX 0 308 + #define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL 0x00e7 309 + #define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 310 + #define mmSDMA0_PAGE_RB_RPTR_ADDR_HI 0x00e8 311 + #define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 312 + #define mmSDMA0_PAGE_RB_RPTR_ADDR_LO 0x00e9 313 + #define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 314 + #define mmSDMA0_PAGE_IB_CNTL 0x00ea 315 + #define mmSDMA0_PAGE_IB_CNTL_BASE_IDX 0 316 + #define mmSDMA0_PAGE_IB_RPTR 0x00eb 317 + #define mmSDMA0_PAGE_IB_RPTR_BASE_IDX 0 318 + #define mmSDMA0_PAGE_IB_OFFSET 0x00ec 319 + #define mmSDMA0_PAGE_IB_OFFSET_BASE_IDX 0 320 + #define mmSDMA0_PAGE_IB_BASE_LO 0x00ed 321 + #define mmSDMA0_PAGE_IB_BASE_LO_BASE_IDX 0 322 + #define mmSDMA0_PAGE_IB_BASE_HI 0x00ee 323 + #define mmSDMA0_PAGE_IB_BASE_HI_BASE_IDX 0 324 + #define mmSDMA0_PAGE_IB_SIZE 0x00ef 325 + #define mmSDMA0_PAGE_IB_SIZE_BASE_IDX 0 326 + #define mmSDMA0_PAGE_SKIP_CNTL 0x00f0 327 + #define mmSDMA0_PAGE_SKIP_CNTL_BASE_IDX 0 328 + #define mmSDMA0_PAGE_CONTEXT_STATUS 0x00f1 329 + #define mmSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX 0 330 + #define mmSDMA0_PAGE_DOORBELL 0x00f2 331 + #define mmSDMA0_PAGE_DOORBELL_BASE_IDX 0 332 + #define mmSDMA0_PAGE_STATUS 0x0108 333 + #define mmSDMA0_PAGE_STATUS_BASE_IDX 0 334 + #define mmSDMA0_PAGE_DOORBELL_LOG 0x0109 335 + #define mmSDMA0_PAGE_DOORBELL_LOG_BASE_IDX 0 336 + #define mmSDMA0_PAGE_WATERMARK 0x010a 337 + #define mmSDMA0_PAGE_WATERMARK_BASE_IDX 0 338 + #define mmSDMA0_PAGE_DOORBELL_OFFSET 0x010b 339 + #define mmSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX 0 340 + #define mmSDMA0_PAGE_CSA_ADDR_LO 0x010c 341 + #define mmSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX 0 342 + #define mmSDMA0_PAGE_CSA_ADDR_HI 0x010d 343 + #define mmSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX 0 344 + #define mmSDMA0_PAGE_IB_SUB_REMAIN 0x010f 345 + #define mmSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX 0 346 + #define mmSDMA0_PAGE_PREEMPT 0x0110 347 + #define mmSDMA0_PAGE_PREEMPT_BASE_IDX 0 348 + #define mmSDMA0_PAGE_DUMMY_REG 0x0111 349 + #define mmSDMA0_PAGE_DUMMY_REG_BASE_IDX 0 350 + #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 0x0112 351 + #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 352 + #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 0x0113 353 + #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 354 + #define mmSDMA0_PAGE_RB_AQL_CNTL 0x0114 355 + #define mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX 0 356 + #define mmSDMA0_PAGE_MINOR_PTR_UPDATE 0x0115 357 + #define mmSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 358 + #define mmSDMA0_PAGE_MIDCMD_DATA0 0x0120 359 + #define mmSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX 0 360 + #define mmSDMA0_PAGE_MIDCMD_DATA1 0x0121 361 + #define mmSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX 0 362 + #define mmSDMA0_PAGE_MIDCMD_DATA2 0x0122 363 + #define mmSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX 0 364 + #define mmSDMA0_PAGE_MIDCMD_DATA3 0x0123 365 + #define mmSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX 0 366 + #define mmSDMA0_PAGE_MIDCMD_DATA4 0x0124 367 + #define mmSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX 0 368 + #define mmSDMA0_PAGE_MIDCMD_DATA5 0x0125 369 + #define mmSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX 0 370 + #define mmSDMA0_PAGE_MIDCMD_DATA6 0x0126 371 + #define mmSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX 0 372 + #define mmSDMA0_PAGE_MIDCMD_DATA7 0x0127 373 + #define mmSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX 0 374 + #define mmSDMA0_PAGE_MIDCMD_DATA8 0x0128 375 + #define mmSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX 0 376 + #define mmSDMA0_PAGE_MIDCMD_CNTL 0x0129 377 + #define mmSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX 0 378 + #define mmSDMA0_RLC0_RB_CNTL 0x0140 379 + #define mmSDMA0_RLC0_RB_CNTL_BASE_IDX 0 380 + #define mmSDMA0_RLC0_RB_BASE 0x0141 381 + #define mmSDMA0_RLC0_RB_BASE_BASE_IDX 0 382 + #define mmSDMA0_RLC0_RB_BASE_HI 0x0142 383 + #define mmSDMA0_RLC0_RB_BASE_HI_BASE_IDX 0 384 + #define mmSDMA0_RLC0_RB_RPTR 0x0143 385 + #define mmSDMA0_RLC0_RB_RPTR_BASE_IDX 0 386 + #define mmSDMA0_RLC0_RB_RPTR_HI 0x0144 387 + #define mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX 0 388 + #define mmSDMA0_RLC0_RB_WPTR 0x0145 389 + #define mmSDMA0_RLC0_RB_WPTR_BASE_IDX 0 390 + #define mmSDMA0_RLC0_RB_WPTR_HI 0x0146 391 + #define mmSDMA0_RLC0_RB_WPTR_HI_BASE_IDX 0 392 + #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x0147 393 + #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 394 + #define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x0148 395 + #define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 396 + #define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x0149 397 + #define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 398 + #define mmSDMA0_RLC0_IB_CNTL 0x014a 399 + #define mmSDMA0_RLC0_IB_CNTL_BASE_IDX 0 400 + #define mmSDMA0_RLC0_IB_RPTR 0x014b 401 + #define mmSDMA0_RLC0_IB_RPTR_BASE_IDX 0 402 + #define mmSDMA0_RLC0_IB_OFFSET 0x014c 403 + #define mmSDMA0_RLC0_IB_OFFSET_BASE_IDX 0 404 + #define mmSDMA0_RLC0_IB_BASE_LO 0x014d 405 + #define mmSDMA0_RLC0_IB_BASE_LO_BASE_IDX 0 406 + #define mmSDMA0_RLC0_IB_BASE_HI 0x014e 407 + #define mmSDMA0_RLC0_IB_BASE_HI_BASE_IDX 0 408 + #define mmSDMA0_RLC0_IB_SIZE 0x014f 409 + #define mmSDMA0_RLC0_IB_SIZE_BASE_IDX 0 410 + #define mmSDMA0_RLC0_SKIP_CNTL 0x0150 411 + #define mmSDMA0_RLC0_SKIP_CNTL_BASE_IDX 0 412 + #define mmSDMA0_RLC0_CONTEXT_STATUS 0x0151 413 + #define mmSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX 0 414 + #define mmSDMA0_RLC0_DOORBELL 0x0152 415 + #define mmSDMA0_RLC0_DOORBELL_BASE_IDX 0 416 + #define mmSDMA0_RLC0_STATUS 0x0168 417 + #define mmSDMA0_RLC0_STATUS_BASE_IDX 0 418 + #define mmSDMA0_RLC0_DOORBELL_LOG 0x0169 419 + #define mmSDMA0_RLC0_DOORBELL_LOG_BASE_IDX 0 420 + #define mmSDMA0_RLC0_WATERMARK 0x016a 421 + #define mmSDMA0_RLC0_WATERMARK_BASE_IDX 0 422 + #define mmSDMA0_RLC0_DOORBELL_OFFSET 0x016b 423 + #define mmSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX 0 424 + #define mmSDMA0_RLC0_CSA_ADDR_LO 0x016c 425 + #define mmSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX 0 426 + #define mmSDMA0_RLC0_CSA_ADDR_HI 0x016d 427 + #define mmSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX 0 428 + #define mmSDMA0_RLC0_IB_SUB_REMAIN 0x016f 429 + #define mmSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX 0 430 + #define mmSDMA0_RLC0_PREEMPT 0x0170 431 + #define mmSDMA0_RLC0_PREEMPT_BASE_IDX 0 432 + #define mmSDMA0_RLC0_DUMMY_REG 0x0171 433 + #define mmSDMA0_RLC0_DUMMY_REG_BASE_IDX 0 434 + #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x0172 435 + #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 436 + #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x0173 437 + #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 438 + #define mmSDMA0_RLC0_RB_AQL_CNTL 0x0174 439 + #define mmSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX 0 440 + #define mmSDMA0_RLC0_MINOR_PTR_UPDATE 0x0175 441 + #define mmSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 442 + #define mmSDMA0_RLC0_MIDCMD_DATA0 0x0180 443 + #define mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX 0 444 + #define mmSDMA0_RLC0_MIDCMD_DATA1 0x0181 445 + #define mmSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX 0 446 + #define mmSDMA0_RLC0_MIDCMD_DATA2 0x0182 447 + #define mmSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX 0 448 + #define mmSDMA0_RLC0_MIDCMD_DATA3 0x0183 449 + #define mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX 0 450 + #define mmSDMA0_RLC0_MIDCMD_DATA4 0x0184 451 + #define mmSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX 0 452 + #define mmSDMA0_RLC0_MIDCMD_DATA5 0x0185 453 + #define mmSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX 0 454 + #define mmSDMA0_RLC0_MIDCMD_DATA6 0x0186 455 + #define mmSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX 0 456 + #define mmSDMA0_RLC0_MIDCMD_DATA7 0x0187 457 + #define mmSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX 0 458 + #define mmSDMA0_RLC0_MIDCMD_DATA8 0x0188 459 + #define mmSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX 0 460 + #define mmSDMA0_RLC0_MIDCMD_CNTL 0x0189 461 + #define mmSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX 0 462 + #define mmSDMA0_RLC1_RB_CNTL 0x01a0 463 + #define mmSDMA0_RLC1_RB_CNTL_BASE_IDX 0 464 + #define mmSDMA0_RLC1_RB_BASE 0x01a1 465 + #define mmSDMA0_RLC1_RB_BASE_BASE_IDX 0 466 + #define mmSDMA0_RLC1_RB_BASE_HI 0x01a2 467 + #define mmSDMA0_RLC1_RB_BASE_HI_BASE_IDX 0 468 + #define mmSDMA0_RLC1_RB_RPTR 0x01a3 469 + #define mmSDMA0_RLC1_RB_RPTR_BASE_IDX 0 470 + #define mmSDMA0_RLC1_RB_RPTR_HI 0x01a4 471 + #define mmSDMA0_RLC1_RB_RPTR_HI_BASE_IDX 0 472 + #define mmSDMA0_RLC1_RB_WPTR 0x01a5 473 + #define mmSDMA0_RLC1_RB_WPTR_BASE_IDX 0 474 + #define mmSDMA0_RLC1_RB_WPTR_HI 0x01a6 475 + #define mmSDMA0_RLC1_RB_WPTR_HI_BASE_IDX 0 476 + #define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x01a7 477 + #define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 478 + #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x01a8 479 + #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 480 + #define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x01a9 481 + #define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 482 + #define mmSDMA0_RLC1_IB_CNTL 0x01aa 483 + #define mmSDMA0_RLC1_IB_CNTL_BASE_IDX 0 484 + #define mmSDMA0_RLC1_IB_RPTR 0x01ab 485 + #define mmSDMA0_RLC1_IB_RPTR_BASE_IDX 0 486 + #define mmSDMA0_RLC1_IB_OFFSET 0x01ac 487 + #define mmSDMA0_RLC1_IB_OFFSET_BASE_IDX 0 488 + #define mmSDMA0_RLC1_IB_BASE_LO 0x01ad 489 + #define mmSDMA0_RLC1_IB_BASE_LO_BASE_IDX 0 490 + #define mmSDMA0_RLC1_IB_BASE_HI 0x01ae 491 + #define mmSDMA0_RLC1_IB_BASE_HI_BASE_IDX 0 492 + #define mmSDMA0_RLC1_IB_SIZE 0x01af 493 + #define mmSDMA0_RLC1_IB_SIZE_BASE_IDX 0 494 + #define mmSDMA0_RLC1_SKIP_CNTL 0x01b0 495 + #define mmSDMA0_RLC1_SKIP_CNTL_BASE_IDX 0 496 + #define mmSDMA0_RLC1_CONTEXT_STATUS 0x01b1 497 + #define mmSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX 0 498 + #define mmSDMA0_RLC1_DOORBELL 0x01b2 499 + #define mmSDMA0_RLC1_DOORBELL_BASE_IDX 0 500 + #define mmSDMA0_RLC1_STATUS 0x01c8 501 + #define mmSDMA0_RLC1_STATUS_BASE_IDX 0 502 + #define mmSDMA0_RLC1_DOORBELL_LOG 0x01c9 503 + #define mmSDMA0_RLC1_DOORBELL_LOG_BASE_IDX 0 504 + #define mmSDMA0_RLC1_WATERMARK 0x01ca 505 + #define mmSDMA0_RLC1_WATERMARK_BASE_IDX 0 506 + #define mmSDMA0_RLC1_DOORBELL_OFFSET 0x01cb 507 + #define mmSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX 0 508 + #define mmSDMA0_RLC1_CSA_ADDR_LO 0x01cc 509 + #define mmSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX 0 510 + #define mmSDMA0_RLC1_CSA_ADDR_HI 0x01cd 511 + #define mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX 0 512 + #define mmSDMA0_RLC1_IB_SUB_REMAIN 0x01cf 513 + #define mmSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX 0 514 + #define mmSDMA0_RLC1_PREEMPT 0x01d0 515 + #define mmSDMA0_RLC1_PREEMPT_BASE_IDX 0 516 + #define mmSDMA0_RLC1_DUMMY_REG 0x01d1 517 + #define mmSDMA0_RLC1_DUMMY_REG_BASE_IDX 0 518 + #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x01d2 519 + #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 520 + #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x01d3 521 + #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 522 + #define mmSDMA0_RLC1_RB_AQL_CNTL 0x01d4 523 + #define mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX 0 524 + #define mmSDMA0_RLC1_MINOR_PTR_UPDATE 0x01d5 525 + #define mmSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 526 + #define mmSDMA0_RLC1_MIDCMD_DATA0 0x01e0 527 + #define mmSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX 0 528 + #define mmSDMA0_RLC1_MIDCMD_DATA1 0x01e1 529 + #define mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX 0 530 + #define mmSDMA0_RLC1_MIDCMD_DATA2 0x01e2 531 + #define mmSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX 0 532 + #define mmSDMA0_RLC1_MIDCMD_DATA3 0x01e3 533 + #define mmSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX 0 534 + #define mmSDMA0_RLC1_MIDCMD_DATA4 0x01e4 535 + #define mmSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX 0 536 + #define mmSDMA0_RLC1_MIDCMD_DATA5 0x01e5 537 + #define mmSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX 0 538 + #define mmSDMA0_RLC1_MIDCMD_DATA6 0x01e6 539 + #define mmSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX 0 540 + #define mmSDMA0_RLC1_MIDCMD_DATA7 0x01e7 541 + #define mmSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX 0 542 + #define mmSDMA0_RLC1_MIDCMD_DATA8 0x01e8 543 + #define mmSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX 0 544 + #define mmSDMA0_RLC1_MIDCMD_CNTL 0x01e9 545 + #define mmSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX 0 546 + 547 + #endif
+1852
drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h
··· 1 + /* 2 + * Copyright (C) 2017 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included 12 + * in all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 + */ 21 + #ifndef _sdma0_4_0_SH_MASK_HEADER 22 + #define _sdma0_4_0_SH_MASK_HEADER 23 + 24 + 25 + // addressBlock: sdma0_sdma0dec 26 + //SDMA0_UCODE_ADDR 27 + #define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 28 + #define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL 29 + //SDMA0_UCODE_DATA 30 + #define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 31 + #define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 32 + //SDMA0_VM_CNTL 33 + #define SDMA0_VM_CNTL__CMD__SHIFT 0x0 34 + #define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL 35 + //SDMA0_VM_CTX_LO 36 + #define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 37 + #define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL 38 + //SDMA0_VM_CTX_HI 39 + #define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 40 + #define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL 41 + //SDMA0_ACTIVE_FCN_ID 42 + #define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 43 + #define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 44 + #define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f 45 + #define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 46 + #define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L 47 + #define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L 48 + //SDMA0_VM_CTX_CNTL 49 + #define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 50 + #define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 51 + #define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L 52 + #define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L 53 + //SDMA0_VIRT_RESET_REQ 54 + #define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 55 + #define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f 56 + #define SDMA0_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 57 + #define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L 58 + //SDMA0_VF_ENABLE 59 + #define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0 60 + #define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x00000001L 61 + //SDMA0_CONTEXT_REG_TYPE0 62 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 63 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 64 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 65 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 66 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4 67 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5 68 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6 69 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 70 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 71 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 72 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa 73 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb 74 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc 75 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd 76 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe 77 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf 78 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 79 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 80 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 81 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 82 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L 83 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L 84 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L 85 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L 86 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L 87 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L 88 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L 89 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L 90 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L 91 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L 92 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L 93 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L 94 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L 95 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L 96 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L 97 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L 98 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L 99 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L 100 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L 101 + #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L 102 + //SDMA0_CONTEXT_REG_TYPE1 103 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8 104 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9 105 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa 106 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb 107 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc 108 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd 109 + #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe 110 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf 111 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 112 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 113 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 114 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 115 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14 116 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 117 + #define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 118 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L 119 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x00000200L 120 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L 121 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L 122 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L 123 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L 124 + #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L 125 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L 126 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L 127 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L 128 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L 129 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L 130 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L 131 + #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L 132 + #define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L 133 + //SDMA0_CONTEXT_REG_TYPE2 134 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 135 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 136 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 137 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 138 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 139 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 140 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6 141 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7 142 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8 143 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9 144 + #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa 145 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L 146 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L 147 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L 148 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L 149 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L 150 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L 151 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L 152 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L 153 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L 154 + #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L 155 + #define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L 156 + //SDMA0_CONTEXT_REG_TYPE3 157 + #define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 158 + #define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL 159 + //SDMA0_PUB_REG_TYPE0 160 + #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 161 + #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 162 + #define SDMA0_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 163 + #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT 0x4 164 + #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT 0x5 165 + #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT 0x6 166 + #define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT 0x7 167 + #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT 0x8 168 + #define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT 0x9 169 + #define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa 170 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT 0xb 171 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT 0xc 172 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT 0xd 173 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT 0xe 174 + #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT 0xf 175 + #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT 0x10 176 + #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT 0x11 177 + #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT 0x12 178 + #define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL__SHIFT 0x13 179 + #define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 180 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 181 + #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x1a 182 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x1b 183 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x1c 184 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d 185 + #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x1e 186 + #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x1f 187 + #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L 188 + #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L 189 + #define SDMA0_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L 190 + #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK 0x00000010L 191 + #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK 0x00000020L 192 + #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK 0x00000040L 193 + #define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK 0x00000080L 194 + #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK 0x00000100L 195 + #define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK 0x00000200L 196 + #define SDMA0_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L 197 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK 0x00000800L 198 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK 0x00001000L 199 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK 0x00002000L 200 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK 0x00004000L 201 + #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK 0x00008000L 202 + #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK 0x00010000L 203 + #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK 0x00020000L 204 + #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK 0x00040000L 205 + #define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL_MASK 0x00080000L 206 + #define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L 207 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L 208 + #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L 209 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x08000000L 210 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L 211 + #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L 212 + #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L 213 + #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L 214 + //SDMA0_PUB_REG_TYPE1 215 + #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x0 216 + #define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 217 + #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x2 218 + #define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x3 219 + #define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x4 220 + #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x5 221 + #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x6 222 + #define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT 0x7 223 + #define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x8 224 + #define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x9 225 + #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa 226 + #define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0xb 227 + #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT 0xc 228 + #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT 0xd 229 + #define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe 230 + #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf 231 + #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 232 + #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 233 + #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x12 234 + #define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x13 235 + #define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x14 236 + #define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x15 237 + #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x16 238 + #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x17 239 + #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x18 240 + #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x19 241 + #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x1a 242 + #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x1b 243 + #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x1c 244 + #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d 245 + #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT 0x1e 246 + #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT 0x1f 247 + #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000001L 248 + #define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L 249 + #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000004L 250 + #define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L 251 + #define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L 252 + #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L 253 + #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L 254 + #define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK 0x00000080L 255 + #define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L 256 + #define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L 257 + #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK 0x00000400L 258 + #define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L 259 + #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK 0x00001000L 260 + #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK 0x00002000L 261 + #define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L 262 + #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L 263 + #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L 264 + #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L 265 + #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L 266 + #define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L 267 + #define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L 268 + #define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L 269 + #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L 270 + #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L 271 + #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L 272 + #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L 273 + #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L 274 + #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L 275 + #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L 276 + #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L 277 + #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK 0x40000000L 278 + #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK 0x80000000L 279 + //SDMA0_PUB_REG_TYPE2 280 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x0 281 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x1 282 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x2 283 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x3 284 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x4 285 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x5 286 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x6 287 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT 0x7 288 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT 0x8 289 + #define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE__SHIFT 0x9 290 + #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa 291 + #define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0xb 292 + #define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0xc 293 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0xd 294 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0xe 295 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM__SHIFT 0xf 296 + #define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x10 297 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x11 298 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x12 299 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x13 300 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x14 301 + #define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x15 302 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE__SHIFT 0x16 303 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL__SHIFT 0x17 304 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x18 305 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x19 306 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a 307 + #define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x1b 308 + #define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL__SHIFT 0x1c 309 + #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d 310 + #define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL__SHIFT 0x1e 311 + #define SDMA0_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f 312 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000001L 313 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000002L 314 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000004L 315 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000008L 316 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000010L 317 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000020L 318 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000040L 319 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK 0x00000080L 320 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK 0x00000100L 321 + #define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE_MASK 0x00000200L 322 + #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L 323 + #define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L 324 + #define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L 325 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L 326 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L 327 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM_MASK 0x00008000L 328 + #define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L 329 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L 330 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L 331 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L 332 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L 333 + #define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L 334 + #define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE_MASK 0x00400000L 335 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL_MASK 0x00800000L 336 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT_MASK 0x01000000L 337 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT_MASK 0x02000000L 338 + #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L 339 + #define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L 340 + #define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL_MASK 0x10000000L 341 + #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L 342 + #define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL_MASK 0x40000000L 343 + #define SDMA0_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L 344 + //SDMA0_PUB_REG_TYPE3 345 + #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x0 346 + #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x1 347 + #define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x2 348 + #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L 349 + #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L 350 + #define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL 351 + //SDMA0_MMHUB_CNTL 352 + #define SDMA0_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 353 + #define SDMA0_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL 354 + //SDMA0_CONTEXT_GROUP_BOUNDARY 355 + #define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 356 + #define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL 357 + //SDMA0_POWER_CNTL 358 + #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 359 + #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 360 + #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 361 + #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 362 + #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 363 + #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 364 + #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 365 + #define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 366 + #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L 367 + #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L 368 + #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L 369 + #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L 370 + #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L 371 + #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L 372 + #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L 373 + #define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L 374 + //SDMA0_CLK_CTRL 375 + #define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 376 + #define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 377 + #define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc 378 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 379 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 380 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 381 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 382 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 383 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 384 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 385 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 386 + #define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 387 + #define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 388 + #define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L 389 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 390 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 391 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 392 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 393 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 394 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 395 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 396 + #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 397 + //SDMA0_CNTL 398 + #define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 399 + #define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1 400 + #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 401 + #define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 402 + #define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 403 + #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 404 + #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 405 + #define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 406 + #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 407 + #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 408 + #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 409 + #define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L 410 + #define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L 411 + #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L 412 + #define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L 413 + #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L 414 + #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L 415 + #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 416 + #define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L 417 + #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L 418 + #define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L 419 + #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L 420 + //SDMA0_CHICKEN_BITS 421 + #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 422 + #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 423 + #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 424 + #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 425 + #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 426 + #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 427 + #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 428 + #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 429 + #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 430 + #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 431 + #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a 432 + #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c 433 + #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e 434 + #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L 435 + #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L 436 + #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L 437 + #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L 438 + #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L 439 + #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L 440 + #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L 441 + #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L 442 + #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L 443 + #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L 444 + #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L 445 + #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L 446 + #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L 447 + //SDMA0_GB_ADDR_CONFIG 448 + #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 449 + #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 450 + #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 451 + #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 452 + #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 453 + #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 454 + #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 455 + #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 456 + #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 457 + #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 458 + //SDMA0_GB_ADDR_CONFIG_READ 459 + #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 460 + #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 461 + #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 462 + #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc 463 + #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 464 + #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 465 + #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 466 + #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 467 + #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L 468 + #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 469 + //SDMA0_RB_RPTR_FETCH_HI 470 + #define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 471 + #define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 472 + //SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 473 + #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 474 + #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL 475 + //SDMA0_RB_RPTR_FETCH 476 + #define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 477 + #define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 478 + //SDMA0_IB_OFFSET_FETCH 479 + #define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 480 + #define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 481 + //SDMA0_PROGRAM 482 + #define SDMA0_PROGRAM__STREAM__SHIFT 0x0 483 + #define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL 484 + //SDMA0_STATUS_REG 485 + #define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 486 + #define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 487 + #define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 488 + #define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 489 + #define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 490 + #define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 491 + #define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 492 + #define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 493 + #define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 494 + #define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 495 + #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa 496 + #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 497 + #define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc 498 + #define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 499 + #define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe 500 + #define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 501 + #define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 502 + #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 503 + #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 504 + #define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 505 + #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 506 + #define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 507 + #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 508 + #define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 509 + #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a 510 + #define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 511 + #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 512 + #define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e 513 + #define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 514 + #define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L 515 + #define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L 516 + #define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L 517 + #define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L 518 + #define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L 519 + #define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L 520 + #define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L 521 + #define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L 522 + #define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L 523 + #define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L 524 + #define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L 525 + #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L 526 + #define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L 527 + #define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L 528 + #define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L 529 + #define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L 530 + #define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L 531 + #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L 532 + #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L 533 + #define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L 534 + #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L 535 + #define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L 536 + #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L 537 + #define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L 538 + #define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L 539 + #define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L 540 + #define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L 541 + #define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L 542 + #define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L 543 + //SDMA0_STATUS1_REG 544 + #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 545 + #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 546 + #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 547 + #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 548 + #define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 549 + #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 550 + #define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 551 + #define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 552 + #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 553 + #define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 554 + #define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 555 + #define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf 556 + #define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 557 + #define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 558 + #define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L 559 + #define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L 560 + #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L 561 + #define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L 562 + #define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L 563 + #define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L 564 + #define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L 565 + #define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L 566 + #define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L 567 + #define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L 568 + #define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L 569 + #define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L 570 + #define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L 571 + #define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L 572 + //SDMA0_RD_BURST_CNTL 573 + #define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 574 + #define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L 575 + //SDMA0_HBM_PAGE_CONFIG 576 + #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 577 + #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L 578 + //SDMA0_UCODE_CHECKSUM 579 + #define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0 580 + #define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 581 + //SDMA0_F32_CNTL 582 + #define SDMA0_F32_CNTL__HALT__SHIFT 0x0 583 + #define SDMA0_F32_CNTL__STEP__SHIFT 0x1 584 + #define SDMA0_F32_CNTL__HALT_MASK 0x00000001L 585 + #define SDMA0_F32_CNTL__STEP_MASK 0x00000002L 586 + //SDMA0_FREEZE 587 + #define SDMA0_FREEZE__PREEMPT__SHIFT 0x0 588 + #define SDMA0_FREEZE__FREEZE__SHIFT 0x4 589 + #define SDMA0_FREEZE__FROZEN__SHIFT 0x5 590 + #define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 591 + #define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L 592 + #define SDMA0_FREEZE__FREEZE_MASK 0x00000010L 593 + #define SDMA0_FREEZE__FROZEN_MASK 0x00000020L 594 + #define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L 595 + //SDMA0_PHASE0_QUANTUM 596 + #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 597 + #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 598 + #define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 599 + #define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL 600 + #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L 601 + #define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L 602 + //SDMA0_PHASE1_QUANTUM 603 + #define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 604 + #define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 605 + #define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 606 + #define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL 607 + #define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L 608 + #define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L 609 + //SDMA_POWER_GATING 610 + #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0 611 + #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1 612 + #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2 613 + #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3 614 + #define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 615 + #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L 616 + #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L 617 + #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L 618 + #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L 619 + #define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L 620 + //SDMA_PGFSM_CONFIG 621 + #define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 622 + #define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 623 + #define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 624 + #define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa 625 + #define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb 626 + #define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc 627 + #define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd 628 + #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b 629 + #define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c 630 + #define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL 631 + #define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L 632 + #define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L 633 + #define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L 634 + #define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L 635 + #define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L 636 + #define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L 637 + #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L 638 + #define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L 639 + //SDMA_PGFSM_WRITE 640 + #define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 641 + #define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL 642 + //SDMA_PGFSM_READ 643 + #define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 644 + #define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL 645 + //SDMA0_EDC_CONFIG 646 + #define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 647 + #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 648 + #define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 649 + #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L 650 + //SDMA0_BA_THRESHOLD 651 + #define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 652 + #define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 653 + #define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL 654 + #define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L 655 + //SDMA0_ID 656 + #define SDMA0_ID__DEVICE_ID__SHIFT 0x0 657 + #define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL 658 + //SDMA0_VERSION 659 + #define SDMA0_VERSION__MINVER__SHIFT 0x0 660 + #define SDMA0_VERSION__MAJVER__SHIFT 0x8 661 + #define SDMA0_VERSION__REV__SHIFT 0x10 662 + #define SDMA0_VERSION__MINVER_MASK 0x0000007FL 663 + #define SDMA0_VERSION__MAJVER_MASK 0x00007F00L 664 + #define SDMA0_VERSION__REV_MASK 0x003F0000L 665 + //SDMA0_EDC_COUNTER 666 + #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 667 + #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 668 + #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 669 + #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 670 + #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 671 + #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 672 + #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 673 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 674 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 675 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 676 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa 677 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb 678 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc 679 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd 680 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe 681 + #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf 682 + #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 683 + #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L 684 + #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L 685 + #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L 686 + #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L 687 + #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L 688 + #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L 689 + #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L 690 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L 691 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L 692 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L 693 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L 694 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L 695 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L 696 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L 697 + #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L 698 + #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L 699 + #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L 700 + //SDMA0_EDC_COUNTER_CLEAR 701 + #define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 702 + #define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L 703 + //SDMA0_STATUS2_REG 704 + #define SDMA0_STATUS2_REG__ID__SHIFT 0x0 705 + #define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 706 + #define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 707 + #define SDMA0_STATUS2_REG__ID_MASK 0x00000003L 708 + #define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL 709 + #define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L 710 + //SDMA0_ATOMIC_CNTL 711 + #define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 712 + #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 713 + #define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 714 + #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L 715 + //SDMA0_ATOMIC_PREOP_LO 716 + #define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 717 + #define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 718 + //SDMA0_ATOMIC_PREOP_HI 719 + #define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 720 + #define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 721 + //SDMA0_UTCL1_CNTL 722 + #define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 723 + #define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 724 + #define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb 725 + #define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe 726 + #define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 727 + #define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d 728 + #define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L 729 + #define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL 730 + #define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L 731 + #define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L 732 + #define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L 733 + #define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L 734 + //SDMA0_UTCL1_WATERMK 735 + #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 736 + #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa 737 + #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 738 + #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a 739 + #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL 740 + #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L 741 + #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L 742 + #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L 743 + //SDMA0_UTCL1_RD_STATUS 744 + #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 745 + #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 746 + #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 747 + #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 748 + #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 749 + #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 750 + #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 751 + #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 752 + #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 753 + #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 754 + #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 755 + #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 756 + #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 757 + #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 758 + #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 759 + #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 760 + #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 761 + #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 762 + #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 763 + #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 764 + #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 765 + #define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 766 + #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 767 + #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 768 + #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d 769 + #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e 770 + #define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f 771 + #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 772 + #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 773 + #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 774 + #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 775 + #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 776 + #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 777 + #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 778 + #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 779 + #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 780 + #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 781 + #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 782 + #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 783 + #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 784 + #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 785 + #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 786 + #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 787 + #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 788 + #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 789 + #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L 790 + #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L 791 + #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L 792 + #define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L 793 + #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L 794 + #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L 795 + #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L 796 + #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L 797 + #define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L 798 + //SDMA0_UTCL1_WR_STATUS 799 + #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 800 + #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 801 + #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 802 + #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 803 + #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 804 + #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 805 + #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 806 + #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 807 + #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 808 + #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 809 + #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 810 + #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 811 + #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 812 + #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 813 + #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 814 + #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 815 + #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 816 + #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 817 + #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 818 + #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 819 + #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 820 + #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 821 + #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 822 + #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 823 + #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c 824 + #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d 825 + #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e 826 + #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f 827 + #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 828 + #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 829 + #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 830 + #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 831 + #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 832 + #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 833 + #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 834 + #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 835 + #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 836 + #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 837 + #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 838 + #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 839 + #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 840 + #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 841 + #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 842 + #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 843 + #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 844 + #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 845 + #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L 846 + #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L 847 + #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L 848 + #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L 849 + #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L 850 + #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L 851 + #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L 852 + #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L 853 + #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L 854 + #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L 855 + //SDMA0_UTCL1_INV0 856 + #define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 857 + #define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 858 + #define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 859 + #define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 860 + #define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 861 + #define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 862 + #define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 863 + #define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 864 + #define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 865 + #define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 866 + #define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa 867 + #define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 868 + #define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc 869 + #define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 870 + #define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L 871 + #define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L 872 + #define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L 873 + #define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L 874 + #define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L 875 + #define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L 876 + #define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L 877 + #define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L 878 + #define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L 879 + #define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L 880 + #define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L 881 + #define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L 882 + #define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L 883 + #define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L 884 + //SDMA0_UTCL1_INV1 885 + #define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 886 + #define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL 887 + //SDMA0_UTCL1_INV2 888 + #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 889 + #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL 890 + //SDMA0_UTCL1_RD_XNACK0 891 + #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 892 + #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 893 + //SDMA0_UTCL1_RD_XNACK1 894 + #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 895 + #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 896 + #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 897 + #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a 898 + #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 899 + #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L 900 + #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 901 + #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L 902 + //SDMA0_UTCL1_WR_XNACK0 903 + #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 904 + #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 905 + //SDMA0_UTCL1_WR_XNACK1 906 + #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 907 + #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 908 + #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 909 + #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a 910 + #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 911 + #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L 912 + #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 913 + #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L 914 + //SDMA0_UTCL1_TIMEOUT 915 + #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 916 + #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 917 + #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL 918 + #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L 919 + //SDMA0_UTCL1_PAGE 920 + #define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 921 + #define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 922 + #define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 923 + #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 924 + #define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L 925 + #define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL 926 + #define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L 927 + #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L 928 + //SDMA0_POWER_CNTL_IDLE 929 + #define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 930 + #define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 931 + #define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 932 + #define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL 933 + #define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L 934 + #define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L 935 + //SDMA0_RELAX_ORDERING_LUT 936 + #define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 937 + #define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 938 + #define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 939 + #define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 940 + #define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 941 + #define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 942 + #define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 943 + #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 944 + #define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 945 + #define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 946 + #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb 947 + #define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc 948 + #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 949 + #define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 950 + #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 951 + #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 952 + #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d 953 + #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 954 + #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 955 + #define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 956 + #define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L 957 + #define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L 958 + #define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 959 + #define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 960 + #define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 961 + #define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 962 + #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 963 + #define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 964 + #define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 965 + #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L 966 + #define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L 967 + #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 968 + #define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 969 + #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 970 + #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 971 + #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L 972 + #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 973 + #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 974 + //SDMA0_CHICKEN_BITS_2 975 + #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 976 + #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 977 + //SDMA0_STATUS3_REG 978 + #define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 979 + #define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 980 + #define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 981 + #define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL 982 + #define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L 983 + #define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L 984 + //SDMA0_PHYSICAL_ADDR_LO 985 + #define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 986 + #define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 987 + #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 988 + #define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc 989 + #define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L 990 + #define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L 991 + #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L 992 + #define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L 993 + //SDMA0_PHYSICAL_ADDR_HI 994 + #define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 995 + #define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL 996 + //SDMA0_PHASE2_QUANTUM 997 + #define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT 0x0 998 + #define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT 0x8 999 + #define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT 0x1e 1000 + #define SDMA0_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL 1001 + #define SDMA0_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L 1002 + #define SDMA0_PHASE2_QUANTUM__PREFER_MASK 0x40000000L 1003 + //SDMA0_ERROR_LOG 1004 + #define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0 1005 + #define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10 1006 + #define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 1007 + #define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L 1008 + //SDMA0_PUB_DUMMY_REG0 1009 + #define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 1010 + #define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL 1011 + //SDMA0_PUB_DUMMY_REG1 1012 + #define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 1013 + #define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL 1014 + //SDMA0_PUB_DUMMY_REG2 1015 + #define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 1016 + #define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL 1017 + //SDMA0_PUB_DUMMY_REG3 1018 + #define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 1019 + #define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL 1020 + //SDMA0_F32_COUNTER 1021 + #define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0 1022 + #define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 1023 + //SDMA0_UNBREAKABLE 1024 + #define SDMA0_UNBREAKABLE__VALUE__SHIFT 0x0 1025 + #define SDMA0_UNBREAKABLE__VALUE_MASK 0x00000001L 1026 + //SDMA0_PERFMON_CNTL 1027 + #define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 1028 + #define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 1029 + #define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 1030 + #define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa 1031 + #define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb 1032 + #define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc 1033 + #define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L 1034 + #define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L 1035 + #define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL 1036 + #define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L 1037 + #define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L 1038 + #define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L 1039 + //SDMA0_PERFCOUNTER0_RESULT 1040 + #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 1041 + #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1042 + //SDMA0_PERFCOUNTER1_RESULT 1043 + #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 1044 + #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1045 + //SDMA0_PERFCOUNTER_TAG_DELAY_RANGE 1046 + #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 1047 + #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe 1048 + #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c 1049 + #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL 1050 + #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L 1051 + #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L 1052 + //SDMA0_CRD_CNTL 1053 + #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 1054 + #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 1055 + #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 1056 + #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 1057 + //SDMA0_MMHUB_TRUSTLVL 1058 + #define SDMA0_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0 1059 + #define SDMA0_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x3 1060 + #define SDMA0_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x6 1061 + #define SDMA0_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x9 1062 + #define SDMA0_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0xc 1063 + #define SDMA0_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0xf 1064 + #define SDMA0_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x12 1065 + #define SDMA0_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x15 1066 + #define SDMA0_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L 1067 + #define SDMA0_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L 1068 + #define SDMA0_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001C0L 1069 + #define SDMA0_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000E00L 1070 + #define SDMA0_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L 1071 + #define SDMA0_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L 1072 + #define SDMA0_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001C0000L 1073 + #define SDMA0_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00E00000L 1074 + //SDMA0_GPU_IOV_VIOLATION_LOG 1075 + #define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 1076 + #define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 1077 + #define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 1078 + #define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12 1079 + #define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 1080 + #define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 1081 + #define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 1082 + #define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 1083 + #define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 1084 + #define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL 1085 + #define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L 1086 + #define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L 1087 + #define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L 1088 + #define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L 1089 + //SDMA0_ULV_CNTL 1090 + #define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0 1091 + #define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d 1092 + #define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e 1093 + #define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f 1094 + #define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL 1095 + #define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L 1096 + #define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L 1097 + #define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L 1098 + //SDMA0_EA_DBIT_ADDR_DATA 1099 + #define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 1100 + #define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL 1101 + //SDMA0_EA_DBIT_ADDR_INDEX 1102 + #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 1103 + #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L 1104 + //SDMA0_GFX_RB_CNTL 1105 + #define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 1106 + #define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 1107 + #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1108 + #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1109 + #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1110 + #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1111 + #define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 1112 + #define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 1113 + #define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1114 + #define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1115 + #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1116 + #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1117 + #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1118 + #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1119 + #define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L 1120 + #define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L 1121 + //SDMA0_GFX_RB_BASE 1122 + #define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 1123 + #define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1124 + //SDMA0_GFX_RB_BASE_HI 1125 + #define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 1126 + #define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1127 + //SDMA0_GFX_RB_RPTR 1128 + #define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0 1129 + #define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1130 + //SDMA0_GFX_RB_RPTR_HI 1131 + #define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 1132 + #define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1133 + //SDMA0_GFX_RB_WPTR 1134 + #define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0 1135 + #define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1136 + //SDMA0_GFX_RB_WPTR_HI 1137 + #define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 1138 + #define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1139 + //SDMA0_GFX_RB_WPTR_POLL_CNTL 1140 + #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1141 + #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1142 + #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1143 + #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1144 + #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1145 + #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1146 + #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1147 + #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1148 + #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1149 + #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1150 + //SDMA0_GFX_RB_RPTR_ADDR_HI 1151 + #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1152 + #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1153 + //SDMA0_GFX_RB_RPTR_ADDR_LO 1154 + #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1155 + #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1156 + //SDMA0_GFX_IB_CNTL 1157 + #define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 1158 + #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1159 + #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1160 + #define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 1161 + #define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1162 + #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1163 + #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1164 + #define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1165 + //SDMA0_GFX_IB_RPTR 1166 + #define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 1167 + #define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1168 + //SDMA0_GFX_IB_OFFSET 1169 + #define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 1170 + #define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1171 + //SDMA0_GFX_IB_BASE_LO 1172 + #define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 1173 + #define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1174 + //SDMA0_GFX_IB_BASE_HI 1175 + #define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 1176 + #define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1177 + //SDMA0_GFX_IB_SIZE 1178 + #define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 1179 + #define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL 1180 + //SDMA0_GFX_SKIP_CNTL 1181 + #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1182 + #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1183 + //SDMA0_GFX_CONTEXT_STATUS 1184 + #define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1185 + #define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 1186 + #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1187 + #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1188 + #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1189 + #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1190 + #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1191 + #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1192 + #define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1193 + #define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1194 + #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1195 + #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1196 + #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1197 + #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1198 + #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1199 + #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1200 + //SDMA0_GFX_DOORBELL 1201 + #define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c 1202 + #define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 1203 + #define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L 1204 + #define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L 1205 + //SDMA0_GFX_CONTEXT_CNTL 1206 + #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 1207 + #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L 1208 + //SDMA0_GFX_STATUS 1209 + #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1210 + #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1211 + #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1212 + #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1213 + //SDMA0_GFX_DOORBELL_LOG 1214 + #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1215 + #define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 1216 + #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1217 + #define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1218 + //SDMA0_GFX_WATERMARK 1219 + #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1220 + #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1221 + #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1222 + #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1223 + //SDMA0_GFX_DOORBELL_OFFSET 1224 + #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1225 + #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1226 + //SDMA0_GFX_CSA_ADDR_LO 1227 + #define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 1228 + #define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1229 + //SDMA0_GFX_CSA_ADDR_HI 1230 + #define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 1231 + #define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1232 + //SDMA0_GFX_IB_SUB_REMAIN 1233 + #define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1234 + #define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1235 + //SDMA0_GFX_PREEMPT 1236 + #define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 1237 + #define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1238 + //SDMA0_GFX_DUMMY_REG 1239 + #define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 1240 + #define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1241 + //SDMA0_GFX_RB_WPTR_POLL_ADDR_HI 1242 + #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1243 + #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1244 + //SDMA0_GFX_RB_WPTR_POLL_ADDR_LO 1245 + #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1246 + #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1247 + //SDMA0_GFX_RB_AQL_CNTL 1248 + #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1249 + #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1250 + #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1251 + #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1252 + #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1253 + #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1254 + //SDMA0_GFX_MINOR_PTR_UPDATE 1255 + #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1256 + #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1257 + //SDMA0_GFX_MIDCMD_DATA0 1258 + #define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 1259 + #define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1260 + //SDMA0_GFX_MIDCMD_DATA1 1261 + #define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 1262 + #define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1263 + //SDMA0_GFX_MIDCMD_DATA2 1264 + #define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 1265 + #define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1266 + //SDMA0_GFX_MIDCMD_DATA3 1267 + #define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 1268 + #define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1269 + //SDMA0_GFX_MIDCMD_DATA4 1270 + #define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 1271 + #define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1272 + //SDMA0_GFX_MIDCMD_DATA5 1273 + #define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 1274 + #define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1275 + //SDMA0_GFX_MIDCMD_DATA6 1276 + #define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 1277 + #define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1278 + //SDMA0_GFX_MIDCMD_DATA7 1279 + #define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 1280 + #define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1281 + //SDMA0_GFX_MIDCMD_DATA8 1282 + #define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 1283 + #define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1284 + //SDMA0_GFX_MIDCMD_CNTL 1285 + #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1286 + #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1287 + #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1288 + #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1289 + #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1290 + #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1291 + #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1292 + #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1293 + //SDMA0_PAGE_RB_CNTL 1294 + #define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 1295 + #define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 1296 + #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1297 + #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1298 + #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1299 + #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1300 + #define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 1301 + #define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 1302 + #define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1303 + #define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1304 + #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1305 + #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1306 + #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1307 + #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1308 + #define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L 1309 + #define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L 1310 + //SDMA0_PAGE_RB_BASE 1311 + #define SDMA0_PAGE_RB_BASE__ADDR__SHIFT 0x0 1312 + #define SDMA0_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1313 + //SDMA0_PAGE_RB_BASE_HI 1314 + #define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 1315 + #define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1316 + //SDMA0_PAGE_RB_RPTR 1317 + #define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 1318 + #define SDMA0_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1319 + //SDMA0_PAGE_RB_RPTR_HI 1320 + #define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 1321 + #define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1322 + //SDMA0_PAGE_RB_WPTR 1323 + #define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 1324 + #define SDMA0_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1325 + //SDMA0_PAGE_RB_WPTR_HI 1326 + #define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 1327 + #define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1328 + //SDMA0_PAGE_RB_WPTR_POLL_CNTL 1329 + #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1330 + #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1331 + #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1332 + #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1333 + #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1334 + #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1335 + #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1336 + #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1337 + #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1338 + #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1339 + //SDMA0_PAGE_RB_RPTR_ADDR_HI 1340 + #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1341 + #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1342 + //SDMA0_PAGE_RB_RPTR_ADDR_LO 1343 + #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1344 + #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1345 + //SDMA0_PAGE_IB_CNTL 1346 + #define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 1347 + #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1348 + #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1349 + #define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 1350 + #define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1351 + #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1352 + #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1353 + #define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1354 + //SDMA0_PAGE_IB_RPTR 1355 + #define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 1356 + #define SDMA0_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1357 + //SDMA0_PAGE_IB_OFFSET 1358 + #define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 1359 + #define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1360 + //SDMA0_PAGE_IB_BASE_LO 1361 + #define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 1362 + #define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1363 + //SDMA0_PAGE_IB_BASE_HI 1364 + #define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 1365 + #define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1366 + //SDMA0_PAGE_IB_SIZE 1367 + #define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT 0x0 1368 + #define SDMA0_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL 1369 + //SDMA0_PAGE_SKIP_CNTL 1370 + #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1371 + #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1372 + //SDMA0_PAGE_CONTEXT_STATUS 1373 + #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1374 + #define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 1375 + #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1376 + #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1377 + #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1378 + #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1379 + #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1380 + #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1381 + #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1382 + #define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1383 + #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1384 + #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1385 + #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1386 + #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1387 + #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1388 + #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1389 + //SDMA0_PAGE_DOORBELL 1390 + #define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT 0x1c 1391 + #define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e 1392 + #define SDMA0_PAGE_DOORBELL__ENABLE_MASK 0x10000000L 1393 + #define SDMA0_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L 1394 + //SDMA0_PAGE_STATUS 1395 + #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1396 + #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1397 + #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1398 + #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1399 + //SDMA0_PAGE_DOORBELL_LOG 1400 + #define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1401 + #define SDMA0_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 1402 + #define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1403 + #define SDMA0_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1404 + //SDMA0_PAGE_WATERMARK 1405 + #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1406 + #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1407 + #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1408 + #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1409 + //SDMA0_PAGE_DOORBELL_OFFSET 1410 + #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1411 + #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1412 + //SDMA0_PAGE_CSA_ADDR_LO 1413 + #define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 1414 + #define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1415 + //SDMA0_PAGE_CSA_ADDR_HI 1416 + #define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 1417 + #define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1418 + //SDMA0_PAGE_IB_SUB_REMAIN 1419 + #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1420 + #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1421 + //SDMA0_PAGE_PREEMPT 1422 + #define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 1423 + #define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1424 + //SDMA0_PAGE_DUMMY_REG 1425 + #define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 1426 + #define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1427 + //SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 1428 + #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1429 + #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1430 + //SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 1431 + #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1432 + #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1433 + //SDMA0_PAGE_RB_AQL_CNTL 1434 + #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1435 + #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1436 + #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1437 + #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1438 + #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1439 + #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1440 + //SDMA0_PAGE_MINOR_PTR_UPDATE 1441 + #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1442 + #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1443 + //SDMA0_PAGE_MIDCMD_DATA0 1444 + #define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 1445 + #define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1446 + //SDMA0_PAGE_MIDCMD_DATA1 1447 + #define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 1448 + #define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1449 + //SDMA0_PAGE_MIDCMD_DATA2 1450 + #define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 1451 + #define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1452 + //SDMA0_PAGE_MIDCMD_DATA3 1453 + #define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 1454 + #define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1455 + //SDMA0_PAGE_MIDCMD_DATA4 1456 + #define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 1457 + #define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1458 + //SDMA0_PAGE_MIDCMD_DATA5 1459 + #define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 1460 + #define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1461 + //SDMA0_PAGE_MIDCMD_DATA6 1462 + #define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 1463 + #define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1464 + //SDMA0_PAGE_MIDCMD_DATA7 1465 + #define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 1466 + #define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1467 + //SDMA0_PAGE_MIDCMD_DATA8 1468 + #define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 1469 + #define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1470 + //SDMA0_PAGE_MIDCMD_CNTL 1471 + #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1472 + #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1473 + #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1474 + #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1475 + #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1476 + #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1477 + #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1478 + #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1479 + //SDMA0_RLC0_RB_CNTL 1480 + #define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 1481 + #define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 1482 + #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1483 + #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1484 + #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1485 + #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1486 + #define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 1487 + #define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 1488 + #define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1489 + #define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1490 + #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1491 + #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1492 + #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1493 + #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1494 + #define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L 1495 + #define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L 1496 + //SDMA0_RLC0_RB_BASE 1497 + #define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 1498 + #define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1499 + //SDMA0_RLC0_RB_BASE_HI 1500 + #define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 1501 + #define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1502 + //SDMA0_RLC0_RB_RPTR 1503 + #define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 1504 + #define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1505 + //SDMA0_RLC0_RB_RPTR_HI 1506 + #define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 1507 + #define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1508 + //SDMA0_RLC0_RB_WPTR 1509 + #define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 1510 + #define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1511 + //SDMA0_RLC0_RB_WPTR_HI 1512 + #define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 1513 + #define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1514 + //SDMA0_RLC0_RB_WPTR_POLL_CNTL 1515 + #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1516 + #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1517 + #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1518 + #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1519 + #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1520 + #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1521 + #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1522 + #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1523 + #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1524 + #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1525 + //SDMA0_RLC0_RB_RPTR_ADDR_HI 1526 + #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1527 + #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1528 + //SDMA0_RLC0_RB_RPTR_ADDR_LO 1529 + #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1530 + #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1531 + //SDMA0_RLC0_IB_CNTL 1532 + #define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 1533 + #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1534 + #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1535 + #define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 1536 + #define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1537 + #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1538 + #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1539 + #define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1540 + //SDMA0_RLC0_IB_RPTR 1541 + #define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 1542 + #define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1543 + //SDMA0_RLC0_IB_OFFSET 1544 + #define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 1545 + #define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1546 + //SDMA0_RLC0_IB_BASE_LO 1547 + #define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 1548 + #define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1549 + //SDMA0_RLC0_IB_BASE_HI 1550 + #define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 1551 + #define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1552 + //SDMA0_RLC0_IB_SIZE 1553 + #define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 1554 + #define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL 1555 + //SDMA0_RLC0_SKIP_CNTL 1556 + #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1557 + #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1558 + //SDMA0_RLC0_CONTEXT_STATUS 1559 + #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1560 + #define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 1561 + #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1562 + #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1563 + #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1564 + #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1565 + #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1566 + #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1567 + #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1568 + #define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1569 + #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1570 + #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1571 + #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1572 + #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1573 + #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1574 + #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1575 + //SDMA0_RLC0_DOORBELL 1576 + #define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 1577 + #define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 1578 + #define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L 1579 + #define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L 1580 + //SDMA0_RLC0_STATUS 1581 + #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1582 + #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1583 + #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1584 + #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1585 + //SDMA0_RLC0_DOORBELL_LOG 1586 + #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1587 + #define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 1588 + #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1589 + #define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1590 + //SDMA0_RLC0_WATERMARK 1591 + #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1592 + #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1593 + #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1594 + #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1595 + //SDMA0_RLC0_DOORBELL_OFFSET 1596 + #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1597 + #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1598 + //SDMA0_RLC0_CSA_ADDR_LO 1599 + #define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 1600 + #define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1601 + //SDMA0_RLC0_CSA_ADDR_HI 1602 + #define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 1603 + #define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1604 + //SDMA0_RLC0_IB_SUB_REMAIN 1605 + #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1606 + #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1607 + //SDMA0_RLC0_PREEMPT 1608 + #define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 1609 + #define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1610 + //SDMA0_RLC0_DUMMY_REG 1611 + #define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 1612 + #define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1613 + //SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 1614 + #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1615 + #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1616 + //SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 1617 + #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1618 + #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1619 + //SDMA0_RLC0_RB_AQL_CNTL 1620 + #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1621 + #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1622 + #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1623 + #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1624 + #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1625 + #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1626 + //SDMA0_RLC0_MINOR_PTR_UPDATE 1627 + #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1628 + #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1629 + //SDMA0_RLC0_MIDCMD_DATA0 1630 + #define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 1631 + #define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1632 + //SDMA0_RLC0_MIDCMD_DATA1 1633 + #define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 1634 + #define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1635 + //SDMA0_RLC0_MIDCMD_DATA2 1636 + #define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 1637 + #define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1638 + //SDMA0_RLC0_MIDCMD_DATA3 1639 + #define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 1640 + #define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1641 + //SDMA0_RLC0_MIDCMD_DATA4 1642 + #define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 1643 + #define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1644 + //SDMA0_RLC0_MIDCMD_DATA5 1645 + #define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 1646 + #define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1647 + //SDMA0_RLC0_MIDCMD_DATA6 1648 + #define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 1649 + #define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1650 + //SDMA0_RLC0_MIDCMD_DATA7 1651 + #define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 1652 + #define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1653 + //SDMA0_RLC0_MIDCMD_DATA8 1654 + #define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 1655 + #define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1656 + //SDMA0_RLC0_MIDCMD_CNTL 1657 + #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1658 + #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1659 + #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1660 + #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1661 + #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1662 + #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1663 + #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1664 + #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1665 + //SDMA0_RLC1_RB_CNTL 1666 + #define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 1667 + #define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 1668 + #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1669 + #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1670 + #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1671 + #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1672 + #define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 1673 + #define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 1674 + #define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1675 + #define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1676 + #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1677 + #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1678 + #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1679 + #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1680 + #define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L 1681 + #define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L 1682 + //SDMA0_RLC1_RB_BASE 1683 + #define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 1684 + #define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1685 + //SDMA0_RLC1_RB_BASE_HI 1686 + #define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 1687 + #define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1688 + //SDMA0_RLC1_RB_RPTR 1689 + #define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 1690 + #define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1691 + //SDMA0_RLC1_RB_RPTR_HI 1692 + #define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 1693 + #define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1694 + //SDMA0_RLC1_RB_WPTR 1695 + #define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 1696 + #define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1697 + //SDMA0_RLC1_RB_WPTR_HI 1698 + #define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 1699 + #define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1700 + //SDMA0_RLC1_RB_WPTR_POLL_CNTL 1701 + #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1702 + #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1703 + #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1704 + #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1705 + #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1706 + #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1707 + #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1708 + #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1709 + #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1710 + #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1711 + //SDMA0_RLC1_RB_RPTR_ADDR_HI 1712 + #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1713 + #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1714 + //SDMA0_RLC1_RB_RPTR_ADDR_LO 1715 + #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1716 + #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1717 + //SDMA0_RLC1_IB_CNTL 1718 + #define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 1719 + #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1720 + #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1721 + #define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 1722 + #define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1723 + #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1724 + #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1725 + #define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1726 + //SDMA0_RLC1_IB_RPTR 1727 + #define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 1728 + #define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1729 + //SDMA0_RLC1_IB_OFFSET 1730 + #define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 1731 + #define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1732 + //SDMA0_RLC1_IB_BASE_LO 1733 + #define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 1734 + #define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1735 + //SDMA0_RLC1_IB_BASE_HI 1736 + #define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 1737 + #define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1738 + //SDMA0_RLC1_IB_SIZE 1739 + #define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 1740 + #define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL 1741 + //SDMA0_RLC1_SKIP_CNTL 1742 + #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1743 + #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1744 + //SDMA0_RLC1_CONTEXT_STATUS 1745 + #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1746 + #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 1747 + #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1748 + #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1749 + #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1750 + #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1751 + #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1752 + #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1753 + #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1754 + #define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1755 + #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1756 + #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1757 + #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1758 + #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1759 + #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1760 + #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1761 + //SDMA0_RLC1_DOORBELL 1762 + #define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 1763 + #define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 1764 + #define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L 1765 + #define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L 1766 + //SDMA0_RLC1_STATUS 1767 + #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1768 + #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1769 + #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1770 + #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1771 + //SDMA0_RLC1_DOORBELL_LOG 1772 + #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1773 + #define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 1774 + #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1775 + #define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1776 + //SDMA0_RLC1_WATERMARK 1777 + #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1778 + #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1779 + #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1780 + #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1781 + //SDMA0_RLC1_DOORBELL_OFFSET 1782 + #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1783 + #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1784 + //SDMA0_RLC1_CSA_ADDR_LO 1785 + #define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 1786 + #define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1787 + //SDMA0_RLC1_CSA_ADDR_HI 1788 + #define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 1789 + #define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1790 + //SDMA0_RLC1_IB_SUB_REMAIN 1791 + #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1792 + #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1793 + //SDMA0_RLC1_PREEMPT 1794 + #define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 1795 + #define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1796 + //SDMA0_RLC1_DUMMY_REG 1797 + #define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 1798 + #define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1799 + //SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 1800 + #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1801 + #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1802 + //SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 1803 + #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1804 + #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1805 + //SDMA0_RLC1_RB_AQL_CNTL 1806 + #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1807 + #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1808 + #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1809 + #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1810 + #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1811 + #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1812 + //SDMA0_RLC1_MINOR_PTR_UPDATE 1813 + #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1814 + #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1815 + //SDMA0_RLC1_MIDCMD_DATA0 1816 + #define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 1817 + #define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1818 + //SDMA0_RLC1_MIDCMD_DATA1 1819 + #define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 1820 + #define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1821 + //SDMA0_RLC1_MIDCMD_DATA2 1822 + #define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 1823 + #define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1824 + //SDMA0_RLC1_MIDCMD_DATA3 1825 + #define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 1826 + #define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1827 + //SDMA0_RLC1_MIDCMD_DATA4 1828 + #define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 1829 + #define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1830 + //SDMA0_RLC1_MIDCMD_DATA5 1831 + #define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 1832 + #define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1833 + //SDMA0_RLC1_MIDCMD_DATA6 1834 + #define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 1835 + #define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1836 + //SDMA0_RLC1_MIDCMD_DATA7 1837 + #define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 1838 + #define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1839 + //SDMA0_RLC1_MIDCMD_DATA8 1840 + #define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 1841 + #define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1842 + //SDMA0_RLC1_MIDCMD_CNTL 1843 + #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1844 + #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1845 + #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1846 + #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1847 + #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1848 + #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1849 + #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1850 + #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1851 + 1852 + #endif
+282
drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_default.h
··· 1 + /* 2 + * Copyright (C) 2017 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included 12 + * in all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 + */ 21 + #ifndef _sdma1_4_0_DEFAULT_HEADER 22 + #define _sdma1_4_0_DEFAULT_HEADER 23 + 24 + 25 + // addressBlock: sdma1_sdma1dec 26 + #define mmSDMA1_UCODE_ADDR_DEFAULT 0x00000000 27 + #define mmSDMA1_UCODE_DATA_DEFAULT 0x00000000 28 + #define mmSDMA1_VM_CNTL_DEFAULT 0x00000000 29 + #define mmSDMA1_VM_CTX_LO_DEFAULT 0x00000000 30 + #define mmSDMA1_VM_CTX_HI_DEFAULT 0x00000000 31 + #define mmSDMA1_ACTIVE_FCN_ID_DEFAULT 0x00000000 32 + #define mmSDMA1_VM_CTX_CNTL_DEFAULT 0x00000000 33 + #define mmSDMA1_VIRT_RESET_REQ_DEFAULT 0x00000000 34 + #define mmSDMA1_VF_ENABLE_DEFAULT 0x00000000 35 + #define mmSDMA1_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f 36 + #define mmSDMA1_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff 37 + #define mmSDMA1_CONTEXT_REG_TYPE2_DEFAULT 0x000003ff 38 + #define mmSDMA1_CONTEXT_REG_TYPE3_DEFAULT 0x00000000 39 + #define mmSDMA1_PUB_REG_TYPE0_DEFAULT 0x3c000000 40 + #define mmSDMA1_PUB_REG_TYPE1_DEFAULT 0x30003882 41 + #define mmSDMA1_PUB_REG_TYPE2_DEFAULT 0x0fc6e880 42 + #define mmSDMA1_PUB_REG_TYPE3_DEFAULT 0x00000000 43 + #define mmSDMA1_MMHUB_CNTL_DEFAULT 0x00000000 44 + #define mmSDMA1_CONTEXT_GROUP_BOUNDARY_DEFAULT 0x00000000 45 + #define mmSDMA1_POWER_CNTL_DEFAULT 0x0003c000 46 + #define mmSDMA1_CLK_CTRL_DEFAULT 0xff000100 47 + #define mmSDMA1_CNTL_DEFAULT 0x00000002 48 + #define mmSDMA1_CHICKEN_BITS_DEFAULT 0x00831f07 49 + #define mmSDMA1_GB_ADDR_CONFIG_DEFAULT 0x00100012 50 + #define mmSDMA1_GB_ADDR_CONFIG_READ_DEFAULT 0x00100012 51 + #define mmSDMA1_RB_RPTR_FETCH_HI_DEFAULT 0x00000000 52 + #define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT 0x00000000 53 + #define mmSDMA1_RB_RPTR_FETCH_DEFAULT 0x00000000 54 + #define mmSDMA1_IB_OFFSET_FETCH_DEFAULT 0x00000000 55 + #define mmSDMA1_PROGRAM_DEFAULT 0x00000000 56 + #define mmSDMA1_STATUS_REG_DEFAULT 0x46dee557 57 + #define mmSDMA1_STATUS1_REG_DEFAULT 0x000003ff 58 + #define mmSDMA1_RD_BURST_CNTL_DEFAULT 0x00000003 59 + #define mmSDMA1_HBM_PAGE_CONFIG_DEFAULT 0x00000000 60 + #define mmSDMA1_UCODE_CHECKSUM_DEFAULT 0x00000000 61 + #define mmSDMA1_F32_CNTL_DEFAULT 0x00000001 62 + #define mmSDMA1_FREEZE_DEFAULT 0x00000000 63 + #define mmSDMA1_PHASE0_QUANTUM_DEFAULT 0x00010002 64 + #define mmSDMA1_PHASE1_QUANTUM_DEFAULT 0x00010002 65 + #define mmSDMA1_EDC_CONFIG_DEFAULT 0x00000002 66 + #define mmSDMA1_BA_THRESHOLD_DEFAULT 0x03ff03ff 67 + #define mmSDMA1_ID_DEFAULT 0x00000001 68 + #define mmSDMA1_VERSION_DEFAULT 0x00000400 69 + #define mmSDMA1_EDC_COUNTER_DEFAULT 0x00000000 70 + #define mmSDMA1_EDC_COUNTER_CLEAR_DEFAULT 0x00000000 71 + #define mmSDMA1_STATUS2_REG_DEFAULT 0x00000001 72 + #define mmSDMA1_ATOMIC_CNTL_DEFAULT 0x00000200 73 + #define mmSDMA1_ATOMIC_PREOP_LO_DEFAULT 0x00000000 74 + #define mmSDMA1_ATOMIC_PREOP_HI_DEFAULT 0x00000000 75 + #define mmSDMA1_UTCL1_CNTL_DEFAULT 0xd0003019 76 + #define mmSDMA1_UTCL1_WATERMK_DEFAULT 0xfffbe1fe 77 + #define mmSDMA1_UTCL1_RD_STATUS_DEFAULT 0x201001ff 78 + #define mmSDMA1_UTCL1_WR_STATUS_DEFAULT 0x503001ff 79 + #define mmSDMA1_UTCL1_INV0_DEFAULT 0x00000600 80 + #define mmSDMA1_UTCL1_INV1_DEFAULT 0x00000000 81 + #define mmSDMA1_UTCL1_INV2_DEFAULT 0x00000000 82 + #define mmSDMA1_UTCL1_RD_XNACK0_DEFAULT 0x00000000 83 + #define mmSDMA1_UTCL1_RD_XNACK1_DEFAULT 0x00000000 84 + #define mmSDMA1_UTCL1_WR_XNACK0_DEFAULT 0x00000000 85 + #define mmSDMA1_UTCL1_WR_XNACK1_DEFAULT 0x00000000 86 + #define mmSDMA1_UTCL1_TIMEOUT_DEFAULT 0x00010001 87 + #define mmSDMA1_UTCL1_PAGE_DEFAULT 0x000003e0 88 + #define mmSDMA1_POWER_CNTL_IDLE_DEFAULT 0x06060200 89 + #define mmSDMA1_RELAX_ORDERING_LUT_DEFAULT 0xc0000006 90 + #define mmSDMA1_CHICKEN_BITS_2_DEFAULT 0x00000005 91 + #define mmSDMA1_STATUS3_REG_DEFAULT 0x00100000 92 + #define mmSDMA1_PHYSICAL_ADDR_LO_DEFAULT 0x00000000 93 + #define mmSDMA1_PHYSICAL_ADDR_HI_DEFAULT 0x00000000 94 + #define mmSDMA1_PHASE2_QUANTUM_DEFAULT 0x00010002 95 + #define mmSDMA1_ERROR_LOG_DEFAULT 0x0000000f 96 + #define mmSDMA1_PUB_DUMMY_REG0_DEFAULT 0x00000000 97 + #define mmSDMA1_PUB_DUMMY_REG1_DEFAULT 0x00000000 98 + #define mmSDMA1_PUB_DUMMY_REG2_DEFAULT 0x00000000 99 + #define mmSDMA1_PUB_DUMMY_REG3_DEFAULT 0x00000000 100 + #define mmSDMA1_F32_COUNTER_DEFAULT 0x00000000 101 + #define mmSDMA1_UNBREAKABLE_DEFAULT 0x00000000 102 + #define mmSDMA1_PERFMON_CNTL_DEFAULT 0x000ff7fd 103 + #define mmSDMA1_PERFCOUNTER0_RESULT_DEFAULT 0x00000000 104 + #define mmSDMA1_PERFCOUNTER1_RESULT_DEFAULT 0x00000000 105 + #define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_DEFAULT 0x00640000 106 + #define mmSDMA1_CRD_CNTL_DEFAULT 0x000085c0 107 + #define mmSDMA1_MMHUB_TRUSTLVL_DEFAULT 0x00000000 108 + #define mmSDMA1_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000 109 + #define mmSDMA1_ULV_CNTL_DEFAULT 0x00000000 110 + #define mmSDMA1_EA_DBIT_ADDR_DATA_DEFAULT 0x00000000 111 + #define mmSDMA1_EA_DBIT_ADDR_INDEX_DEFAULT 0x00000000 112 + #define mmSDMA1_GFX_RB_CNTL_DEFAULT 0x00040000 113 + #define mmSDMA1_GFX_RB_BASE_DEFAULT 0x00000000 114 + #define mmSDMA1_GFX_RB_BASE_HI_DEFAULT 0x00000000 115 + #define mmSDMA1_GFX_RB_RPTR_DEFAULT 0x00000000 116 + #define mmSDMA1_GFX_RB_RPTR_HI_DEFAULT 0x00000000 117 + #define mmSDMA1_GFX_RB_WPTR_DEFAULT 0x00000000 118 + #define mmSDMA1_GFX_RB_WPTR_HI_DEFAULT 0x00000000 119 + #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 120 + #define mmSDMA1_GFX_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 121 + #define mmSDMA1_GFX_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 122 + #define mmSDMA1_GFX_IB_CNTL_DEFAULT 0x00000100 123 + #define mmSDMA1_GFX_IB_RPTR_DEFAULT 0x00000000 124 + #define mmSDMA1_GFX_IB_OFFSET_DEFAULT 0x00000000 125 + #define mmSDMA1_GFX_IB_BASE_LO_DEFAULT 0x00000000 126 + #define mmSDMA1_GFX_IB_BASE_HI_DEFAULT 0x00000000 127 + #define mmSDMA1_GFX_IB_SIZE_DEFAULT 0x00000000 128 + #define mmSDMA1_GFX_SKIP_CNTL_DEFAULT 0x00000000 129 + #define mmSDMA1_GFX_CONTEXT_STATUS_DEFAULT 0x00000005 130 + #define mmSDMA1_GFX_DOORBELL_DEFAULT 0x00000000 131 + #define mmSDMA1_GFX_CONTEXT_CNTL_DEFAULT 0x00000000 132 + #define mmSDMA1_GFX_STATUS_DEFAULT 0x00000000 133 + #define mmSDMA1_GFX_DOORBELL_LOG_DEFAULT 0x00000000 134 + #define mmSDMA1_GFX_WATERMARK_DEFAULT 0x00000000 135 + #define mmSDMA1_GFX_DOORBELL_OFFSET_DEFAULT 0x00000000 136 + #define mmSDMA1_GFX_CSA_ADDR_LO_DEFAULT 0x00000000 137 + #define mmSDMA1_GFX_CSA_ADDR_HI_DEFAULT 0x00000000 138 + #define mmSDMA1_GFX_IB_SUB_REMAIN_DEFAULT 0x00000000 139 + #define mmSDMA1_GFX_PREEMPT_DEFAULT 0x00000000 140 + #define mmSDMA1_GFX_DUMMY_REG_DEFAULT 0x0000000f 141 + #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 142 + #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 143 + #define mmSDMA1_GFX_RB_AQL_CNTL_DEFAULT 0x00004000 144 + #define mmSDMA1_GFX_MINOR_PTR_UPDATE_DEFAULT 0x00000000 145 + #define mmSDMA1_GFX_MIDCMD_DATA0_DEFAULT 0x00000000 146 + #define mmSDMA1_GFX_MIDCMD_DATA1_DEFAULT 0x00000000 147 + #define mmSDMA1_GFX_MIDCMD_DATA2_DEFAULT 0x00000000 148 + #define mmSDMA1_GFX_MIDCMD_DATA3_DEFAULT 0x00000000 149 + #define mmSDMA1_GFX_MIDCMD_DATA4_DEFAULT 0x00000000 150 + #define mmSDMA1_GFX_MIDCMD_DATA5_DEFAULT 0x00000000 151 + #define mmSDMA1_GFX_MIDCMD_DATA6_DEFAULT 0x00000000 152 + #define mmSDMA1_GFX_MIDCMD_DATA7_DEFAULT 0x00000000 153 + #define mmSDMA1_GFX_MIDCMD_DATA8_DEFAULT 0x00000000 154 + #define mmSDMA1_GFX_MIDCMD_CNTL_DEFAULT 0x00000000 155 + #define mmSDMA1_PAGE_RB_CNTL_DEFAULT 0x00040000 156 + #define mmSDMA1_PAGE_RB_BASE_DEFAULT 0x00000000 157 + #define mmSDMA1_PAGE_RB_BASE_HI_DEFAULT 0x00000000 158 + #define mmSDMA1_PAGE_RB_RPTR_DEFAULT 0x00000000 159 + #define mmSDMA1_PAGE_RB_RPTR_HI_DEFAULT 0x00000000 160 + #define mmSDMA1_PAGE_RB_WPTR_DEFAULT 0x00000000 161 + #define mmSDMA1_PAGE_RB_WPTR_HI_DEFAULT 0x00000000 162 + #define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 163 + #define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 164 + #define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 165 + #define mmSDMA1_PAGE_IB_CNTL_DEFAULT 0x00000100 166 + #define mmSDMA1_PAGE_IB_RPTR_DEFAULT 0x00000000 167 + #define mmSDMA1_PAGE_IB_OFFSET_DEFAULT 0x00000000 168 + #define mmSDMA1_PAGE_IB_BASE_LO_DEFAULT 0x00000000 169 + #define mmSDMA1_PAGE_IB_BASE_HI_DEFAULT 0x00000000 170 + #define mmSDMA1_PAGE_IB_SIZE_DEFAULT 0x00000000 171 + #define mmSDMA1_PAGE_SKIP_CNTL_DEFAULT 0x00000000 172 + #define mmSDMA1_PAGE_CONTEXT_STATUS_DEFAULT 0x00000004 173 + #define mmSDMA1_PAGE_DOORBELL_DEFAULT 0x00000000 174 + #define mmSDMA1_PAGE_STATUS_DEFAULT 0x00000000 175 + #define mmSDMA1_PAGE_DOORBELL_LOG_DEFAULT 0x00000000 176 + #define mmSDMA1_PAGE_WATERMARK_DEFAULT 0x00000000 177 + #define mmSDMA1_PAGE_DOORBELL_OFFSET_DEFAULT 0x00000000 178 + #define mmSDMA1_PAGE_CSA_ADDR_LO_DEFAULT 0x00000000 179 + #define mmSDMA1_PAGE_CSA_ADDR_HI_DEFAULT 0x00000000 180 + #define mmSDMA1_PAGE_IB_SUB_REMAIN_DEFAULT 0x00000000 181 + #define mmSDMA1_PAGE_PREEMPT_DEFAULT 0x00000000 182 + #define mmSDMA1_PAGE_DUMMY_REG_DEFAULT 0x0000000f 183 + #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 184 + #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 185 + #define mmSDMA1_PAGE_RB_AQL_CNTL_DEFAULT 0x00004000 186 + #define mmSDMA1_PAGE_MINOR_PTR_UPDATE_DEFAULT 0x00000000 187 + #define mmSDMA1_PAGE_MIDCMD_DATA0_DEFAULT 0x00000000 188 + #define mmSDMA1_PAGE_MIDCMD_DATA1_DEFAULT 0x00000000 189 + #define mmSDMA1_PAGE_MIDCMD_DATA2_DEFAULT 0x00000000 190 + #define mmSDMA1_PAGE_MIDCMD_DATA3_DEFAULT 0x00000000 191 + #define mmSDMA1_PAGE_MIDCMD_DATA4_DEFAULT 0x00000000 192 + #define mmSDMA1_PAGE_MIDCMD_DATA5_DEFAULT 0x00000000 193 + #define mmSDMA1_PAGE_MIDCMD_DATA6_DEFAULT 0x00000000 194 + #define mmSDMA1_PAGE_MIDCMD_DATA7_DEFAULT 0x00000000 195 + #define mmSDMA1_PAGE_MIDCMD_DATA8_DEFAULT 0x00000000 196 + #define mmSDMA1_PAGE_MIDCMD_CNTL_DEFAULT 0x00000000 197 + #define mmSDMA1_RLC0_RB_CNTL_DEFAULT 0x00040000 198 + #define mmSDMA1_RLC0_RB_BASE_DEFAULT 0x00000000 199 + #define mmSDMA1_RLC0_RB_BASE_HI_DEFAULT 0x00000000 200 + #define mmSDMA1_RLC0_RB_RPTR_DEFAULT 0x00000000 201 + #define mmSDMA1_RLC0_RB_RPTR_HI_DEFAULT 0x00000000 202 + #define mmSDMA1_RLC0_RB_WPTR_DEFAULT 0x00000000 203 + #define mmSDMA1_RLC0_RB_WPTR_HI_DEFAULT 0x00000000 204 + #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 205 + #define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 206 + #define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 207 + #define mmSDMA1_RLC0_IB_CNTL_DEFAULT 0x00000100 208 + #define mmSDMA1_RLC0_IB_RPTR_DEFAULT 0x00000000 209 + #define mmSDMA1_RLC0_IB_OFFSET_DEFAULT 0x00000000 210 + #define mmSDMA1_RLC0_IB_BASE_LO_DEFAULT 0x00000000 211 + #define mmSDMA1_RLC0_IB_BASE_HI_DEFAULT 0x00000000 212 + #define mmSDMA1_RLC0_IB_SIZE_DEFAULT 0x00000000 213 + #define mmSDMA1_RLC0_SKIP_CNTL_DEFAULT 0x00000000 214 + #define mmSDMA1_RLC0_CONTEXT_STATUS_DEFAULT 0x00000004 215 + #define mmSDMA1_RLC0_DOORBELL_DEFAULT 0x00000000 216 + #define mmSDMA1_RLC0_STATUS_DEFAULT 0x00000000 217 + #define mmSDMA1_RLC0_DOORBELL_LOG_DEFAULT 0x00000000 218 + #define mmSDMA1_RLC0_WATERMARK_DEFAULT 0x00000000 219 + #define mmSDMA1_RLC0_DOORBELL_OFFSET_DEFAULT 0x00000000 220 + #define mmSDMA1_RLC0_CSA_ADDR_LO_DEFAULT 0x00000000 221 + #define mmSDMA1_RLC0_CSA_ADDR_HI_DEFAULT 0x00000000 222 + #define mmSDMA1_RLC0_IB_SUB_REMAIN_DEFAULT 0x00000000 223 + #define mmSDMA1_RLC0_PREEMPT_DEFAULT 0x00000000 224 + #define mmSDMA1_RLC0_DUMMY_REG_DEFAULT 0x0000000f 225 + #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 226 + #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 227 + #define mmSDMA1_RLC0_RB_AQL_CNTL_DEFAULT 0x00004000 228 + #define mmSDMA1_RLC0_MINOR_PTR_UPDATE_DEFAULT 0x00000000 229 + #define mmSDMA1_RLC0_MIDCMD_DATA0_DEFAULT 0x00000000 230 + #define mmSDMA1_RLC0_MIDCMD_DATA1_DEFAULT 0x00000000 231 + #define mmSDMA1_RLC0_MIDCMD_DATA2_DEFAULT 0x00000000 232 + #define mmSDMA1_RLC0_MIDCMD_DATA3_DEFAULT 0x00000000 233 + #define mmSDMA1_RLC0_MIDCMD_DATA4_DEFAULT 0x00000000 234 + #define mmSDMA1_RLC0_MIDCMD_DATA5_DEFAULT 0x00000000 235 + #define mmSDMA1_RLC0_MIDCMD_DATA6_DEFAULT 0x00000000 236 + #define mmSDMA1_RLC0_MIDCMD_DATA7_DEFAULT 0x00000000 237 + #define mmSDMA1_RLC0_MIDCMD_DATA8_DEFAULT 0x00000000 238 + #define mmSDMA1_RLC0_MIDCMD_CNTL_DEFAULT 0x00000000 239 + #define mmSDMA1_RLC1_RB_CNTL_DEFAULT 0x00040000 240 + #define mmSDMA1_RLC1_RB_BASE_DEFAULT 0x00000000 241 + #define mmSDMA1_RLC1_RB_BASE_HI_DEFAULT 0x00000000 242 + #define mmSDMA1_RLC1_RB_RPTR_DEFAULT 0x00000000 243 + #define mmSDMA1_RLC1_RB_RPTR_HI_DEFAULT 0x00000000 244 + #define mmSDMA1_RLC1_RB_WPTR_DEFAULT 0x00000000 245 + #define mmSDMA1_RLC1_RB_WPTR_HI_DEFAULT 0x00000000 246 + #define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 247 + #define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 248 + #define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 249 + #define mmSDMA1_RLC1_IB_CNTL_DEFAULT 0x00000100 250 + #define mmSDMA1_RLC1_IB_RPTR_DEFAULT 0x00000000 251 + #define mmSDMA1_RLC1_IB_OFFSET_DEFAULT 0x00000000 252 + #define mmSDMA1_RLC1_IB_BASE_LO_DEFAULT 0x00000000 253 + #define mmSDMA1_RLC1_IB_BASE_HI_DEFAULT 0x00000000 254 + #define mmSDMA1_RLC1_IB_SIZE_DEFAULT 0x00000000 255 + #define mmSDMA1_RLC1_SKIP_CNTL_DEFAULT 0x00000000 256 + #define mmSDMA1_RLC1_CONTEXT_STATUS_DEFAULT 0x00000004 257 + #define mmSDMA1_RLC1_DOORBELL_DEFAULT 0x00000000 258 + #define mmSDMA1_RLC1_STATUS_DEFAULT 0x00000000 259 + #define mmSDMA1_RLC1_DOORBELL_LOG_DEFAULT 0x00000000 260 + #define mmSDMA1_RLC1_WATERMARK_DEFAULT 0x00000000 261 + #define mmSDMA1_RLC1_DOORBELL_OFFSET_DEFAULT 0x00000000 262 + #define mmSDMA1_RLC1_CSA_ADDR_LO_DEFAULT 0x00000000 263 + #define mmSDMA1_RLC1_CSA_ADDR_HI_DEFAULT 0x00000000 264 + #define mmSDMA1_RLC1_IB_SUB_REMAIN_DEFAULT 0x00000000 265 + #define mmSDMA1_RLC1_PREEMPT_DEFAULT 0x00000000 266 + #define mmSDMA1_RLC1_DUMMY_REG_DEFAULT 0x0000000f 267 + #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 268 + #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 269 + #define mmSDMA1_RLC1_RB_AQL_CNTL_DEFAULT 0x00004000 270 + #define mmSDMA1_RLC1_MINOR_PTR_UPDATE_DEFAULT 0x00000000 271 + #define mmSDMA1_RLC1_MIDCMD_DATA0_DEFAULT 0x00000000 272 + #define mmSDMA1_RLC1_MIDCMD_DATA1_DEFAULT 0x00000000 273 + #define mmSDMA1_RLC1_MIDCMD_DATA2_DEFAULT 0x00000000 274 + #define mmSDMA1_RLC1_MIDCMD_DATA3_DEFAULT 0x00000000 275 + #define mmSDMA1_RLC1_MIDCMD_DATA4_DEFAULT 0x00000000 276 + #define mmSDMA1_RLC1_MIDCMD_DATA5_DEFAULT 0x00000000 277 + #define mmSDMA1_RLC1_MIDCMD_DATA6_DEFAULT 0x00000000 278 + #define mmSDMA1_RLC1_MIDCMD_DATA7_DEFAULT 0x00000000 279 + #define mmSDMA1_RLC1_MIDCMD_DATA8_DEFAULT 0x00000000 280 + #define mmSDMA1_RLC1_MIDCMD_CNTL_DEFAULT 0x00000000 281 + 282 + #endif
+539
drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_offset.h
··· 1 + /* 2 + * Copyright (C) 2017 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included 12 + * in all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 + */ 21 + #ifndef _sdma1_4_0_OFFSET_HEADER 22 + #define _sdma1_4_0_OFFSET_HEADER 23 + 24 + 25 + 26 + // addressBlock: sdma1_sdma1dec 27 + // base address: 0x5180 28 + #define mmSDMA1_UCODE_ADDR 0x0000 29 + #define mmSDMA1_UCODE_ADDR_BASE_IDX 0 30 + #define mmSDMA1_UCODE_DATA 0x0001 31 + #define mmSDMA1_UCODE_DATA_BASE_IDX 0 32 + #define mmSDMA1_VM_CNTL 0x0004 33 + #define mmSDMA1_VM_CNTL_BASE_IDX 0 34 + #define mmSDMA1_VM_CTX_LO 0x0005 35 + #define mmSDMA1_VM_CTX_LO_BASE_IDX 0 36 + #define mmSDMA1_VM_CTX_HI 0x0006 37 + #define mmSDMA1_VM_CTX_HI_BASE_IDX 0 38 + #define mmSDMA1_ACTIVE_FCN_ID 0x0007 39 + #define mmSDMA1_ACTIVE_FCN_ID_BASE_IDX 0 40 + #define mmSDMA1_VM_CTX_CNTL 0x0008 41 + #define mmSDMA1_VM_CTX_CNTL_BASE_IDX 0 42 + #define mmSDMA1_VIRT_RESET_REQ 0x0009 43 + #define mmSDMA1_VIRT_RESET_REQ_BASE_IDX 0 44 + #define mmSDMA1_VF_ENABLE 0x000a 45 + #define mmSDMA1_VF_ENABLE_BASE_IDX 0 46 + #define mmSDMA1_CONTEXT_REG_TYPE0 0x000b 47 + #define mmSDMA1_CONTEXT_REG_TYPE0_BASE_IDX 0 48 + #define mmSDMA1_CONTEXT_REG_TYPE1 0x000c 49 + #define mmSDMA1_CONTEXT_REG_TYPE1_BASE_IDX 0 50 + #define mmSDMA1_CONTEXT_REG_TYPE2 0x000d 51 + #define mmSDMA1_CONTEXT_REG_TYPE2_BASE_IDX 0 52 + #define mmSDMA1_CONTEXT_REG_TYPE3 0x000e 53 + #define mmSDMA1_CONTEXT_REG_TYPE3_BASE_IDX 0 54 + #define mmSDMA1_PUB_REG_TYPE0 0x000f 55 + #define mmSDMA1_PUB_REG_TYPE0_BASE_IDX 0 56 + #define mmSDMA1_PUB_REG_TYPE1 0x0010 57 + #define mmSDMA1_PUB_REG_TYPE1_BASE_IDX 0 58 + #define mmSDMA1_PUB_REG_TYPE2 0x0011 59 + #define mmSDMA1_PUB_REG_TYPE2_BASE_IDX 0 60 + #define mmSDMA1_PUB_REG_TYPE3 0x0012 61 + #define mmSDMA1_PUB_REG_TYPE3_BASE_IDX 0 62 + #define mmSDMA1_MMHUB_CNTL 0x0013 63 + #define mmSDMA1_MMHUB_CNTL_BASE_IDX 0 64 + #define mmSDMA1_CONTEXT_GROUP_BOUNDARY 0x0019 65 + #define mmSDMA1_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 66 + #define mmSDMA1_POWER_CNTL 0x001a 67 + #define mmSDMA1_POWER_CNTL_BASE_IDX 0 68 + #define mmSDMA1_CLK_CTRL 0x001b 69 + #define mmSDMA1_CLK_CTRL_BASE_IDX 0 70 + #define mmSDMA1_CNTL 0x001c 71 + #define mmSDMA1_CNTL_BASE_IDX 0 72 + #define mmSDMA1_CHICKEN_BITS 0x001d 73 + #define mmSDMA1_CHICKEN_BITS_BASE_IDX 0 74 + #define mmSDMA1_GB_ADDR_CONFIG 0x001e 75 + #define mmSDMA1_GB_ADDR_CONFIG_BASE_IDX 0 76 + #define mmSDMA1_GB_ADDR_CONFIG_READ 0x001f 77 + #define mmSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX 0 78 + #define mmSDMA1_RB_RPTR_FETCH_HI 0x0020 79 + #define mmSDMA1_RB_RPTR_FETCH_HI_BASE_IDX 0 80 + #define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 81 + #define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 82 + #define mmSDMA1_RB_RPTR_FETCH 0x0022 83 + #define mmSDMA1_RB_RPTR_FETCH_BASE_IDX 0 84 + #define mmSDMA1_IB_OFFSET_FETCH 0x0023 85 + #define mmSDMA1_IB_OFFSET_FETCH_BASE_IDX 0 86 + #define mmSDMA1_PROGRAM 0x0024 87 + #define mmSDMA1_PROGRAM_BASE_IDX 0 88 + #define mmSDMA1_STATUS_REG 0x0025 89 + #define mmSDMA1_STATUS_REG_BASE_IDX 0 90 + #define mmSDMA1_STATUS1_REG 0x0026 91 + #define mmSDMA1_STATUS1_REG_BASE_IDX 0 92 + #define mmSDMA1_RD_BURST_CNTL 0x0027 93 + #define mmSDMA1_RD_BURST_CNTL_BASE_IDX 0 94 + #define mmSDMA1_HBM_PAGE_CONFIG 0x0028 95 + #define mmSDMA1_HBM_PAGE_CONFIG_BASE_IDX 0 96 + #define mmSDMA1_UCODE_CHECKSUM 0x0029 97 + #define mmSDMA1_UCODE_CHECKSUM_BASE_IDX 0 98 + #define mmSDMA1_F32_CNTL 0x002a 99 + #define mmSDMA1_F32_CNTL_BASE_IDX 0 100 + #define mmSDMA1_FREEZE 0x002b 101 + #define mmSDMA1_FREEZE_BASE_IDX 0 102 + #define mmSDMA1_PHASE0_QUANTUM 0x002c 103 + #define mmSDMA1_PHASE0_QUANTUM_BASE_IDX 0 104 + #define mmSDMA1_PHASE1_QUANTUM 0x002d 105 + #define mmSDMA1_PHASE1_QUANTUM_BASE_IDX 0 106 + #define mmSDMA1_EDC_CONFIG 0x0032 107 + #define mmSDMA1_EDC_CONFIG_BASE_IDX 0 108 + #define mmSDMA1_BA_THRESHOLD 0x0033 109 + #define mmSDMA1_BA_THRESHOLD_BASE_IDX 0 110 + #define mmSDMA1_ID 0x0034 111 + #define mmSDMA1_ID_BASE_IDX 0 112 + #define mmSDMA1_VERSION 0x0035 113 + #define mmSDMA1_VERSION_BASE_IDX 0 114 + #define mmSDMA1_EDC_COUNTER 0x0036 115 + #define mmSDMA1_EDC_COUNTER_BASE_IDX 0 116 + #define mmSDMA1_EDC_COUNTER_CLEAR 0x0037 117 + #define mmSDMA1_EDC_COUNTER_CLEAR_BASE_IDX 0 118 + #define mmSDMA1_STATUS2_REG 0x0038 119 + #define mmSDMA1_STATUS2_REG_BASE_IDX 0 120 + #define mmSDMA1_ATOMIC_CNTL 0x0039 121 + #define mmSDMA1_ATOMIC_CNTL_BASE_IDX 0 122 + #define mmSDMA1_ATOMIC_PREOP_LO 0x003a 123 + #define mmSDMA1_ATOMIC_PREOP_LO_BASE_IDX 0 124 + #define mmSDMA1_ATOMIC_PREOP_HI 0x003b 125 + #define mmSDMA1_ATOMIC_PREOP_HI_BASE_IDX 0 126 + #define mmSDMA1_UTCL1_CNTL 0x003c 127 + #define mmSDMA1_UTCL1_CNTL_BASE_IDX 0 128 + #define mmSDMA1_UTCL1_WATERMK 0x003d 129 + #define mmSDMA1_UTCL1_WATERMK_BASE_IDX 0 130 + #define mmSDMA1_UTCL1_RD_STATUS 0x003e 131 + #define mmSDMA1_UTCL1_RD_STATUS_BASE_IDX 0 132 + #define mmSDMA1_UTCL1_WR_STATUS 0x003f 133 + #define mmSDMA1_UTCL1_WR_STATUS_BASE_IDX 0 134 + #define mmSDMA1_UTCL1_INV0 0x0040 135 + #define mmSDMA1_UTCL1_INV0_BASE_IDX 0 136 + #define mmSDMA1_UTCL1_INV1 0x0041 137 + #define mmSDMA1_UTCL1_INV1_BASE_IDX 0 138 + #define mmSDMA1_UTCL1_INV2 0x0042 139 + #define mmSDMA1_UTCL1_INV2_BASE_IDX 0 140 + #define mmSDMA1_UTCL1_RD_XNACK0 0x0043 141 + #define mmSDMA1_UTCL1_RD_XNACK0_BASE_IDX 0 142 + #define mmSDMA1_UTCL1_RD_XNACK1 0x0044 143 + #define mmSDMA1_UTCL1_RD_XNACK1_BASE_IDX 0 144 + #define mmSDMA1_UTCL1_WR_XNACK0 0x0045 145 + #define mmSDMA1_UTCL1_WR_XNACK0_BASE_IDX 0 146 + #define mmSDMA1_UTCL1_WR_XNACK1 0x0046 147 + #define mmSDMA1_UTCL1_WR_XNACK1_BASE_IDX 0 148 + #define mmSDMA1_UTCL1_TIMEOUT 0x0047 149 + #define mmSDMA1_UTCL1_TIMEOUT_BASE_IDX 0 150 + #define mmSDMA1_UTCL1_PAGE 0x0048 151 + #define mmSDMA1_UTCL1_PAGE_BASE_IDX 0 152 + #define mmSDMA1_POWER_CNTL_IDLE 0x0049 153 + #define mmSDMA1_POWER_CNTL_IDLE_BASE_IDX 0 154 + #define mmSDMA1_RELAX_ORDERING_LUT 0x004a 155 + #define mmSDMA1_RELAX_ORDERING_LUT_BASE_IDX 0 156 + #define mmSDMA1_CHICKEN_BITS_2 0x004b 157 + #define mmSDMA1_CHICKEN_BITS_2_BASE_IDX 0 158 + #define mmSDMA1_STATUS3_REG 0x004c 159 + #define mmSDMA1_STATUS3_REG_BASE_IDX 0 160 + #define mmSDMA1_PHYSICAL_ADDR_LO 0x004d 161 + #define mmSDMA1_PHYSICAL_ADDR_LO_BASE_IDX 0 162 + #define mmSDMA1_PHYSICAL_ADDR_HI 0x004e 163 + #define mmSDMA1_PHYSICAL_ADDR_HI_BASE_IDX 0 164 + #define mmSDMA1_PHASE2_QUANTUM 0x004f 165 + #define mmSDMA1_PHASE2_QUANTUM_BASE_IDX 0 166 + #define mmSDMA1_ERROR_LOG 0x0050 167 + #define mmSDMA1_ERROR_LOG_BASE_IDX 0 168 + #define mmSDMA1_PUB_DUMMY_REG0 0x0051 169 + #define mmSDMA1_PUB_DUMMY_REG0_BASE_IDX 0 170 + #define mmSDMA1_PUB_DUMMY_REG1 0x0052 171 + #define mmSDMA1_PUB_DUMMY_REG1_BASE_IDX 0 172 + #define mmSDMA1_PUB_DUMMY_REG2 0x0053 173 + #define mmSDMA1_PUB_DUMMY_REG2_BASE_IDX 0 174 + #define mmSDMA1_PUB_DUMMY_REG3 0x0054 175 + #define mmSDMA1_PUB_DUMMY_REG3_BASE_IDX 0 176 + #define mmSDMA1_F32_COUNTER 0x0055 177 + #define mmSDMA1_F32_COUNTER_BASE_IDX 0 178 + #define mmSDMA1_UNBREAKABLE 0x0056 179 + #define mmSDMA1_UNBREAKABLE_BASE_IDX 0 180 + #define mmSDMA1_PERFMON_CNTL 0x0057 181 + #define mmSDMA1_PERFMON_CNTL_BASE_IDX 0 182 + #define mmSDMA1_PERFCOUNTER0_RESULT 0x0058 183 + #define mmSDMA1_PERFCOUNTER0_RESULT_BASE_IDX 0 184 + #define mmSDMA1_PERFCOUNTER1_RESULT 0x0059 185 + #define mmSDMA1_PERFCOUNTER1_RESULT_BASE_IDX 0 186 + #define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE 0x005a 187 + #define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0 188 + #define mmSDMA1_CRD_CNTL 0x005b 189 + #define mmSDMA1_CRD_CNTL_BASE_IDX 0 190 + #define mmSDMA1_MMHUB_TRUSTLVL 0x005c 191 + #define mmSDMA1_MMHUB_TRUSTLVL_BASE_IDX 0 192 + #define mmSDMA1_GPU_IOV_VIOLATION_LOG 0x005d 193 + #define mmSDMA1_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 194 + #define mmSDMA1_ULV_CNTL 0x005e 195 + #define mmSDMA1_ULV_CNTL_BASE_IDX 0 196 + #define mmSDMA1_EA_DBIT_ADDR_DATA 0x0060 197 + #define mmSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX 0 198 + #define mmSDMA1_EA_DBIT_ADDR_INDEX 0x0061 199 + #define mmSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX 0 200 + #define mmSDMA1_GFX_RB_CNTL 0x0080 201 + #define mmSDMA1_GFX_RB_CNTL_BASE_IDX 0 202 + #define mmSDMA1_GFX_RB_BASE 0x0081 203 + #define mmSDMA1_GFX_RB_BASE_BASE_IDX 0 204 + #define mmSDMA1_GFX_RB_BASE_HI 0x0082 205 + #define mmSDMA1_GFX_RB_BASE_HI_BASE_IDX 0 206 + #define mmSDMA1_GFX_RB_RPTR 0x0083 207 + #define mmSDMA1_GFX_RB_RPTR_BASE_IDX 0 208 + #define mmSDMA1_GFX_RB_RPTR_HI 0x0084 209 + #define mmSDMA1_GFX_RB_RPTR_HI_BASE_IDX 0 210 + #define mmSDMA1_GFX_RB_WPTR 0x0085 211 + #define mmSDMA1_GFX_RB_WPTR_BASE_IDX 0 212 + #define mmSDMA1_GFX_RB_WPTR_HI 0x0086 213 + #define mmSDMA1_GFX_RB_WPTR_HI_BASE_IDX 0 214 + #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x0087 215 + #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 216 + #define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x0088 217 + #define mmSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 218 + #define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x0089 219 + #define mmSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 220 + #define mmSDMA1_GFX_IB_CNTL 0x008a 221 + #define mmSDMA1_GFX_IB_CNTL_BASE_IDX 0 222 + #define mmSDMA1_GFX_IB_RPTR 0x008b 223 + #define mmSDMA1_GFX_IB_RPTR_BASE_IDX 0 224 + #define mmSDMA1_GFX_IB_OFFSET 0x008c 225 + #define mmSDMA1_GFX_IB_OFFSET_BASE_IDX 0 226 + #define mmSDMA1_GFX_IB_BASE_LO 0x008d 227 + #define mmSDMA1_GFX_IB_BASE_LO_BASE_IDX 0 228 + #define mmSDMA1_GFX_IB_BASE_HI 0x008e 229 + #define mmSDMA1_GFX_IB_BASE_HI_BASE_IDX 0 230 + #define mmSDMA1_GFX_IB_SIZE 0x008f 231 + #define mmSDMA1_GFX_IB_SIZE_BASE_IDX 0 232 + #define mmSDMA1_GFX_SKIP_CNTL 0x0090 233 + #define mmSDMA1_GFX_SKIP_CNTL_BASE_IDX 0 234 + #define mmSDMA1_GFX_CONTEXT_STATUS 0x0091 235 + #define mmSDMA1_GFX_CONTEXT_STATUS_BASE_IDX 0 236 + #define mmSDMA1_GFX_DOORBELL 0x0092 237 + #define mmSDMA1_GFX_DOORBELL_BASE_IDX 0 238 + #define mmSDMA1_GFX_CONTEXT_CNTL 0x0093 239 + #define mmSDMA1_GFX_CONTEXT_CNTL_BASE_IDX 0 240 + #define mmSDMA1_GFX_STATUS 0x00a8 241 + #define mmSDMA1_GFX_STATUS_BASE_IDX 0 242 + #define mmSDMA1_GFX_DOORBELL_LOG 0x00a9 243 + #define mmSDMA1_GFX_DOORBELL_LOG_BASE_IDX 0 244 + #define mmSDMA1_GFX_WATERMARK 0x00aa 245 + #define mmSDMA1_GFX_WATERMARK_BASE_IDX 0 246 + #define mmSDMA1_GFX_DOORBELL_OFFSET 0x00ab 247 + #define mmSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX 0 248 + #define mmSDMA1_GFX_CSA_ADDR_LO 0x00ac 249 + #define mmSDMA1_GFX_CSA_ADDR_LO_BASE_IDX 0 250 + #define mmSDMA1_GFX_CSA_ADDR_HI 0x00ad 251 + #define mmSDMA1_GFX_CSA_ADDR_HI_BASE_IDX 0 252 + #define mmSDMA1_GFX_IB_SUB_REMAIN 0x00af 253 + #define mmSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX 0 254 + #define mmSDMA1_GFX_PREEMPT 0x00b0 255 + #define mmSDMA1_GFX_PREEMPT_BASE_IDX 0 256 + #define mmSDMA1_GFX_DUMMY_REG 0x00b1 257 + #define mmSDMA1_GFX_DUMMY_REG_BASE_IDX 0 258 + #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 259 + #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 260 + #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 261 + #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 262 + #define mmSDMA1_GFX_RB_AQL_CNTL 0x00b4 263 + #define mmSDMA1_GFX_RB_AQL_CNTL_BASE_IDX 0 264 + #define mmSDMA1_GFX_MINOR_PTR_UPDATE 0x00b5 265 + #define mmSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 266 + #define mmSDMA1_GFX_MIDCMD_DATA0 0x00c0 267 + #define mmSDMA1_GFX_MIDCMD_DATA0_BASE_IDX 0 268 + #define mmSDMA1_GFX_MIDCMD_DATA1 0x00c1 269 + #define mmSDMA1_GFX_MIDCMD_DATA1_BASE_IDX 0 270 + #define mmSDMA1_GFX_MIDCMD_DATA2 0x00c2 271 + #define mmSDMA1_GFX_MIDCMD_DATA2_BASE_IDX 0 272 + #define mmSDMA1_GFX_MIDCMD_DATA3 0x00c3 273 + #define mmSDMA1_GFX_MIDCMD_DATA3_BASE_IDX 0 274 + #define mmSDMA1_GFX_MIDCMD_DATA4 0x00c4 275 + #define mmSDMA1_GFX_MIDCMD_DATA4_BASE_IDX 0 276 + #define mmSDMA1_GFX_MIDCMD_DATA5 0x00c5 277 + #define mmSDMA1_GFX_MIDCMD_DATA5_BASE_IDX 0 278 + #define mmSDMA1_GFX_MIDCMD_DATA6 0x00c6 279 + #define mmSDMA1_GFX_MIDCMD_DATA6_BASE_IDX 0 280 + #define mmSDMA1_GFX_MIDCMD_DATA7 0x00c7 281 + #define mmSDMA1_GFX_MIDCMD_DATA7_BASE_IDX 0 282 + #define mmSDMA1_GFX_MIDCMD_DATA8 0x00c8 283 + #define mmSDMA1_GFX_MIDCMD_DATA8_BASE_IDX 0 284 + #define mmSDMA1_GFX_MIDCMD_CNTL 0x00c9 285 + #define mmSDMA1_GFX_MIDCMD_CNTL_BASE_IDX 0 286 + #define mmSDMA1_PAGE_RB_CNTL 0x00e0 287 + #define mmSDMA1_PAGE_RB_CNTL_BASE_IDX 0 288 + #define mmSDMA1_PAGE_RB_BASE 0x00e1 289 + #define mmSDMA1_PAGE_RB_BASE_BASE_IDX 0 290 + #define mmSDMA1_PAGE_RB_BASE_HI 0x00e2 291 + #define mmSDMA1_PAGE_RB_BASE_HI_BASE_IDX 0 292 + #define mmSDMA1_PAGE_RB_RPTR 0x00e3 293 + #define mmSDMA1_PAGE_RB_RPTR_BASE_IDX 0 294 + #define mmSDMA1_PAGE_RB_RPTR_HI 0x00e4 295 + #define mmSDMA1_PAGE_RB_RPTR_HI_BASE_IDX 0 296 + #define mmSDMA1_PAGE_RB_WPTR 0x00e5 297 + #define mmSDMA1_PAGE_RB_WPTR_BASE_IDX 0 298 + #define mmSDMA1_PAGE_RB_WPTR_HI 0x00e6 299 + #define mmSDMA1_PAGE_RB_WPTR_HI_BASE_IDX 0 300 + #define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL 0x00e7 301 + #define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 302 + #define mmSDMA1_PAGE_RB_RPTR_ADDR_HI 0x00e8 303 + #define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 304 + #define mmSDMA1_PAGE_RB_RPTR_ADDR_LO 0x00e9 305 + #define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 306 + #define mmSDMA1_PAGE_IB_CNTL 0x00ea 307 + #define mmSDMA1_PAGE_IB_CNTL_BASE_IDX 0 308 + #define mmSDMA1_PAGE_IB_RPTR 0x00eb 309 + #define mmSDMA1_PAGE_IB_RPTR_BASE_IDX 0 310 + #define mmSDMA1_PAGE_IB_OFFSET 0x00ec 311 + #define mmSDMA1_PAGE_IB_OFFSET_BASE_IDX 0 312 + #define mmSDMA1_PAGE_IB_BASE_LO 0x00ed 313 + #define mmSDMA1_PAGE_IB_BASE_LO_BASE_IDX 0 314 + #define mmSDMA1_PAGE_IB_BASE_HI 0x00ee 315 + #define mmSDMA1_PAGE_IB_BASE_HI_BASE_IDX 0 316 + #define mmSDMA1_PAGE_IB_SIZE 0x00ef 317 + #define mmSDMA1_PAGE_IB_SIZE_BASE_IDX 0 318 + #define mmSDMA1_PAGE_SKIP_CNTL 0x00f0 319 + #define mmSDMA1_PAGE_SKIP_CNTL_BASE_IDX 0 320 + #define mmSDMA1_PAGE_CONTEXT_STATUS 0x00f1 321 + #define mmSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX 0 322 + #define mmSDMA1_PAGE_DOORBELL 0x00f2 323 + #define mmSDMA1_PAGE_DOORBELL_BASE_IDX 0 324 + #define mmSDMA1_PAGE_STATUS 0x0108 325 + #define mmSDMA1_PAGE_STATUS_BASE_IDX 0 326 + #define mmSDMA1_PAGE_DOORBELL_LOG 0x0109 327 + #define mmSDMA1_PAGE_DOORBELL_LOG_BASE_IDX 0 328 + #define mmSDMA1_PAGE_WATERMARK 0x010a 329 + #define mmSDMA1_PAGE_WATERMARK_BASE_IDX 0 330 + #define mmSDMA1_PAGE_DOORBELL_OFFSET 0x010b 331 + #define mmSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX 0 332 + #define mmSDMA1_PAGE_CSA_ADDR_LO 0x010c 333 + #define mmSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX 0 334 + #define mmSDMA1_PAGE_CSA_ADDR_HI 0x010d 335 + #define mmSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX 0 336 + #define mmSDMA1_PAGE_IB_SUB_REMAIN 0x010f 337 + #define mmSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX 0 338 + #define mmSDMA1_PAGE_PREEMPT 0x0110 339 + #define mmSDMA1_PAGE_PREEMPT_BASE_IDX 0 340 + #define mmSDMA1_PAGE_DUMMY_REG 0x0111 341 + #define mmSDMA1_PAGE_DUMMY_REG_BASE_IDX 0 342 + #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI 0x0112 343 + #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 344 + #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO 0x0113 345 + #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 346 + #define mmSDMA1_PAGE_RB_AQL_CNTL 0x0114 347 + #define mmSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX 0 348 + #define mmSDMA1_PAGE_MINOR_PTR_UPDATE 0x0115 349 + #define mmSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 350 + #define mmSDMA1_PAGE_MIDCMD_DATA0 0x0120 351 + #define mmSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX 0 352 + #define mmSDMA1_PAGE_MIDCMD_DATA1 0x0121 353 + #define mmSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX 0 354 + #define mmSDMA1_PAGE_MIDCMD_DATA2 0x0122 355 + #define mmSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX 0 356 + #define mmSDMA1_PAGE_MIDCMD_DATA3 0x0123 357 + #define mmSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX 0 358 + #define mmSDMA1_PAGE_MIDCMD_DATA4 0x0124 359 + #define mmSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX 0 360 + #define mmSDMA1_PAGE_MIDCMD_DATA5 0x0125 361 + #define mmSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX 0 362 + #define mmSDMA1_PAGE_MIDCMD_DATA6 0x0126 363 + #define mmSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX 0 364 + #define mmSDMA1_PAGE_MIDCMD_DATA7 0x0127 365 + #define mmSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX 0 366 + #define mmSDMA1_PAGE_MIDCMD_DATA8 0x0128 367 + #define mmSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX 0 368 + #define mmSDMA1_PAGE_MIDCMD_CNTL 0x0129 369 + #define mmSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX 0 370 + #define mmSDMA1_RLC0_RB_CNTL 0x0140 371 + #define mmSDMA1_RLC0_RB_CNTL_BASE_IDX 0 372 + #define mmSDMA1_RLC0_RB_BASE 0x0141 373 + #define mmSDMA1_RLC0_RB_BASE_BASE_IDX 0 374 + #define mmSDMA1_RLC0_RB_BASE_HI 0x0142 375 + #define mmSDMA1_RLC0_RB_BASE_HI_BASE_IDX 0 376 + #define mmSDMA1_RLC0_RB_RPTR 0x0143 377 + #define mmSDMA1_RLC0_RB_RPTR_BASE_IDX 0 378 + #define mmSDMA1_RLC0_RB_RPTR_HI 0x0144 379 + #define mmSDMA1_RLC0_RB_RPTR_HI_BASE_IDX 0 380 + #define mmSDMA1_RLC0_RB_WPTR 0x0145 381 + #define mmSDMA1_RLC0_RB_WPTR_BASE_IDX 0 382 + #define mmSDMA1_RLC0_RB_WPTR_HI 0x0146 383 + #define mmSDMA1_RLC0_RB_WPTR_HI_BASE_IDX 0 384 + #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x0147 385 + #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 386 + #define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x0148 387 + #define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 388 + #define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x0149 389 + #define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 390 + #define mmSDMA1_RLC0_IB_CNTL 0x014a 391 + #define mmSDMA1_RLC0_IB_CNTL_BASE_IDX 0 392 + #define mmSDMA1_RLC0_IB_RPTR 0x014b 393 + #define mmSDMA1_RLC0_IB_RPTR_BASE_IDX 0 394 + #define mmSDMA1_RLC0_IB_OFFSET 0x014c 395 + #define mmSDMA1_RLC0_IB_OFFSET_BASE_IDX 0 396 + #define mmSDMA1_RLC0_IB_BASE_LO 0x014d 397 + #define mmSDMA1_RLC0_IB_BASE_LO_BASE_IDX 0 398 + #define mmSDMA1_RLC0_IB_BASE_HI 0x014e 399 + #define mmSDMA1_RLC0_IB_BASE_HI_BASE_IDX 0 400 + #define mmSDMA1_RLC0_IB_SIZE 0x014f 401 + #define mmSDMA1_RLC0_IB_SIZE_BASE_IDX 0 402 + #define mmSDMA1_RLC0_SKIP_CNTL 0x0150 403 + #define mmSDMA1_RLC0_SKIP_CNTL_BASE_IDX 0 404 + #define mmSDMA1_RLC0_CONTEXT_STATUS 0x0151 405 + #define mmSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX 0 406 + #define mmSDMA1_RLC0_DOORBELL 0x0152 407 + #define mmSDMA1_RLC0_DOORBELL_BASE_IDX 0 408 + #define mmSDMA1_RLC0_STATUS 0x0168 409 + #define mmSDMA1_RLC0_STATUS_BASE_IDX 0 410 + #define mmSDMA1_RLC0_DOORBELL_LOG 0x0169 411 + #define mmSDMA1_RLC0_DOORBELL_LOG_BASE_IDX 0 412 + #define mmSDMA1_RLC0_WATERMARK 0x016a 413 + #define mmSDMA1_RLC0_WATERMARK_BASE_IDX 0 414 + #define mmSDMA1_RLC0_DOORBELL_OFFSET 0x016b 415 + #define mmSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX 0 416 + #define mmSDMA1_RLC0_CSA_ADDR_LO 0x016c 417 + #define mmSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX 0 418 + #define mmSDMA1_RLC0_CSA_ADDR_HI 0x016d 419 + #define mmSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX 0 420 + #define mmSDMA1_RLC0_IB_SUB_REMAIN 0x016f 421 + #define mmSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX 0 422 + #define mmSDMA1_RLC0_PREEMPT 0x0170 423 + #define mmSDMA1_RLC0_PREEMPT_BASE_IDX 0 424 + #define mmSDMA1_RLC0_DUMMY_REG 0x0171 425 + #define mmSDMA1_RLC0_DUMMY_REG_BASE_IDX 0 426 + #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x0172 427 + #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 428 + #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x0173 429 + #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 430 + #define mmSDMA1_RLC0_RB_AQL_CNTL 0x0174 431 + #define mmSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX 0 432 + #define mmSDMA1_RLC0_MINOR_PTR_UPDATE 0x0175 433 + #define mmSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 434 + #define mmSDMA1_RLC0_MIDCMD_DATA0 0x0180 435 + #define mmSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX 0 436 + #define mmSDMA1_RLC0_MIDCMD_DATA1 0x0181 437 + #define mmSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX 0 438 + #define mmSDMA1_RLC0_MIDCMD_DATA2 0x0182 439 + #define mmSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX 0 440 + #define mmSDMA1_RLC0_MIDCMD_DATA3 0x0183 441 + #define mmSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX 0 442 + #define mmSDMA1_RLC0_MIDCMD_DATA4 0x0184 443 + #define mmSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX 0 444 + #define mmSDMA1_RLC0_MIDCMD_DATA5 0x0185 445 + #define mmSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX 0 446 + #define mmSDMA1_RLC0_MIDCMD_DATA6 0x0186 447 + #define mmSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX 0 448 + #define mmSDMA1_RLC0_MIDCMD_DATA7 0x0187 449 + #define mmSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX 0 450 + #define mmSDMA1_RLC0_MIDCMD_DATA8 0x0188 451 + #define mmSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX 0 452 + #define mmSDMA1_RLC0_MIDCMD_CNTL 0x0189 453 + #define mmSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX 0 454 + #define mmSDMA1_RLC1_RB_CNTL 0x01a0 455 + #define mmSDMA1_RLC1_RB_CNTL_BASE_IDX 0 456 + #define mmSDMA1_RLC1_RB_BASE 0x01a1 457 + #define mmSDMA1_RLC1_RB_BASE_BASE_IDX 0 458 + #define mmSDMA1_RLC1_RB_BASE_HI 0x01a2 459 + #define mmSDMA1_RLC1_RB_BASE_HI_BASE_IDX 0 460 + #define mmSDMA1_RLC1_RB_RPTR 0x01a3 461 + #define mmSDMA1_RLC1_RB_RPTR_BASE_IDX 0 462 + #define mmSDMA1_RLC1_RB_RPTR_HI 0x01a4 463 + #define mmSDMA1_RLC1_RB_RPTR_HI_BASE_IDX 0 464 + #define mmSDMA1_RLC1_RB_WPTR 0x01a5 465 + #define mmSDMA1_RLC1_RB_WPTR_BASE_IDX 0 466 + #define mmSDMA1_RLC1_RB_WPTR_HI 0x01a6 467 + #define mmSDMA1_RLC1_RB_WPTR_HI_BASE_IDX 0 468 + #define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x01a7 469 + #define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 470 + #define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x01a8 471 + #define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 472 + #define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x01a9 473 + #define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 474 + #define mmSDMA1_RLC1_IB_CNTL 0x01aa 475 + #define mmSDMA1_RLC1_IB_CNTL_BASE_IDX 0 476 + #define mmSDMA1_RLC1_IB_RPTR 0x01ab 477 + #define mmSDMA1_RLC1_IB_RPTR_BASE_IDX 0 478 + #define mmSDMA1_RLC1_IB_OFFSET 0x01ac 479 + #define mmSDMA1_RLC1_IB_OFFSET_BASE_IDX 0 480 + #define mmSDMA1_RLC1_IB_BASE_LO 0x01ad 481 + #define mmSDMA1_RLC1_IB_BASE_LO_BASE_IDX 0 482 + #define mmSDMA1_RLC1_IB_BASE_HI 0x01ae 483 + #define mmSDMA1_RLC1_IB_BASE_HI_BASE_IDX 0 484 + #define mmSDMA1_RLC1_IB_SIZE 0x01af 485 + #define mmSDMA1_RLC1_IB_SIZE_BASE_IDX 0 486 + #define mmSDMA1_RLC1_SKIP_CNTL 0x01b0 487 + #define mmSDMA1_RLC1_SKIP_CNTL_BASE_IDX 0 488 + #define mmSDMA1_RLC1_CONTEXT_STATUS 0x01b1 489 + #define mmSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX 0 490 + #define mmSDMA1_RLC1_DOORBELL 0x01b2 491 + #define mmSDMA1_RLC1_DOORBELL_BASE_IDX 0 492 + #define mmSDMA1_RLC1_STATUS 0x01c8 493 + #define mmSDMA1_RLC1_STATUS_BASE_IDX 0 494 + #define mmSDMA1_RLC1_DOORBELL_LOG 0x01c9 495 + #define mmSDMA1_RLC1_DOORBELL_LOG_BASE_IDX 0 496 + #define mmSDMA1_RLC1_WATERMARK 0x01ca 497 + #define mmSDMA1_RLC1_WATERMARK_BASE_IDX 0 498 + #define mmSDMA1_RLC1_DOORBELL_OFFSET 0x01cb 499 + #define mmSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX 0 500 + #define mmSDMA1_RLC1_CSA_ADDR_LO 0x01cc 501 + #define mmSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX 0 502 + #define mmSDMA1_RLC1_CSA_ADDR_HI 0x01cd 503 + #define mmSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX 0 504 + #define mmSDMA1_RLC1_IB_SUB_REMAIN 0x01cf 505 + #define mmSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX 0 506 + #define mmSDMA1_RLC1_PREEMPT 0x01d0 507 + #define mmSDMA1_RLC1_PREEMPT_BASE_IDX 0 508 + #define mmSDMA1_RLC1_DUMMY_REG 0x01d1 509 + #define mmSDMA1_RLC1_DUMMY_REG_BASE_IDX 0 510 + #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x01d2 511 + #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 512 + #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x01d3 513 + #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 514 + #define mmSDMA1_RLC1_RB_AQL_CNTL 0x01d4 515 + #define mmSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX 0 516 + #define mmSDMA1_RLC1_MINOR_PTR_UPDATE 0x01d5 517 + #define mmSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 518 + #define mmSDMA1_RLC1_MIDCMD_DATA0 0x01e0 519 + #define mmSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX 0 520 + #define mmSDMA1_RLC1_MIDCMD_DATA1 0x01e1 521 + #define mmSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX 0 522 + #define mmSDMA1_RLC1_MIDCMD_DATA2 0x01e2 523 + #define mmSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX 0 524 + #define mmSDMA1_RLC1_MIDCMD_DATA3 0x01e3 525 + #define mmSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX 0 526 + #define mmSDMA1_RLC1_MIDCMD_DATA4 0x01e4 527 + #define mmSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX 0 528 + #define mmSDMA1_RLC1_MIDCMD_DATA5 0x01e5 529 + #define mmSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX 0 530 + #define mmSDMA1_RLC1_MIDCMD_DATA6 0x01e6 531 + #define mmSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX 0 532 + #define mmSDMA1_RLC1_MIDCMD_DATA7 0x01e7 533 + #define mmSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX 0 534 + #define mmSDMA1_RLC1_MIDCMD_DATA8 0x01e8 535 + #define mmSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX 0 536 + #define mmSDMA1_RLC1_MIDCMD_CNTL 0x01e9 537 + #define mmSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX 0 538 + 539 + #endif
+1810
drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h
··· 1 + /* 2 + * Copyright (C) 2017 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included 12 + * in all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 + */ 21 + #ifndef _sdma1_4_0_SH_MASK_HEADER 22 + #define _sdma1_4_0_SH_MASK_HEADER 23 + 24 + 25 + // addressBlock: sdma1_sdma1dec 26 + //SDMA1_UCODE_ADDR 27 + #define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0 28 + #define SDMA1_UCODE_ADDR__VALUE_MASK 0x00001FFFL 29 + //SDMA1_UCODE_DATA 30 + #define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0 31 + #define SDMA1_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 32 + //SDMA1_VM_CNTL 33 + #define SDMA1_VM_CNTL__CMD__SHIFT 0x0 34 + #define SDMA1_VM_CNTL__CMD_MASK 0x0000000FL 35 + //SDMA1_VM_CTX_LO 36 + #define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2 37 + #define SDMA1_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL 38 + //SDMA1_VM_CTX_HI 39 + #define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0 40 + #define SDMA1_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL 41 + //SDMA1_ACTIVE_FCN_ID 42 + #define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 43 + #define SDMA1_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 44 + #define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x1f 45 + #define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 46 + #define SDMA1_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L 47 + #define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000L 48 + //SDMA1_VM_CTX_CNTL 49 + #define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x0 50 + #define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x4 51 + #define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x00000001L 52 + #define SDMA1_VM_CTX_CNTL__VMID_MASK 0x000000F0L 53 + //SDMA1_VIRT_RESET_REQ 54 + #define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x0 55 + #define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x1f 56 + #define SDMA1_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 57 + #define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000L 58 + //SDMA1_VF_ENABLE 59 + #define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0 60 + #define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x00000001L 61 + //SDMA1_CONTEXT_REG_TYPE0 62 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT 0x0 63 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1 64 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2 65 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT 0x3 66 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI__SHIFT 0x4 67 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT 0x5 68 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI__SHIFT 0x6 69 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 70 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 71 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 72 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa 73 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT 0xb 74 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT 0xc 75 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT 0xd 76 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT 0xe 77 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT 0xf 78 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT 0x10 79 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT 0x11 80 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT 0x12 81 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT 0x13 82 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x00000001L 83 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x00000002L 84 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK 0x00000004L 85 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK 0x00000008L 86 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI_MASK 0x00000010L 87 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK 0x00000020L 88 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI_MASK 0x00000040L 89 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L 90 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L 91 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L 92 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK 0x00000400L 93 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK 0x00000800L 94 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK 0x00001000L 95 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK 0x00002000L 96 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK 0x00004000L 97 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK 0x00008000L 98 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK 0x00010000L 99 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK 0x00020000L 100 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK 0x00040000L 101 + #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK 0x00080000L 102 + //SDMA1_CONTEXT_REG_TYPE1 103 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS__SHIFT 0x8 104 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT 0x9 105 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa 106 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET__SHIFT 0xb 107 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT 0xc 108 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT 0xd 109 + #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe 110 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT 0xf 111 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT 0x10 112 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT 0x11 113 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 114 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 115 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL__SHIFT 0x14 116 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 117 + #define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 118 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS_MASK 0x00000100L 119 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK 0x00000200L 120 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK 0x00000400L 121 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET_MASK 0x00000800L 122 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK 0x00001000L 123 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK 0x00002000L 124 + #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L 125 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK 0x00008000L 126 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK 0x00010000L 127 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK 0x00020000L 128 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L 129 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L 130 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL_MASK 0x00100000L 131 + #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L 132 + #define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L 133 + //SDMA1_CONTEXT_REG_TYPE2 134 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT 0x0 135 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1 136 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2 137 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT 0x3 138 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT 0x4 139 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT 0x5 140 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6__SHIFT 0x6 141 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7__SHIFT 0x7 142 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8__SHIFT 0x8 143 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT 0x9 144 + #define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa 145 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x00000001L 146 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x00000002L 147 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK 0x00000004L 148 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK 0x00000008L 149 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK 0x00000010L 150 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK 0x00000020L 151 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6_MASK 0x00000040L 152 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7_MASK 0x00000080L 153 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8_MASK 0x00000100L 154 + #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK 0x00000200L 155 + #define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L 156 + //SDMA1_CONTEXT_REG_TYPE3 157 + #define SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 158 + #define SDMA1_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL 159 + //SDMA1_PUB_REG_TYPE0 160 + #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x0 161 + #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1 162 + #define SDMA1_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 163 + #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL__SHIFT 0x4 164 + #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO__SHIFT 0x5 165 + #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI__SHIFT 0x6 166 + #define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID__SHIFT 0x7 167 + #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL__SHIFT 0x8 168 + #define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ__SHIFT 0x9 169 + #define SDMA1_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa 170 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0__SHIFT 0xb 171 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1__SHIFT 0xc 172 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2__SHIFT 0xd 173 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3__SHIFT 0xe 174 + #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0__SHIFT 0xf 175 + #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1__SHIFT 0x10 176 + #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2__SHIFT 0x11 177 + #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3__SHIFT 0x12 178 + #define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL__SHIFT 0x13 179 + #define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 180 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 181 + #define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x1a 182 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT 0x1b 183 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT 0x1c 184 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x1d 185 + #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG__SHIFT 0x1e 186 + #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ__SHIFT 0x1f 187 + #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x00000001L 188 + #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x00000002L 189 + #define SDMA1_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L 190 + #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL_MASK 0x00000010L 191 + #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO_MASK 0x00000020L 192 + #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI_MASK 0x00000040L 193 + #define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID_MASK 0x00000080L 194 + #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL_MASK 0x00000100L 195 + #define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ_MASK 0x00000200L 196 + #define SDMA1_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L 197 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0_MASK 0x00000800L 198 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1_MASK 0x00001000L 199 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2_MASK 0x00002000L 200 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3_MASK 0x00004000L 201 + #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0_MASK 0x00008000L 202 + #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1_MASK 0x00010000L 203 + #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2_MASK 0x00020000L 204 + #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3_MASK 0x00040000L 205 + #define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL_MASK 0x00080000L 206 + #define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L 207 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L 208 + #define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK 0x04000000L 209 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK 0x08000000L 210 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK 0x10000000L 211 + #define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK 0x20000000L 212 + #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_MASK 0x40000000L 213 + #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ_MASK 0x80000000L 214 + //SDMA1_PUB_REG_TYPE1 215 + #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI__SHIFT 0x0 216 + #define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 217 + #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH__SHIFT 0x2 218 + #define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH__SHIFT 0x3 219 + #define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM__SHIFT 0x4 220 + #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG__SHIFT 0x5 221 + #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG__SHIFT 0x6 222 + #define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL__SHIFT 0x7 223 + #define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG__SHIFT 0x8 224 + #define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM__SHIFT 0x9 225 + #define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL__SHIFT 0xa 226 + #define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE__SHIFT 0xb 227 + #define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM__SHIFT 0xc 228 + #define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM__SHIFT 0xd 229 + #define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe 230 + #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf 231 + #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 232 + #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 233 + #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG__SHIFT 0x12 234 + #define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD__SHIFT 0x13 235 + #define SDMA1_PUB_REG_TYPE1__SDMA1_ID__SHIFT 0x14 236 + #define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION__SHIFT 0x15 237 + #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER__SHIFT 0x16 238 + #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR__SHIFT 0x17 239 + #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT 0x18 240 + #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT 0x19 241 + #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT 0x1a 242 + #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT 0x1b 243 + #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL__SHIFT 0x1c 244 + #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK__SHIFT 0x1d 245 + #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS__SHIFT 0x1e 246 + #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS__SHIFT 0x1f 247 + #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI_MASK 0x00000001L 248 + #define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L 249 + #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_MASK 0x00000004L 250 + #define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH_MASK 0x00000008L 251 + #define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM_MASK 0x00000010L 252 + #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG_MASK 0x00000020L 253 + #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG_MASK 0x00000040L 254 + #define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL_MASK 0x00000080L 255 + #define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG_MASK 0x00000100L 256 + #define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM_MASK 0x00000200L 257 + #define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL_MASK 0x00000400L 258 + #define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE_MASK 0x00000800L 259 + #define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM_MASK 0x00001000L 260 + #define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM_MASK 0x00002000L 261 + #define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L 262 + #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L 263 + #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L 264 + #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L 265 + #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG_MASK 0x00040000L 266 + #define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD_MASK 0x00080000L 267 + #define SDMA1_PUB_REG_TYPE1__SDMA1_ID_MASK 0x00100000L 268 + #define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION_MASK 0x00200000L 269 + #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_MASK 0x00400000L 270 + #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR_MASK 0x00800000L 271 + #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK 0x01000000L 272 + #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK 0x02000000L 273 + #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK 0x04000000L 274 + #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK 0x08000000L 275 + #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL_MASK 0x10000000L 276 + #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK_MASK 0x20000000L 277 + #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS_MASK 0x40000000L 278 + #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS_MASK 0x80000000L 279 + //SDMA1_PUB_REG_TYPE2 280 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0__SHIFT 0x0 281 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1__SHIFT 0x1 282 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2__SHIFT 0x2 283 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0__SHIFT 0x3 284 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1__SHIFT 0x4 285 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0__SHIFT 0x5 286 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1__SHIFT 0x6 287 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT__SHIFT 0x7 288 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE__SHIFT 0x8 289 + #define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE__SHIFT 0x9 290 + #define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT__SHIFT 0xa 291 + #define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2__SHIFT 0xb 292 + #define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG__SHIFT 0xc 293 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO__SHIFT 0xd 294 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI__SHIFT 0xe 295 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM__SHIFT 0xf 296 + #define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG__SHIFT 0x10 297 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0__SHIFT 0x11 298 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1__SHIFT 0x12 299 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2__SHIFT 0x13 300 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3__SHIFT 0x14 301 + #define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER__SHIFT 0x15 302 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UNBREAKABLE__SHIFT 0x16 303 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL__SHIFT 0x17 304 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT__SHIFT 0x18 305 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT__SHIFT 0x19 306 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a 307 + #define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL__SHIFT 0x1b 308 + #define SDMA1_PUB_REG_TYPE2__SDMA1_MMHUB_TRUSTLVL__SHIFT 0x1c 309 + #define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d 310 + #define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL__SHIFT 0x1e 311 + #define SDMA1_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f 312 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0_MASK 0x00000001L 313 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1_MASK 0x00000002L 314 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2_MASK 0x00000004L 315 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0_MASK 0x00000008L 316 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1_MASK 0x00000010L 317 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0_MASK 0x00000020L 318 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1_MASK 0x00000040L 319 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT_MASK 0x00000080L 320 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE_MASK 0x00000100L 321 + #define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE_MASK 0x00000200L 322 + #define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT_MASK 0x00000400L 323 + #define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2_MASK 0x00000800L 324 + #define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG_MASK 0x00001000L 325 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO_MASK 0x00002000L 326 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI_MASK 0x00004000L 327 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM_MASK 0x00008000L 328 + #define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG_MASK 0x00010000L 329 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0_MASK 0x00020000L 330 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1_MASK 0x00040000L 331 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2_MASK 0x00080000L 332 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3_MASK 0x00100000L 333 + #define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER_MASK 0x00200000L 334 + #define SDMA1_PUB_REG_TYPE2__SDMA1_UNBREAKABLE_MASK 0x00400000L 335 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL_MASK 0x00800000L 336 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT_MASK 0x01000000L 337 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT_MASK 0x02000000L 338 + #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L 339 + #define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL_MASK 0x08000000L 340 + #define SDMA1_PUB_REG_TYPE2__SDMA1_MMHUB_TRUSTLVL_MASK 0x10000000L 341 + #define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L 342 + #define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL_MASK 0x40000000L 343 + #define SDMA1_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L 344 + //SDMA1_PUB_REG_TYPE3 345 + #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA__SHIFT 0x0 346 + #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX__SHIFT 0x1 347 + #define SDMA1_PUB_REG_TYPE3__RESERVED__SHIFT 0x2 348 + #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA_MASK 0x00000001L 349 + #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX_MASK 0x00000002L 350 + #define SDMA1_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL 351 + //SDMA1_MMHUB_CNTL 352 + #define SDMA1_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 353 + #define SDMA1_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL 354 + //SDMA1_CONTEXT_GROUP_BOUNDARY 355 + #define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 356 + #define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL 357 + //SDMA1_POWER_CNTL 358 + #define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 359 + #define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 360 + #define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 361 + #define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 362 + #define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 363 + #define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L 364 + #define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L 365 + #define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L 366 + #define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L 367 + #define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L 368 + //SDMA1_CLK_CTRL 369 + #define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0 370 + #define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 371 + #define SDMA1_CLK_CTRL__RESERVED__SHIFT 0xc 372 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 373 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 374 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 375 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 376 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 377 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 378 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 379 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 380 + #define SDMA1_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 381 + #define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 382 + #define SDMA1_CLK_CTRL__RESERVED_MASK 0x00FFF000L 383 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 384 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 385 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 386 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 387 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 388 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 389 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 390 + #define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 391 + //SDMA1_CNTL 392 + #define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0 393 + #define SDMA1_CNTL__UTC_L1_ENABLE__SHIFT 0x1 394 + #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 395 + #define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 396 + #define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 397 + #define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 398 + #define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 399 + #define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 400 + #define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 401 + #define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 402 + #define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 403 + #define SDMA1_CNTL__TRAP_ENABLE_MASK 0x00000001L 404 + #define SDMA1_CNTL__UTC_L1_ENABLE_MASK 0x00000002L 405 + #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L 406 + #define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L 407 + #define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L 408 + #define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L 409 + #define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 410 + #define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L 411 + #define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L 412 + #define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L 413 + #define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L 414 + //SDMA1_CHICKEN_BITS 415 + #define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 416 + #define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 417 + #define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 418 + #define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 419 + #define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 420 + #define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 421 + #define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 422 + #define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 423 + #define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 424 + #define SDMA1_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 425 + #define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a 426 + #define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c 427 + #define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e 428 + #define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L 429 + #define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L 430 + #define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L 431 + #define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L 432 + #define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L 433 + #define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L 434 + #define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L 435 + #define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L 436 + #define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L 437 + #define SDMA1_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L 438 + #define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L 439 + #define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L 440 + #define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L 441 + //SDMA1_GB_ADDR_CONFIG 442 + #define SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 443 + #define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 444 + #define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 445 + #define SDMA1_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 446 + #define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 447 + #define SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 448 + #define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 449 + #define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 450 + #define SDMA1_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 451 + #define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 452 + //SDMA1_GB_ADDR_CONFIG_READ 453 + #define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 454 + #define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 455 + #define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 456 + #define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc 457 + #define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 458 + #define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 459 + #define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 460 + #define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 461 + #define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L 462 + #define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 463 + //SDMA1_RB_RPTR_FETCH_HI 464 + #define SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 465 + #define SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 466 + //SDMA1_SEM_WAIT_FAIL_TIMER_CNTL 467 + #define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 468 + #define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL 469 + //SDMA1_RB_RPTR_FETCH 470 + #define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 471 + #define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 472 + //SDMA1_IB_OFFSET_FETCH 473 + #define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 474 + #define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 475 + //SDMA1_PROGRAM 476 + #define SDMA1_PROGRAM__STREAM__SHIFT 0x0 477 + #define SDMA1_PROGRAM__STREAM_MASK 0xFFFFFFFFL 478 + //SDMA1_STATUS_REG 479 + #define SDMA1_STATUS_REG__IDLE__SHIFT 0x0 480 + #define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1 481 + #define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2 482 + #define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3 483 + #define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 484 + #define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 485 + #define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 486 + #define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 487 + #define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 488 + #define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9 489 + #define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa 490 + #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 491 + #define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc 492 + #define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 493 + #define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe 494 + #define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 495 + #define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 496 + #define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 497 + #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 498 + #define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 499 + #define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 500 + #define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 501 + #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 502 + #define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 503 + #define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a 504 + #define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 505 + #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 506 + #define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e 507 + #define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 508 + #define SDMA1_STATUS_REG__IDLE_MASK 0x00000001L 509 + #define SDMA1_STATUS_REG__REG_IDLE_MASK 0x00000002L 510 + #define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x00000004L 511 + #define SDMA1_STATUS_REG__RB_FULL_MASK 0x00000008L 512 + #define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L 513 + #define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L 514 + #define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L 515 + #define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L 516 + #define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L 517 + #define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x00000200L 518 + #define SDMA1_STATUS_REG__EX_IDLE_MASK 0x00000400L 519 + #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L 520 + #define SDMA1_STATUS_REG__PACKET_READY_MASK 0x00001000L 521 + #define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L 522 + #define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x00004000L 523 + #define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L 524 + #define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L 525 + #define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L 526 + #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L 527 + #define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L 528 + #define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L 529 + #define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L 530 + #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L 531 + #define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L 532 + #define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x04000000L 533 + #define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L 534 + #define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L 535 + #define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000L 536 + #define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L 537 + //SDMA1_STATUS1_REG 538 + #define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 539 + #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 540 + #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 541 + #define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 542 + #define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 543 + #define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 544 + #define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 545 + #define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 546 + #define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 547 + #define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 548 + #define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 549 + #define SDMA1_STATUS1_REG__EX_START__SHIFT 0xf 550 + #define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 551 + #define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 552 + #define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L 553 + #define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L 554 + #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L 555 + #define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L 556 + #define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L 557 + #define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L 558 + #define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L 559 + #define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L 560 + #define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L 561 + #define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L 562 + #define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L 563 + #define SDMA1_STATUS1_REG__EX_START_MASK 0x00008000L 564 + #define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L 565 + #define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L 566 + //SDMA1_RD_BURST_CNTL 567 + #define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 568 + #define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L 569 + //SDMA1_HBM_PAGE_CONFIG 570 + #define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 571 + #define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L 572 + //SDMA1_UCODE_CHECKSUM 573 + #define SDMA1_UCODE_CHECKSUM__DATA__SHIFT 0x0 574 + #define SDMA1_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 575 + //SDMA1_F32_CNTL 576 + #define SDMA1_F32_CNTL__HALT__SHIFT 0x0 577 + #define SDMA1_F32_CNTL__STEP__SHIFT 0x1 578 + #define SDMA1_F32_CNTL__HALT_MASK 0x00000001L 579 + #define SDMA1_F32_CNTL__STEP_MASK 0x00000002L 580 + //SDMA1_FREEZE 581 + #define SDMA1_FREEZE__PREEMPT__SHIFT 0x0 582 + #define SDMA1_FREEZE__FREEZE__SHIFT 0x4 583 + #define SDMA1_FREEZE__FROZEN__SHIFT 0x5 584 + #define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6 585 + #define SDMA1_FREEZE__PREEMPT_MASK 0x00000001L 586 + #define SDMA1_FREEZE__FREEZE_MASK 0x00000010L 587 + #define SDMA1_FREEZE__FROZEN_MASK 0x00000020L 588 + #define SDMA1_FREEZE__F32_FREEZE_MASK 0x00000040L 589 + //SDMA1_PHASE0_QUANTUM 590 + #define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0 591 + #define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 592 + #define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 593 + #define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL 594 + #define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L 595 + #define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000L 596 + //SDMA1_PHASE1_QUANTUM 597 + #define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0 598 + #define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8 599 + #define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 600 + #define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL 601 + #define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L 602 + #define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000L 603 + //SDMA1_EDC_CONFIG 604 + #define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1 605 + #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 606 + #define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 607 + #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L 608 + //SDMA1_BA_THRESHOLD 609 + #define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0 610 + #define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 611 + #define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL 612 + #define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L 613 + //SDMA1_ID 614 + #define SDMA1_ID__DEVICE_ID__SHIFT 0x0 615 + #define SDMA1_ID__DEVICE_ID_MASK 0x000000FFL 616 + //SDMA1_VERSION 617 + #define SDMA1_VERSION__MINVER__SHIFT 0x0 618 + #define SDMA1_VERSION__MAJVER__SHIFT 0x8 619 + #define SDMA1_VERSION__REV__SHIFT 0x10 620 + #define SDMA1_VERSION__MINVER_MASK 0x0000007FL 621 + #define SDMA1_VERSION__MAJVER_MASK 0x00007F00L 622 + #define SDMA1_VERSION__REV_MASK 0x003F0000L 623 + //SDMA1_EDC_COUNTER 624 + #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 625 + #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 626 + #define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 627 + #define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 628 + #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 629 + #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 630 + #define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 631 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 632 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 633 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 634 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa 635 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb 636 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc 637 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd 638 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe 639 + #define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf 640 + #define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 641 + #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L 642 + #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L 643 + #define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L 644 + #define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L 645 + #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L 646 + #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L 647 + #define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L 648 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L 649 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L 650 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L 651 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L 652 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L 653 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L 654 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L 655 + #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L 656 + #define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L 657 + #define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L 658 + //SDMA1_EDC_COUNTER_CLEAR 659 + #define SDMA1_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 660 + #define SDMA1_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L 661 + //SDMA1_STATUS2_REG 662 + #define SDMA1_STATUS2_REG__ID__SHIFT 0x0 663 + #define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 664 + #define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10 665 + #define SDMA1_STATUS2_REG__ID_MASK 0x00000003L 666 + #define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL 667 + #define SDMA1_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L 668 + //SDMA1_ATOMIC_CNTL 669 + #define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 670 + #define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 671 + #define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 672 + #define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L 673 + //SDMA1_ATOMIC_PREOP_LO 674 + #define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 675 + #define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 676 + //SDMA1_ATOMIC_PREOP_HI 677 + #define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 678 + #define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 679 + //SDMA1_UTCL1_CNTL 680 + #define SDMA1_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 681 + #define SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 682 + #define SDMA1_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb 683 + #define SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe 684 + #define SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 685 + #define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d 686 + #define SDMA1_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L 687 + #define SDMA1_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL 688 + #define SDMA1_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L 689 + #define SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L 690 + #define SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L 691 + #define SDMA1_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L 692 + //SDMA1_UTCL1_WATERMK 693 + #define SDMA1_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 694 + #define SDMA1_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa 695 + #define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 696 + #define SDMA1_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a 697 + #define SDMA1_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL 698 + #define SDMA1_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L 699 + #define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L 700 + #define SDMA1_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L 701 + //SDMA1_UTCL1_RD_STATUS 702 + #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 703 + #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 704 + #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 705 + #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 706 + #define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 707 + #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 708 + #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 709 + #define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 710 + #define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 711 + #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 712 + #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 713 + #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 714 + #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 715 + #define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 716 + #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 717 + #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 718 + #define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 719 + #define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 720 + #define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 721 + #define SDMA1_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 722 + #define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 723 + #define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 724 + #define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 725 + #define SDMA1_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 726 + #define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d 727 + #define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e 728 + #define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f 729 + #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 730 + #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 731 + #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 732 + #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 733 + #define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 734 + #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 735 + #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 736 + #define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 737 + #define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 738 + #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 739 + #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 740 + #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 741 + #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 742 + #define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 743 + #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 744 + #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 745 + #define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 746 + #define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 747 + #define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L 748 + #define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L 749 + #define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L 750 + #define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L 751 + #define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L 752 + #define SDMA1_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L 753 + #define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L 754 + #define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L 755 + #define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L 756 + //SDMA1_UTCL1_WR_STATUS 757 + #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 758 + #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 759 + #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 760 + #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 761 + #define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 762 + #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 763 + #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 764 + #define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 765 + #define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 766 + #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 767 + #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 768 + #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 769 + #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 770 + #define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 771 + #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 772 + #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 773 + #define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 774 + #define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 775 + #define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 776 + #define SDMA1_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 777 + #define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 778 + #define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 779 + #define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 780 + #define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 781 + #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c 782 + #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d 783 + #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e 784 + #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f 785 + #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 786 + #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 787 + #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 788 + #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 789 + #define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 790 + #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 791 + #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 792 + #define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 793 + #define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 794 + #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 795 + #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 796 + #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 797 + #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 798 + #define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 799 + #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 800 + #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 801 + #define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 802 + #define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 803 + #define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L 804 + #define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L 805 + #define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L 806 + #define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L 807 + #define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L 808 + #define SDMA1_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L 809 + #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L 810 + #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L 811 + #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L 812 + #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L 813 + //SDMA1_UTCL1_INV0 814 + #define SDMA1_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 815 + #define SDMA1_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 816 + #define SDMA1_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 817 + #define SDMA1_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 818 + #define SDMA1_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 819 + #define SDMA1_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 820 + #define SDMA1_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 821 + #define SDMA1_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 822 + #define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 823 + #define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 824 + #define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa 825 + #define SDMA1_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 826 + #define SDMA1_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc 827 + #define SDMA1_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 828 + #define SDMA1_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L 829 + #define SDMA1_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L 830 + #define SDMA1_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L 831 + #define SDMA1_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L 832 + #define SDMA1_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L 833 + #define SDMA1_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L 834 + #define SDMA1_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L 835 + #define SDMA1_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L 836 + #define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L 837 + #define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L 838 + #define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L 839 + #define SDMA1_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L 840 + #define SDMA1_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L 841 + #define SDMA1_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L 842 + //SDMA1_UTCL1_INV1 843 + #define SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 844 + #define SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL 845 + //SDMA1_UTCL1_INV2 846 + #define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 847 + #define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL 848 + //SDMA1_UTCL1_RD_XNACK0 849 + #define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 850 + #define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 851 + //SDMA1_UTCL1_RD_XNACK1 852 + #define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 853 + #define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 854 + #define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 855 + #define SDMA1_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a 856 + #define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 857 + #define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L 858 + #define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 859 + #define SDMA1_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L 860 + //SDMA1_UTCL1_WR_XNACK0 861 + #define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 862 + #define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 863 + //SDMA1_UTCL1_WR_XNACK1 864 + #define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 865 + #define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 866 + #define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 867 + #define SDMA1_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a 868 + #define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 869 + #define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L 870 + #define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 871 + #define SDMA1_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L 872 + //SDMA1_UTCL1_TIMEOUT 873 + #define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 874 + #define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 875 + #define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL 876 + #define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L 877 + //SDMA1_UTCL1_PAGE 878 + #define SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 879 + #define SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 880 + #define SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 881 + #define SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 882 + #define SDMA1_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L 883 + #define SDMA1_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL 884 + #define SDMA1_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L 885 + #define SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L 886 + //SDMA1_POWER_CNTL_IDLE 887 + #define SDMA1_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 888 + #define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 889 + #define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 890 + #define SDMA1_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL 891 + #define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L 892 + #define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L 893 + //SDMA1_RELAX_ORDERING_LUT 894 + #define SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 895 + #define SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 896 + #define SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 897 + #define SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 898 + #define SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 899 + #define SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 900 + #define SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 901 + #define SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 902 + #define SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 903 + #define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 904 + #define SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb 905 + #define SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc 906 + #define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 907 + #define SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 908 + #define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 909 + #define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 910 + #define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d 911 + #define SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 912 + #define SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 913 + #define SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 914 + #define SDMA1_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L 915 + #define SDMA1_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L 916 + #define SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 917 + #define SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 918 + #define SDMA1_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 919 + #define SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 920 + #define SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 921 + #define SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 922 + #define SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 923 + #define SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L 924 + #define SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L 925 + #define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 926 + #define SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 927 + #define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 928 + #define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 929 + #define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L 930 + #define SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 931 + #define SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 932 + //SDMA1_CHICKEN_BITS_2 933 + #define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 934 + #define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 935 + //SDMA1_STATUS3_REG 936 + #define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 937 + #define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 938 + #define SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 939 + #define SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL 940 + #define SDMA1_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L 941 + #define SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L 942 + //SDMA1_PHYSICAL_ADDR_LO 943 + #define SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 944 + #define SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 945 + #define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 946 + #define SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc 947 + #define SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L 948 + #define SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L 949 + #define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L 950 + #define SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L 951 + //SDMA1_PHYSICAL_ADDR_HI 952 + #define SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 953 + #define SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL 954 + //SDMA1_PHASE2_QUANTUM 955 + #define SDMA1_PHASE2_QUANTUM__UNIT__SHIFT 0x0 956 + #define SDMA1_PHASE2_QUANTUM__VALUE__SHIFT 0x8 957 + #define SDMA1_PHASE2_QUANTUM__PREFER__SHIFT 0x1e 958 + #define SDMA1_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL 959 + #define SDMA1_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L 960 + #define SDMA1_PHASE2_QUANTUM__PREFER_MASK 0x40000000L 961 + //SDMA1_ERROR_LOG 962 + #define SDMA1_ERROR_LOG__OVERRIDE__SHIFT 0x0 963 + #define SDMA1_ERROR_LOG__STATUS__SHIFT 0x10 964 + #define SDMA1_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 965 + #define SDMA1_ERROR_LOG__STATUS_MASK 0xFFFF0000L 966 + //SDMA1_PUB_DUMMY_REG0 967 + #define SDMA1_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 968 + #define SDMA1_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL 969 + //SDMA1_PUB_DUMMY_REG1 970 + #define SDMA1_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 971 + #define SDMA1_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL 972 + //SDMA1_PUB_DUMMY_REG2 973 + #define SDMA1_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 974 + #define SDMA1_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL 975 + //SDMA1_PUB_DUMMY_REG3 976 + #define SDMA1_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 977 + #define SDMA1_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL 978 + //SDMA1_F32_COUNTER 979 + #define SDMA1_F32_COUNTER__VALUE__SHIFT 0x0 980 + #define SDMA1_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 981 + //SDMA1_UNBREAKABLE 982 + #define SDMA1_UNBREAKABLE__VALUE__SHIFT 0x0 983 + #define SDMA1_UNBREAKABLE__VALUE_MASK 0x00000001L 984 + //SDMA1_PERFMON_CNTL 985 + #define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 986 + #define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 987 + #define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 988 + #define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa 989 + #define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb 990 + #define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc 991 + #define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L 992 + #define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L 993 + #define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL 994 + #define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L 995 + #define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L 996 + #define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L 997 + //SDMA1_PERFCOUNTER0_RESULT 998 + #define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 999 + #define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1000 + //SDMA1_PERFCOUNTER1_RESULT 1001 + #define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 1002 + #define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1003 + //SDMA1_PERFCOUNTER_TAG_DELAY_RANGE 1004 + #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 1005 + #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe 1006 + #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c 1007 + #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL 1008 + #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L 1009 + #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L 1010 + //SDMA1_CRD_CNTL 1011 + #define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 1012 + #define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 1013 + #define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 1014 + #define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 1015 + //SDMA1_MMHUB_TRUSTLVL 1016 + #define SDMA1_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0 1017 + #define SDMA1_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x3 1018 + #define SDMA1_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x6 1019 + #define SDMA1_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x9 1020 + #define SDMA1_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0xc 1021 + #define SDMA1_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0xf 1022 + #define SDMA1_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x12 1023 + #define SDMA1_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x15 1024 + #define SDMA1_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L 1025 + #define SDMA1_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L 1026 + #define SDMA1_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001C0L 1027 + #define SDMA1_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000E00L 1028 + #define SDMA1_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L 1029 + #define SDMA1_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L 1030 + #define SDMA1_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001C0000L 1031 + #define SDMA1_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00E00000L 1032 + //SDMA1_GPU_IOV_VIOLATION_LOG 1033 + #define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 1034 + #define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 1035 + #define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 1036 + #define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12 1037 + #define SDMA1_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 1038 + #define SDMA1_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 1039 + #define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 1040 + #define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 1041 + #define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 1042 + #define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL 1043 + #define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L 1044 + #define SDMA1_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L 1045 + #define SDMA1_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L 1046 + #define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L 1047 + //SDMA1_ULV_CNTL 1048 + #define SDMA1_ULV_CNTL__HYSTERESIS__SHIFT 0x0 1049 + #define SDMA1_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d 1050 + #define SDMA1_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e 1051 + #define SDMA1_ULV_CNTL__ULV_STATUS__SHIFT 0x1f 1052 + #define SDMA1_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL 1053 + #define SDMA1_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L 1054 + #define SDMA1_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L 1055 + #define SDMA1_ULV_CNTL__ULV_STATUS_MASK 0x80000000L 1056 + //SDMA1_EA_DBIT_ADDR_DATA 1057 + #define SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 1058 + #define SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL 1059 + //SDMA1_EA_DBIT_ADDR_INDEX 1060 + #define SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 1061 + #define SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L 1062 + //SDMA1_GFX_RB_CNTL 1063 + #define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 1064 + #define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 1065 + #define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1066 + #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1067 + #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1068 + #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1069 + #define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 1070 + #define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 1071 + #define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1072 + #define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1073 + #define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1074 + #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1075 + #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1076 + #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1077 + #define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L 1078 + #define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L 1079 + //SDMA1_GFX_RB_BASE 1080 + #define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0 1081 + #define SDMA1_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1082 + //SDMA1_GFX_RB_BASE_HI 1083 + #define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 1084 + #define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1085 + //SDMA1_GFX_RB_RPTR 1086 + #define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x0 1087 + #define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1088 + //SDMA1_GFX_RB_RPTR_HI 1089 + #define SDMA1_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 1090 + #define SDMA1_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1091 + //SDMA1_GFX_RB_WPTR 1092 + #define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x0 1093 + #define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1094 + //SDMA1_GFX_RB_WPTR_HI 1095 + #define SDMA1_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 1096 + #define SDMA1_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1097 + //SDMA1_GFX_RB_WPTR_POLL_CNTL 1098 + #define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1099 + #define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1100 + #define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1101 + #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1102 + #define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1103 + #define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1104 + #define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1105 + #define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1106 + #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1107 + #define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1108 + //SDMA1_GFX_RB_RPTR_ADDR_HI 1109 + #define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1110 + #define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1111 + //SDMA1_GFX_RB_RPTR_ADDR_LO 1112 + #define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1113 + #define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1114 + //SDMA1_GFX_IB_CNTL 1115 + #define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 1116 + #define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1117 + #define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1118 + #define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 1119 + #define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1120 + #define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1121 + #define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1122 + #define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1123 + //SDMA1_GFX_IB_RPTR 1124 + #define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2 1125 + #define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1126 + //SDMA1_GFX_IB_OFFSET 1127 + #define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 1128 + #define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1129 + //SDMA1_GFX_IB_BASE_LO 1130 + #define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 1131 + #define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1132 + //SDMA1_GFX_IB_BASE_HI 1133 + #define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 1134 + #define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1135 + //SDMA1_GFX_IB_SIZE 1136 + #define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0 1137 + #define SDMA1_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL 1138 + //SDMA1_GFX_SKIP_CNTL 1139 + #define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1140 + #define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1141 + //SDMA1_GFX_CONTEXT_STATUS 1142 + #define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1143 + #define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 1144 + #define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1145 + #define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1146 + #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1147 + #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1148 + #define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1149 + #define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1150 + #define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1151 + #define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1152 + #define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1153 + #define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1154 + #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1155 + #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1156 + #define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1157 + #define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1158 + //SDMA1_GFX_DOORBELL 1159 + #define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c 1160 + #define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 1161 + #define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000L 1162 + #define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000L 1163 + //SDMA1_GFX_CONTEXT_CNTL 1164 + #define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 1165 + #define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L 1166 + //SDMA1_GFX_STATUS 1167 + #define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1168 + #define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1169 + #define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1170 + #define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1171 + //SDMA1_GFX_DOORBELL_LOG 1172 + #define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1173 + #define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 1174 + #define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1175 + #define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1176 + //SDMA1_GFX_WATERMARK 1177 + #define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1178 + #define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1179 + #define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1180 + #define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1181 + //SDMA1_GFX_DOORBELL_OFFSET 1182 + #define SDMA1_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1183 + #define SDMA1_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1184 + //SDMA1_GFX_CSA_ADDR_LO 1185 + #define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 1186 + #define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1187 + //SDMA1_GFX_CSA_ADDR_HI 1188 + #define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 1189 + #define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1190 + //SDMA1_GFX_IB_SUB_REMAIN 1191 + #define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1192 + #define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1193 + //SDMA1_GFX_PREEMPT 1194 + #define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 1195 + #define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1196 + //SDMA1_GFX_DUMMY_REG 1197 + #define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 1198 + #define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1199 + //SDMA1_GFX_RB_WPTR_POLL_ADDR_HI 1200 + #define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1201 + #define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1202 + //SDMA1_GFX_RB_WPTR_POLL_ADDR_LO 1203 + #define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1204 + #define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1205 + //SDMA1_GFX_RB_AQL_CNTL 1206 + #define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1207 + #define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1208 + #define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1209 + #define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1210 + #define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1211 + #define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1212 + //SDMA1_GFX_MINOR_PTR_UPDATE 1213 + #define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1214 + #define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1215 + //SDMA1_GFX_MIDCMD_DATA0 1216 + #define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 1217 + #define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1218 + //SDMA1_GFX_MIDCMD_DATA1 1219 + #define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 1220 + #define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1221 + //SDMA1_GFX_MIDCMD_DATA2 1222 + #define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 1223 + #define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1224 + //SDMA1_GFX_MIDCMD_DATA3 1225 + #define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 1226 + #define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1227 + //SDMA1_GFX_MIDCMD_DATA4 1228 + #define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 1229 + #define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1230 + //SDMA1_GFX_MIDCMD_DATA5 1231 + #define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 1232 + #define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1233 + //SDMA1_GFX_MIDCMD_DATA6 1234 + #define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 1235 + #define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1236 + //SDMA1_GFX_MIDCMD_DATA7 1237 + #define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 1238 + #define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1239 + //SDMA1_GFX_MIDCMD_DATA8 1240 + #define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 1241 + #define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1242 + //SDMA1_GFX_MIDCMD_CNTL 1243 + #define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1244 + #define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1245 + #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1246 + #define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1247 + #define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1248 + #define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1249 + #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1250 + #define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1251 + //SDMA1_PAGE_RB_CNTL 1252 + #define SDMA1_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 1253 + #define SDMA1_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 1254 + #define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1255 + #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1256 + #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1257 + #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1258 + #define SDMA1_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 1259 + #define SDMA1_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 1260 + #define SDMA1_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1261 + #define SDMA1_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1262 + #define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1263 + #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1264 + #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1265 + #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1266 + #define SDMA1_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L 1267 + #define SDMA1_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L 1268 + //SDMA1_PAGE_RB_BASE 1269 + #define SDMA1_PAGE_RB_BASE__ADDR__SHIFT 0x0 1270 + #define SDMA1_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1271 + //SDMA1_PAGE_RB_BASE_HI 1272 + #define SDMA1_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 1273 + #define SDMA1_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1274 + //SDMA1_PAGE_RB_RPTR 1275 + #define SDMA1_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 1276 + #define SDMA1_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1277 + //SDMA1_PAGE_RB_RPTR_HI 1278 + #define SDMA1_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 1279 + #define SDMA1_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1280 + //SDMA1_PAGE_RB_WPTR 1281 + #define SDMA1_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 1282 + #define SDMA1_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1283 + //SDMA1_PAGE_RB_WPTR_HI 1284 + #define SDMA1_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 1285 + #define SDMA1_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1286 + //SDMA1_PAGE_RB_WPTR_POLL_CNTL 1287 + #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1288 + #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1289 + #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1290 + #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1291 + #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1292 + #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1293 + #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1294 + #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1295 + #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1296 + #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1297 + //SDMA1_PAGE_RB_RPTR_ADDR_HI 1298 + #define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1299 + #define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1300 + //SDMA1_PAGE_RB_RPTR_ADDR_LO 1301 + #define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1302 + #define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1303 + //SDMA1_PAGE_IB_CNTL 1304 + #define SDMA1_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 1305 + #define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1306 + #define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1307 + #define SDMA1_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 1308 + #define SDMA1_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1309 + #define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1310 + #define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1311 + #define SDMA1_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1312 + //SDMA1_PAGE_IB_RPTR 1313 + #define SDMA1_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 1314 + #define SDMA1_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1315 + //SDMA1_PAGE_IB_OFFSET 1316 + #define SDMA1_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 1317 + #define SDMA1_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1318 + //SDMA1_PAGE_IB_BASE_LO 1319 + #define SDMA1_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 1320 + #define SDMA1_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1321 + //SDMA1_PAGE_IB_BASE_HI 1322 + #define SDMA1_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 1323 + #define SDMA1_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1324 + //SDMA1_PAGE_IB_SIZE 1325 + #define SDMA1_PAGE_IB_SIZE__SIZE__SHIFT 0x0 1326 + #define SDMA1_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL 1327 + //SDMA1_PAGE_SKIP_CNTL 1328 + #define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1329 + #define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1330 + //SDMA1_PAGE_CONTEXT_STATUS 1331 + #define SDMA1_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1332 + #define SDMA1_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 1333 + #define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1334 + #define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1335 + #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1336 + #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1337 + #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1338 + #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1339 + #define SDMA1_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1340 + #define SDMA1_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1341 + #define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1342 + #define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1343 + #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1344 + #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1345 + #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1346 + #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1347 + //SDMA1_PAGE_DOORBELL 1348 + #define SDMA1_PAGE_DOORBELL__ENABLE__SHIFT 0x1c 1349 + #define SDMA1_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e 1350 + #define SDMA1_PAGE_DOORBELL__ENABLE_MASK 0x10000000L 1351 + #define SDMA1_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L 1352 + //SDMA1_PAGE_STATUS 1353 + #define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1354 + #define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1355 + #define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1356 + #define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1357 + //SDMA1_PAGE_DOORBELL_LOG 1358 + #define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1359 + #define SDMA1_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 1360 + #define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1361 + #define SDMA1_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1362 + //SDMA1_PAGE_WATERMARK 1363 + #define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1364 + #define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1365 + #define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1366 + #define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1367 + //SDMA1_PAGE_DOORBELL_OFFSET 1368 + #define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1369 + #define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1370 + //SDMA1_PAGE_CSA_ADDR_LO 1371 + #define SDMA1_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 1372 + #define SDMA1_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1373 + //SDMA1_PAGE_CSA_ADDR_HI 1374 + #define SDMA1_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 1375 + #define SDMA1_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1376 + //SDMA1_PAGE_IB_SUB_REMAIN 1377 + #define SDMA1_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1378 + #define SDMA1_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1379 + //SDMA1_PAGE_PREEMPT 1380 + #define SDMA1_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 1381 + #define SDMA1_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1382 + //SDMA1_PAGE_DUMMY_REG 1383 + #define SDMA1_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 1384 + #define SDMA1_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1385 + //SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI 1386 + #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1387 + #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1388 + //SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO 1389 + #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1390 + #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1391 + //SDMA1_PAGE_RB_AQL_CNTL 1392 + #define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1393 + #define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1394 + #define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1395 + #define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1396 + #define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1397 + #define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1398 + //SDMA1_PAGE_MINOR_PTR_UPDATE 1399 + #define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1400 + #define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1401 + //SDMA1_PAGE_MIDCMD_DATA0 1402 + #define SDMA1_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 1403 + #define SDMA1_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1404 + //SDMA1_PAGE_MIDCMD_DATA1 1405 + #define SDMA1_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 1406 + #define SDMA1_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1407 + //SDMA1_PAGE_MIDCMD_DATA2 1408 + #define SDMA1_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 1409 + #define SDMA1_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1410 + //SDMA1_PAGE_MIDCMD_DATA3 1411 + #define SDMA1_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 1412 + #define SDMA1_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1413 + //SDMA1_PAGE_MIDCMD_DATA4 1414 + #define SDMA1_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 1415 + #define SDMA1_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1416 + //SDMA1_PAGE_MIDCMD_DATA5 1417 + #define SDMA1_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 1418 + #define SDMA1_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1419 + //SDMA1_PAGE_MIDCMD_DATA6 1420 + #define SDMA1_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 1421 + #define SDMA1_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1422 + //SDMA1_PAGE_MIDCMD_DATA7 1423 + #define SDMA1_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 1424 + #define SDMA1_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1425 + //SDMA1_PAGE_MIDCMD_DATA8 1426 + #define SDMA1_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 1427 + #define SDMA1_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1428 + //SDMA1_PAGE_MIDCMD_CNTL 1429 + #define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1430 + #define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1431 + #define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1432 + #define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1433 + #define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1434 + #define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1435 + #define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1436 + #define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1437 + //SDMA1_RLC0_RB_CNTL 1438 + #define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 1439 + #define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 1440 + #define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1441 + #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1442 + #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1443 + #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1444 + #define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 1445 + #define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 1446 + #define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1447 + #define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1448 + #define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1449 + #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1450 + #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1451 + #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1452 + #define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L 1453 + #define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L 1454 + //SDMA1_RLC0_RB_BASE 1455 + #define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 1456 + #define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1457 + //SDMA1_RLC0_RB_BASE_HI 1458 + #define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 1459 + #define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1460 + //SDMA1_RLC0_RB_RPTR 1461 + #define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 1462 + #define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1463 + //SDMA1_RLC0_RB_RPTR_HI 1464 + #define SDMA1_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 1465 + #define SDMA1_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1466 + //SDMA1_RLC0_RB_WPTR 1467 + #define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 1468 + #define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1469 + //SDMA1_RLC0_RB_WPTR_HI 1470 + #define SDMA1_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 1471 + #define SDMA1_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1472 + //SDMA1_RLC0_RB_WPTR_POLL_CNTL 1473 + #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1474 + #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1475 + #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1476 + #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1477 + #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1478 + #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1479 + #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1480 + #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1481 + #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1482 + #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1483 + //SDMA1_RLC0_RB_RPTR_ADDR_HI 1484 + #define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1485 + #define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1486 + //SDMA1_RLC0_RB_RPTR_ADDR_LO 1487 + #define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1488 + #define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1489 + //SDMA1_RLC0_IB_CNTL 1490 + #define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 1491 + #define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1492 + #define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1493 + #define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 1494 + #define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1495 + #define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1496 + #define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1497 + #define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1498 + //SDMA1_RLC0_IB_RPTR 1499 + #define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 1500 + #define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1501 + //SDMA1_RLC0_IB_OFFSET 1502 + #define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 1503 + #define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1504 + //SDMA1_RLC0_IB_BASE_LO 1505 + #define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 1506 + #define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1507 + //SDMA1_RLC0_IB_BASE_HI 1508 + #define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 1509 + #define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1510 + //SDMA1_RLC0_IB_SIZE 1511 + #define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0 1512 + #define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL 1513 + //SDMA1_RLC0_SKIP_CNTL 1514 + #define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1515 + #define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1516 + //SDMA1_RLC0_CONTEXT_STATUS 1517 + #define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1518 + #define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 1519 + #define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1520 + #define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1521 + #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1522 + #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1523 + #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1524 + #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1525 + #define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1526 + #define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1527 + #define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1528 + #define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1529 + #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1530 + #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1531 + #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1532 + #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1533 + //SDMA1_RLC0_DOORBELL 1534 + #define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 1535 + #define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 1536 + #define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000L 1537 + #define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L 1538 + //SDMA1_RLC0_STATUS 1539 + #define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1540 + #define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1541 + #define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1542 + #define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1543 + //SDMA1_RLC0_DOORBELL_LOG 1544 + #define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1545 + #define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 1546 + #define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1547 + #define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1548 + //SDMA1_RLC0_WATERMARK 1549 + #define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1550 + #define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1551 + #define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1552 + #define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1553 + //SDMA1_RLC0_DOORBELL_OFFSET 1554 + #define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1555 + #define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1556 + //SDMA1_RLC0_CSA_ADDR_LO 1557 + #define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 1558 + #define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1559 + //SDMA1_RLC0_CSA_ADDR_HI 1560 + #define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 1561 + #define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1562 + //SDMA1_RLC0_IB_SUB_REMAIN 1563 + #define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1564 + #define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1565 + //SDMA1_RLC0_PREEMPT 1566 + #define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 1567 + #define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1568 + //SDMA1_RLC0_DUMMY_REG 1569 + #define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 1570 + #define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1571 + //SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 1572 + #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1573 + #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1574 + //SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 1575 + #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1576 + #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1577 + //SDMA1_RLC0_RB_AQL_CNTL 1578 + #define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1579 + #define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1580 + #define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1581 + #define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1582 + #define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1583 + #define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1584 + //SDMA1_RLC0_MINOR_PTR_UPDATE 1585 + #define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1586 + #define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1587 + //SDMA1_RLC0_MIDCMD_DATA0 1588 + #define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 1589 + #define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1590 + //SDMA1_RLC0_MIDCMD_DATA1 1591 + #define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 1592 + #define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1593 + //SDMA1_RLC0_MIDCMD_DATA2 1594 + #define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 1595 + #define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1596 + //SDMA1_RLC0_MIDCMD_DATA3 1597 + #define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 1598 + #define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1599 + //SDMA1_RLC0_MIDCMD_DATA4 1600 + #define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 1601 + #define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1602 + //SDMA1_RLC0_MIDCMD_DATA5 1603 + #define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 1604 + #define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1605 + //SDMA1_RLC0_MIDCMD_DATA6 1606 + #define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 1607 + #define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1608 + //SDMA1_RLC0_MIDCMD_DATA7 1609 + #define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 1610 + #define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1611 + //SDMA1_RLC0_MIDCMD_DATA8 1612 + #define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 1613 + #define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1614 + //SDMA1_RLC0_MIDCMD_CNTL 1615 + #define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1616 + #define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1617 + #define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1618 + #define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1619 + #define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1620 + #define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1621 + #define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1622 + #define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1623 + //SDMA1_RLC1_RB_CNTL 1624 + #define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 1625 + #define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 1626 + #define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1627 + #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1628 + #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1629 + #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1630 + #define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 1631 + #define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 1632 + #define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1633 + #define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1634 + #define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1635 + #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1636 + #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1637 + #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1638 + #define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L 1639 + #define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L 1640 + //SDMA1_RLC1_RB_BASE 1641 + #define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0 1642 + #define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1643 + //SDMA1_RLC1_RB_BASE_HI 1644 + #define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 1645 + #define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1646 + //SDMA1_RLC1_RB_RPTR 1647 + #define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 1648 + #define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1649 + //SDMA1_RLC1_RB_RPTR_HI 1650 + #define SDMA1_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 1651 + #define SDMA1_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1652 + //SDMA1_RLC1_RB_WPTR 1653 + #define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 1654 + #define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1655 + //SDMA1_RLC1_RB_WPTR_HI 1656 + #define SDMA1_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 1657 + #define SDMA1_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1658 + //SDMA1_RLC1_RB_WPTR_POLL_CNTL 1659 + #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1660 + #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1661 + #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1662 + #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1663 + #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1664 + #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1665 + #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1666 + #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1667 + #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1668 + #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1669 + //SDMA1_RLC1_RB_RPTR_ADDR_HI 1670 + #define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1671 + #define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1672 + //SDMA1_RLC1_RB_RPTR_ADDR_LO 1673 + #define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1674 + #define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1675 + //SDMA1_RLC1_IB_CNTL 1676 + #define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 1677 + #define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1678 + #define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1679 + #define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 1680 + #define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1681 + #define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1682 + #define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1683 + #define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1684 + //SDMA1_RLC1_IB_RPTR 1685 + #define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 1686 + #define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1687 + //SDMA1_RLC1_IB_OFFSET 1688 + #define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 1689 + #define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1690 + //SDMA1_RLC1_IB_BASE_LO 1691 + #define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 1692 + #define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1693 + //SDMA1_RLC1_IB_BASE_HI 1694 + #define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 1695 + #define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1696 + //SDMA1_RLC1_IB_SIZE 1697 + #define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0 1698 + #define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL 1699 + //SDMA1_RLC1_SKIP_CNTL 1700 + #define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1701 + #define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1702 + //SDMA1_RLC1_CONTEXT_STATUS 1703 + #define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1704 + #define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 1705 + #define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1706 + #define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1707 + #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1708 + #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1709 + #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1710 + #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1711 + #define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1712 + #define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1713 + #define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1714 + #define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1715 + #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1716 + #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1717 + #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1718 + #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1719 + //SDMA1_RLC1_DOORBELL 1720 + #define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 1721 + #define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 1722 + #define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000L 1723 + #define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L 1724 + //SDMA1_RLC1_STATUS 1725 + #define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1726 + #define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1727 + #define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1728 + #define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1729 + //SDMA1_RLC1_DOORBELL_LOG 1730 + #define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1731 + #define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 1732 + #define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1733 + #define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1734 + //SDMA1_RLC1_WATERMARK 1735 + #define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1736 + #define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1737 + #define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1738 + #define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1739 + //SDMA1_RLC1_DOORBELL_OFFSET 1740 + #define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1741 + #define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1742 + //SDMA1_RLC1_CSA_ADDR_LO 1743 + #define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 1744 + #define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1745 + //SDMA1_RLC1_CSA_ADDR_HI 1746 + #define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 1747 + #define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1748 + //SDMA1_RLC1_IB_SUB_REMAIN 1749 + #define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1750 + #define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1751 + //SDMA1_RLC1_PREEMPT 1752 + #define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 1753 + #define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1754 + //SDMA1_RLC1_DUMMY_REG 1755 + #define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 1756 + #define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1757 + //SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 1758 + #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1759 + #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1760 + //SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 1761 + #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1762 + #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1763 + //SDMA1_RLC1_RB_AQL_CNTL 1764 + #define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1765 + #define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1766 + #define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1767 + #define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1768 + #define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1769 + #define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1770 + //SDMA1_RLC1_MINOR_PTR_UPDATE 1771 + #define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1772 + #define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1773 + //SDMA1_RLC1_MIDCMD_DATA0 1774 + #define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 1775 + #define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1776 + //SDMA1_RLC1_MIDCMD_DATA1 1777 + #define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 1778 + #define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1779 + //SDMA1_RLC1_MIDCMD_DATA2 1780 + #define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 1781 + #define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1782 + //SDMA1_RLC1_MIDCMD_DATA3 1783 + #define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 1784 + #define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1785 + //SDMA1_RLC1_MIDCMD_DATA4 1786 + #define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 1787 + #define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1788 + //SDMA1_RLC1_MIDCMD_DATA5 1789 + #define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 1790 + #define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1791 + //SDMA1_RLC1_MIDCMD_DATA6 1792 + #define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 1793 + #define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1794 + //SDMA1_RLC1_MIDCMD_DATA7 1795 + #define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 1796 + #define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1797 + //SDMA1_RLC1_MIDCMD_DATA8 1798 + #define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 1799 + #define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1800 + //SDMA1_RLC1_MIDCMD_CNTL 1801 + #define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1802 + #define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1803 + #define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1804 + #define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1805 + #define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1806 + #define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1807 + #define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1808 + #define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1809 + 1810 + #endif
-286
drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_default.h
··· 1 - /* 2 - * Copyright (C) 2017 Advanced Micro Devices, Inc. 3 - * 4 - * Permission is hereby granted, free of charge, to any person obtaining a 5 - * copy of this software and associated documentation files (the "Software"), 6 - * to deal in the Software without restriction, including without limitation 7 - * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 - * and/or sell copies of the Software, and to permit persons to whom the 9 - * Software is furnished to do so, subject to the following conditions: 10 - * 11 - * The above copyright notice and this permission notice shall be included 12 - * in all copies or substantial portions of the Software. 13 - * 14 - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 - */ 21 - #ifndef _sdma0_4_0_DEFAULT_HEADER 22 - #define _sdma0_4_0_DEFAULT_HEADER 23 - 24 - 25 - // addressBlock: sdma0_sdma0dec 26 - #define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000 27 - #define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000 28 - #define mmSDMA0_VM_CNTL_DEFAULT 0x00000000 29 - #define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000 30 - #define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000 31 - #define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000 32 - #define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000 33 - #define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000 34 - #define mmSDMA0_VF_ENABLE_DEFAULT 0x00000000 35 - #define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f 36 - #define mmSDMA0_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff 37 - #define mmSDMA0_CONTEXT_REG_TYPE2_DEFAULT 0x000003ff 38 - #define mmSDMA0_CONTEXT_REG_TYPE3_DEFAULT 0x00000000 39 - #define mmSDMA0_PUB_REG_TYPE0_DEFAULT 0x3c000000 40 - #define mmSDMA0_PUB_REG_TYPE1_DEFAULT 0x30003882 41 - #define mmSDMA0_PUB_REG_TYPE2_DEFAULT 0x0fc6e880 42 - #define mmSDMA0_PUB_REG_TYPE3_DEFAULT 0x00000000 43 - #define mmSDMA0_MMHUB_CNTL_DEFAULT 0x00000000 44 - #define mmSDMA0_CONTEXT_GROUP_BOUNDARY_DEFAULT 0x00000000 45 - #define mmSDMA0_POWER_CNTL_DEFAULT 0x0003c000 46 - #define mmSDMA0_CLK_CTRL_DEFAULT 0xff000100 47 - #define mmSDMA0_CNTL_DEFAULT 0x00000002 48 - #define mmSDMA0_CHICKEN_BITS_DEFAULT 0x00831f07 49 - #define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00100012 50 - #define mmSDMA0_GB_ADDR_CONFIG_READ_DEFAULT 0x00100012 51 - #define mmSDMA0_RB_RPTR_FETCH_HI_DEFAULT 0x00000000 52 - #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT 0x00000000 53 - #define mmSDMA0_RB_RPTR_FETCH_DEFAULT 0x00000000 54 - #define mmSDMA0_IB_OFFSET_FETCH_DEFAULT 0x00000000 55 - #define mmSDMA0_PROGRAM_DEFAULT 0x00000000 56 - #define mmSDMA0_STATUS_REG_DEFAULT 0x46dee557 57 - #define mmSDMA0_STATUS1_REG_DEFAULT 0x000003ff 58 - #define mmSDMA0_RD_BURST_CNTL_DEFAULT 0x00000003 59 - #define mmSDMA0_HBM_PAGE_CONFIG_DEFAULT 0x00000000 60 - #define mmSDMA0_UCODE_CHECKSUM_DEFAULT 0x00000000 61 - #define mmSDMA0_F32_CNTL_DEFAULT 0x00000001 62 - #define mmSDMA0_FREEZE_DEFAULT 0x00000000 63 - #define mmSDMA0_PHASE0_QUANTUM_DEFAULT 0x00010002 64 - #define mmSDMA0_PHASE1_QUANTUM_DEFAULT 0x00010002 65 - #define mmSDMA_POWER_GATING_DEFAULT 0x00000000 66 - #define mmSDMA_PGFSM_CONFIG_DEFAULT 0x00000000 67 - #define mmSDMA_PGFSM_WRITE_DEFAULT 0x00000000 68 - #define mmSDMA_PGFSM_READ_DEFAULT 0x00000000 69 - #define mmSDMA0_EDC_CONFIG_DEFAULT 0x00000002 70 - #define mmSDMA0_BA_THRESHOLD_DEFAULT 0x03ff03ff 71 - #define mmSDMA0_ID_DEFAULT 0x00000001 72 - #define mmSDMA0_VERSION_DEFAULT 0x00000400 73 - #define mmSDMA0_EDC_COUNTER_DEFAULT 0x00000000 74 - #define mmSDMA0_EDC_COUNTER_CLEAR_DEFAULT 0x00000000 75 - #define mmSDMA0_STATUS2_REG_DEFAULT 0x00000000 76 - #define mmSDMA0_ATOMIC_CNTL_DEFAULT 0x00000200 77 - #define mmSDMA0_ATOMIC_PREOP_LO_DEFAULT 0x00000000 78 - #define mmSDMA0_ATOMIC_PREOP_HI_DEFAULT 0x00000000 79 - #define mmSDMA0_UTCL1_CNTL_DEFAULT 0xd0003019 80 - #define mmSDMA0_UTCL1_WATERMK_DEFAULT 0xfffbe1fe 81 - #define mmSDMA0_UTCL1_RD_STATUS_DEFAULT 0x201001ff 82 - #define mmSDMA0_UTCL1_WR_STATUS_DEFAULT 0x503001ff 83 - #define mmSDMA0_UTCL1_INV0_DEFAULT 0x00000600 84 - #define mmSDMA0_UTCL1_INV1_DEFAULT 0x00000000 85 - #define mmSDMA0_UTCL1_INV2_DEFAULT 0x00000000 86 - #define mmSDMA0_UTCL1_RD_XNACK0_DEFAULT 0x00000000 87 - #define mmSDMA0_UTCL1_RD_XNACK1_DEFAULT 0x00000000 88 - #define mmSDMA0_UTCL1_WR_XNACK0_DEFAULT 0x00000000 89 - #define mmSDMA0_UTCL1_WR_XNACK1_DEFAULT 0x00000000 90 - #define mmSDMA0_UTCL1_TIMEOUT_DEFAULT 0x00010001 91 - #define mmSDMA0_UTCL1_PAGE_DEFAULT 0x000003e0 92 - #define mmSDMA0_POWER_CNTL_IDLE_DEFAULT 0x06060200 93 - #define mmSDMA0_RELAX_ORDERING_LUT_DEFAULT 0xc0000006 94 - #define mmSDMA0_CHICKEN_BITS_2_DEFAULT 0x00000005 95 - #define mmSDMA0_STATUS3_REG_DEFAULT 0x00100000 96 - #define mmSDMA0_PHYSICAL_ADDR_LO_DEFAULT 0x00000000 97 - #define mmSDMA0_PHYSICAL_ADDR_HI_DEFAULT 0x00000000 98 - #define mmSDMA0_PHASE2_QUANTUM_DEFAULT 0x00010002 99 - #define mmSDMA0_ERROR_LOG_DEFAULT 0x0000000f 100 - #define mmSDMA0_PUB_DUMMY_REG0_DEFAULT 0x00000000 101 - #define mmSDMA0_PUB_DUMMY_REG1_DEFAULT 0x00000000 102 - #define mmSDMA0_PUB_DUMMY_REG2_DEFAULT 0x00000000 103 - #define mmSDMA0_PUB_DUMMY_REG3_DEFAULT 0x00000000 104 - #define mmSDMA0_F32_COUNTER_DEFAULT 0x00000000 105 - #define mmSDMA0_UNBREAKABLE_DEFAULT 0x00000000 106 - #define mmSDMA0_PERFMON_CNTL_DEFAULT 0x000ff7fd 107 - #define mmSDMA0_PERFCOUNTER0_RESULT_DEFAULT 0x00000000 108 - #define mmSDMA0_PERFCOUNTER1_RESULT_DEFAULT 0x00000000 109 - #define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_DEFAULT 0x00640000 110 - #define mmSDMA0_CRD_CNTL_DEFAULT 0x000085c0 111 - #define mmSDMA0_MMHUB_TRUSTLVL_DEFAULT 0x00000000 112 - #define mmSDMA0_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000 113 - #define mmSDMA0_ULV_CNTL_DEFAULT 0x00000000 114 - #define mmSDMA0_EA_DBIT_ADDR_DATA_DEFAULT 0x00000000 115 - #define mmSDMA0_EA_DBIT_ADDR_INDEX_DEFAULT 0x00000000 116 - #define mmSDMA0_GFX_RB_CNTL_DEFAULT 0x00040000 117 - #define mmSDMA0_GFX_RB_BASE_DEFAULT 0x00000000 118 - #define mmSDMA0_GFX_RB_BASE_HI_DEFAULT 0x00000000 119 - #define mmSDMA0_GFX_RB_RPTR_DEFAULT 0x00000000 120 - #define mmSDMA0_GFX_RB_RPTR_HI_DEFAULT 0x00000000 121 - #define mmSDMA0_GFX_RB_WPTR_DEFAULT 0x00000000 122 - #define mmSDMA0_GFX_RB_WPTR_HI_DEFAULT 0x00000000 123 - #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 124 - #define mmSDMA0_GFX_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 125 - #define mmSDMA0_GFX_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 126 - #define mmSDMA0_GFX_IB_CNTL_DEFAULT 0x00000100 127 - #define mmSDMA0_GFX_IB_RPTR_DEFAULT 0x00000000 128 - #define mmSDMA0_GFX_IB_OFFSET_DEFAULT 0x00000000 129 - #define mmSDMA0_GFX_IB_BASE_LO_DEFAULT 0x00000000 130 - #define mmSDMA0_GFX_IB_BASE_HI_DEFAULT 0x00000000 131 - #define mmSDMA0_GFX_IB_SIZE_DEFAULT 0x00000000 132 - #define mmSDMA0_GFX_SKIP_CNTL_DEFAULT 0x00000000 133 - #define mmSDMA0_GFX_CONTEXT_STATUS_DEFAULT 0x00000005 134 - #define mmSDMA0_GFX_DOORBELL_DEFAULT 0x00000000 135 - #define mmSDMA0_GFX_CONTEXT_CNTL_DEFAULT 0x00000000 136 - #define mmSDMA0_GFX_STATUS_DEFAULT 0x00000000 137 - #define mmSDMA0_GFX_DOORBELL_LOG_DEFAULT 0x00000000 138 - #define mmSDMA0_GFX_WATERMARK_DEFAULT 0x00000000 139 - #define mmSDMA0_GFX_DOORBELL_OFFSET_DEFAULT 0x00000000 140 - #define mmSDMA0_GFX_CSA_ADDR_LO_DEFAULT 0x00000000 141 - #define mmSDMA0_GFX_CSA_ADDR_HI_DEFAULT 0x00000000 142 - #define mmSDMA0_GFX_IB_SUB_REMAIN_DEFAULT 0x00000000 143 - #define mmSDMA0_GFX_PREEMPT_DEFAULT 0x00000000 144 - #define mmSDMA0_GFX_DUMMY_REG_DEFAULT 0x0000000f 145 - #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 146 - #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 147 - #define mmSDMA0_GFX_RB_AQL_CNTL_DEFAULT 0x00004000 148 - #define mmSDMA0_GFX_MINOR_PTR_UPDATE_DEFAULT 0x00000000 149 - #define mmSDMA0_GFX_MIDCMD_DATA0_DEFAULT 0x00000000 150 - #define mmSDMA0_GFX_MIDCMD_DATA1_DEFAULT 0x00000000 151 - #define mmSDMA0_GFX_MIDCMD_DATA2_DEFAULT 0x00000000 152 - #define mmSDMA0_GFX_MIDCMD_DATA3_DEFAULT 0x00000000 153 - #define mmSDMA0_GFX_MIDCMD_DATA4_DEFAULT 0x00000000 154 - #define mmSDMA0_GFX_MIDCMD_DATA5_DEFAULT 0x00000000 155 - #define mmSDMA0_GFX_MIDCMD_DATA6_DEFAULT 0x00000000 156 - #define mmSDMA0_GFX_MIDCMD_DATA7_DEFAULT 0x00000000 157 - #define mmSDMA0_GFX_MIDCMD_DATA8_DEFAULT 0x00000000 158 - #define mmSDMA0_GFX_MIDCMD_CNTL_DEFAULT 0x00000000 159 - #define mmSDMA0_PAGE_RB_CNTL_DEFAULT 0x00040000 160 - #define mmSDMA0_PAGE_RB_BASE_DEFAULT 0x00000000 161 - #define mmSDMA0_PAGE_RB_BASE_HI_DEFAULT 0x00000000 162 - #define mmSDMA0_PAGE_RB_RPTR_DEFAULT 0x00000000 163 - #define mmSDMA0_PAGE_RB_RPTR_HI_DEFAULT 0x00000000 164 - #define mmSDMA0_PAGE_RB_WPTR_DEFAULT 0x00000000 165 - #define mmSDMA0_PAGE_RB_WPTR_HI_DEFAULT 0x00000000 166 - #define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 167 - #define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 168 - #define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 169 - #define mmSDMA0_PAGE_IB_CNTL_DEFAULT 0x00000100 170 - #define mmSDMA0_PAGE_IB_RPTR_DEFAULT 0x00000000 171 - #define mmSDMA0_PAGE_IB_OFFSET_DEFAULT 0x00000000 172 - #define mmSDMA0_PAGE_IB_BASE_LO_DEFAULT 0x00000000 173 - #define mmSDMA0_PAGE_IB_BASE_HI_DEFAULT 0x00000000 174 - #define mmSDMA0_PAGE_IB_SIZE_DEFAULT 0x00000000 175 - #define mmSDMA0_PAGE_SKIP_CNTL_DEFAULT 0x00000000 176 - #define mmSDMA0_PAGE_CONTEXT_STATUS_DEFAULT 0x00000004 177 - #define mmSDMA0_PAGE_DOORBELL_DEFAULT 0x00000000 178 - #define mmSDMA0_PAGE_STATUS_DEFAULT 0x00000000 179 - #define mmSDMA0_PAGE_DOORBELL_LOG_DEFAULT 0x00000000 180 - #define mmSDMA0_PAGE_WATERMARK_DEFAULT 0x00000000 181 - #define mmSDMA0_PAGE_DOORBELL_OFFSET_DEFAULT 0x00000000 182 - #define mmSDMA0_PAGE_CSA_ADDR_LO_DEFAULT 0x00000000 183 - #define mmSDMA0_PAGE_CSA_ADDR_HI_DEFAULT 0x00000000 184 - #define mmSDMA0_PAGE_IB_SUB_REMAIN_DEFAULT 0x00000000 185 - #define mmSDMA0_PAGE_PREEMPT_DEFAULT 0x00000000 186 - #define mmSDMA0_PAGE_DUMMY_REG_DEFAULT 0x0000000f 187 - #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 188 - #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 189 - #define mmSDMA0_PAGE_RB_AQL_CNTL_DEFAULT 0x00004000 190 - #define mmSDMA0_PAGE_MINOR_PTR_UPDATE_DEFAULT 0x00000000 191 - #define mmSDMA0_PAGE_MIDCMD_DATA0_DEFAULT 0x00000000 192 - #define mmSDMA0_PAGE_MIDCMD_DATA1_DEFAULT 0x00000000 193 - #define mmSDMA0_PAGE_MIDCMD_DATA2_DEFAULT 0x00000000 194 - #define mmSDMA0_PAGE_MIDCMD_DATA3_DEFAULT 0x00000000 195 - #define mmSDMA0_PAGE_MIDCMD_DATA4_DEFAULT 0x00000000 196 - #define mmSDMA0_PAGE_MIDCMD_DATA5_DEFAULT 0x00000000 197 - #define mmSDMA0_PAGE_MIDCMD_DATA6_DEFAULT 0x00000000 198 - #define mmSDMA0_PAGE_MIDCMD_DATA7_DEFAULT 0x00000000 199 - #define mmSDMA0_PAGE_MIDCMD_DATA8_DEFAULT 0x00000000 200 - #define mmSDMA0_PAGE_MIDCMD_CNTL_DEFAULT 0x00000000 201 - #define mmSDMA0_RLC0_RB_CNTL_DEFAULT 0x00040000 202 - #define mmSDMA0_RLC0_RB_BASE_DEFAULT 0x00000000 203 - #define mmSDMA0_RLC0_RB_BASE_HI_DEFAULT 0x00000000 204 - #define mmSDMA0_RLC0_RB_RPTR_DEFAULT 0x00000000 205 - #define mmSDMA0_RLC0_RB_RPTR_HI_DEFAULT 0x00000000 206 - #define mmSDMA0_RLC0_RB_WPTR_DEFAULT 0x00000000 207 - #define mmSDMA0_RLC0_RB_WPTR_HI_DEFAULT 0x00000000 208 - #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 209 - #define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 210 - #define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 211 - #define mmSDMA0_RLC0_IB_CNTL_DEFAULT 0x00000100 212 - #define mmSDMA0_RLC0_IB_RPTR_DEFAULT 0x00000000 213 - #define mmSDMA0_RLC0_IB_OFFSET_DEFAULT 0x00000000 214 - #define mmSDMA0_RLC0_IB_BASE_LO_DEFAULT 0x00000000 215 - #define mmSDMA0_RLC0_IB_BASE_HI_DEFAULT 0x00000000 216 - #define mmSDMA0_RLC0_IB_SIZE_DEFAULT 0x00000000 217 - #define mmSDMA0_RLC0_SKIP_CNTL_DEFAULT 0x00000000 218 - #define mmSDMA0_RLC0_CONTEXT_STATUS_DEFAULT 0x00000004 219 - #define mmSDMA0_RLC0_DOORBELL_DEFAULT 0x00000000 220 - #define mmSDMA0_RLC0_STATUS_DEFAULT 0x00000000 221 - #define mmSDMA0_RLC0_DOORBELL_LOG_DEFAULT 0x00000000 222 - #define mmSDMA0_RLC0_WATERMARK_DEFAULT 0x00000000 223 - #define mmSDMA0_RLC0_DOORBELL_OFFSET_DEFAULT 0x00000000 224 - #define mmSDMA0_RLC0_CSA_ADDR_LO_DEFAULT 0x00000000 225 - #define mmSDMA0_RLC0_CSA_ADDR_HI_DEFAULT 0x00000000 226 - #define mmSDMA0_RLC0_IB_SUB_REMAIN_DEFAULT 0x00000000 227 - #define mmSDMA0_RLC0_PREEMPT_DEFAULT 0x00000000 228 - #define mmSDMA0_RLC0_DUMMY_REG_DEFAULT 0x0000000f 229 - #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 230 - #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 231 - #define mmSDMA0_RLC0_RB_AQL_CNTL_DEFAULT 0x00004000 232 - #define mmSDMA0_RLC0_MINOR_PTR_UPDATE_DEFAULT 0x00000000 233 - #define mmSDMA0_RLC0_MIDCMD_DATA0_DEFAULT 0x00000000 234 - #define mmSDMA0_RLC0_MIDCMD_DATA1_DEFAULT 0x00000000 235 - #define mmSDMA0_RLC0_MIDCMD_DATA2_DEFAULT 0x00000000 236 - #define mmSDMA0_RLC0_MIDCMD_DATA3_DEFAULT 0x00000000 237 - #define mmSDMA0_RLC0_MIDCMD_DATA4_DEFAULT 0x00000000 238 - #define mmSDMA0_RLC0_MIDCMD_DATA5_DEFAULT 0x00000000 239 - #define mmSDMA0_RLC0_MIDCMD_DATA6_DEFAULT 0x00000000 240 - #define mmSDMA0_RLC0_MIDCMD_DATA7_DEFAULT 0x00000000 241 - #define mmSDMA0_RLC0_MIDCMD_DATA8_DEFAULT 0x00000000 242 - #define mmSDMA0_RLC0_MIDCMD_CNTL_DEFAULT 0x00000000 243 - #define mmSDMA0_RLC1_RB_CNTL_DEFAULT 0x00040000 244 - #define mmSDMA0_RLC1_RB_BASE_DEFAULT 0x00000000 245 - #define mmSDMA0_RLC1_RB_BASE_HI_DEFAULT 0x00000000 246 - #define mmSDMA0_RLC1_RB_RPTR_DEFAULT 0x00000000 247 - #define mmSDMA0_RLC1_RB_RPTR_HI_DEFAULT 0x00000000 248 - #define mmSDMA0_RLC1_RB_WPTR_DEFAULT 0x00000000 249 - #define mmSDMA0_RLC1_RB_WPTR_HI_DEFAULT 0x00000000 250 - #define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 251 - #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 252 - #define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 253 - #define mmSDMA0_RLC1_IB_CNTL_DEFAULT 0x00000100 254 - #define mmSDMA0_RLC1_IB_RPTR_DEFAULT 0x00000000 255 - #define mmSDMA0_RLC1_IB_OFFSET_DEFAULT 0x00000000 256 - #define mmSDMA0_RLC1_IB_BASE_LO_DEFAULT 0x00000000 257 - #define mmSDMA0_RLC1_IB_BASE_HI_DEFAULT 0x00000000 258 - #define mmSDMA0_RLC1_IB_SIZE_DEFAULT 0x00000000 259 - #define mmSDMA0_RLC1_SKIP_CNTL_DEFAULT 0x00000000 260 - #define mmSDMA0_RLC1_CONTEXT_STATUS_DEFAULT 0x00000004 261 - #define mmSDMA0_RLC1_DOORBELL_DEFAULT 0x00000000 262 - #define mmSDMA0_RLC1_STATUS_DEFAULT 0x00000000 263 - #define mmSDMA0_RLC1_DOORBELL_LOG_DEFAULT 0x00000000 264 - #define mmSDMA0_RLC1_WATERMARK_DEFAULT 0x00000000 265 - #define mmSDMA0_RLC1_DOORBELL_OFFSET_DEFAULT 0x00000000 266 - #define mmSDMA0_RLC1_CSA_ADDR_LO_DEFAULT 0x00000000 267 - #define mmSDMA0_RLC1_CSA_ADDR_HI_DEFAULT 0x00000000 268 - #define mmSDMA0_RLC1_IB_SUB_REMAIN_DEFAULT 0x00000000 269 - #define mmSDMA0_RLC1_PREEMPT_DEFAULT 0x00000000 270 - #define mmSDMA0_RLC1_DUMMY_REG_DEFAULT 0x0000000f 271 - #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 272 - #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 273 - #define mmSDMA0_RLC1_RB_AQL_CNTL_DEFAULT 0x00004000 274 - #define mmSDMA0_RLC1_MINOR_PTR_UPDATE_DEFAULT 0x00000000 275 - #define mmSDMA0_RLC1_MIDCMD_DATA0_DEFAULT 0x00000000 276 - #define mmSDMA0_RLC1_MIDCMD_DATA1_DEFAULT 0x00000000 277 - #define mmSDMA0_RLC1_MIDCMD_DATA2_DEFAULT 0x00000000 278 - #define mmSDMA0_RLC1_MIDCMD_DATA3_DEFAULT 0x00000000 279 - #define mmSDMA0_RLC1_MIDCMD_DATA4_DEFAULT 0x00000000 280 - #define mmSDMA0_RLC1_MIDCMD_DATA5_DEFAULT 0x00000000 281 - #define mmSDMA0_RLC1_MIDCMD_DATA6_DEFAULT 0x00000000 282 - #define mmSDMA0_RLC1_MIDCMD_DATA7_DEFAULT 0x00000000 283 - #define mmSDMA0_RLC1_MIDCMD_DATA8_DEFAULT 0x00000000 284 - #define mmSDMA0_RLC1_MIDCMD_CNTL_DEFAULT 0x00000000 285 - 286 - #endif
-547
drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_offset.h
··· 1 - /* 2 - * Copyright (C) 2017 Advanced Micro Devices, Inc. 3 - * 4 - * Permission is hereby granted, free of charge, to any person obtaining a 5 - * copy of this software and associated documentation files (the "Software"), 6 - * to deal in the Software without restriction, including without limitation 7 - * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 - * and/or sell copies of the Software, and to permit persons to whom the 9 - * Software is furnished to do so, subject to the following conditions: 10 - * 11 - * The above copyright notice and this permission notice shall be included 12 - * in all copies or substantial portions of the Software. 13 - * 14 - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 - */ 21 - #ifndef _sdma0_4_0_OFFSET_HEADER 22 - #define _sdma0_4_0_OFFSET_HEADER 23 - 24 - 25 - 26 - // addressBlock: sdma0_sdma0dec 27 - // base address: 0x4980 28 - #define mmSDMA0_UCODE_ADDR 0x0000 29 - #define mmSDMA0_UCODE_ADDR_BASE_IDX 0 30 - #define mmSDMA0_UCODE_DATA 0x0001 31 - #define mmSDMA0_UCODE_DATA_BASE_IDX 0 32 - #define mmSDMA0_VM_CNTL 0x0004 33 - #define mmSDMA0_VM_CNTL_BASE_IDX 0 34 - #define mmSDMA0_VM_CTX_LO 0x0005 35 - #define mmSDMA0_VM_CTX_LO_BASE_IDX 0 36 - #define mmSDMA0_VM_CTX_HI 0x0006 37 - #define mmSDMA0_VM_CTX_HI_BASE_IDX 0 38 - #define mmSDMA0_ACTIVE_FCN_ID 0x0007 39 - #define mmSDMA0_ACTIVE_FCN_ID_BASE_IDX 0 40 - #define mmSDMA0_VM_CTX_CNTL 0x0008 41 - #define mmSDMA0_VM_CTX_CNTL_BASE_IDX 0 42 - #define mmSDMA0_VIRT_RESET_REQ 0x0009 43 - #define mmSDMA0_VIRT_RESET_REQ_BASE_IDX 0 44 - #define mmSDMA0_VF_ENABLE 0x000a 45 - #define mmSDMA0_VF_ENABLE_BASE_IDX 0 46 - #define mmSDMA0_CONTEXT_REG_TYPE0 0x000b 47 - #define mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX 0 48 - #define mmSDMA0_CONTEXT_REG_TYPE1 0x000c 49 - #define mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX 0 50 - #define mmSDMA0_CONTEXT_REG_TYPE2 0x000d 51 - #define mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX 0 52 - #define mmSDMA0_CONTEXT_REG_TYPE3 0x000e 53 - #define mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX 0 54 - #define mmSDMA0_PUB_REG_TYPE0 0x000f 55 - #define mmSDMA0_PUB_REG_TYPE0_BASE_IDX 0 56 - #define mmSDMA0_PUB_REG_TYPE1 0x0010 57 - #define mmSDMA0_PUB_REG_TYPE1_BASE_IDX 0 58 - #define mmSDMA0_PUB_REG_TYPE2 0x0011 59 - #define mmSDMA0_PUB_REG_TYPE2_BASE_IDX 0 60 - #define mmSDMA0_PUB_REG_TYPE3 0x0012 61 - #define mmSDMA0_PUB_REG_TYPE3_BASE_IDX 0 62 - #define mmSDMA0_MMHUB_CNTL 0x0013 63 - #define mmSDMA0_MMHUB_CNTL_BASE_IDX 0 64 - #define mmSDMA0_CONTEXT_GROUP_BOUNDARY 0x0019 65 - #define mmSDMA0_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 66 - #define mmSDMA0_POWER_CNTL 0x001a 67 - #define mmSDMA0_POWER_CNTL_BASE_IDX 0 68 - #define mmSDMA0_CLK_CTRL 0x001b 69 - #define mmSDMA0_CLK_CTRL_BASE_IDX 0 70 - #define mmSDMA0_CNTL 0x001c 71 - #define mmSDMA0_CNTL_BASE_IDX 0 72 - #define mmSDMA0_CHICKEN_BITS 0x001d 73 - #define mmSDMA0_CHICKEN_BITS_BASE_IDX 0 74 - #define mmSDMA0_GB_ADDR_CONFIG 0x001e 75 - #define mmSDMA0_GB_ADDR_CONFIG_BASE_IDX 0 76 - #define mmSDMA0_GB_ADDR_CONFIG_READ 0x001f 77 - #define mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX 0 78 - #define mmSDMA0_RB_RPTR_FETCH_HI 0x0020 79 - #define mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX 0 80 - #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 81 - #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 82 - #define mmSDMA0_RB_RPTR_FETCH 0x0022 83 - #define mmSDMA0_RB_RPTR_FETCH_BASE_IDX 0 84 - #define mmSDMA0_IB_OFFSET_FETCH 0x0023 85 - #define mmSDMA0_IB_OFFSET_FETCH_BASE_IDX 0 86 - #define mmSDMA0_PROGRAM 0x0024 87 - #define mmSDMA0_PROGRAM_BASE_IDX 0 88 - #define mmSDMA0_STATUS_REG 0x0025 89 - #define mmSDMA0_STATUS_REG_BASE_IDX 0 90 - #define mmSDMA0_STATUS1_REG 0x0026 91 - #define mmSDMA0_STATUS1_REG_BASE_IDX 0 92 - #define mmSDMA0_RD_BURST_CNTL 0x0027 93 - #define mmSDMA0_RD_BURST_CNTL_BASE_IDX 0 94 - #define mmSDMA0_HBM_PAGE_CONFIG 0x0028 95 - #define mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX 0 96 - #define mmSDMA0_UCODE_CHECKSUM 0x0029 97 - #define mmSDMA0_UCODE_CHECKSUM_BASE_IDX 0 98 - #define mmSDMA0_F32_CNTL 0x002a 99 - #define mmSDMA0_F32_CNTL_BASE_IDX 0 100 - #define mmSDMA0_FREEZE 0x002b 101 - #define mmSDMA0_FREEZE_BASE_IDX 0 102 - #define mmSDMA0_PHASE0_QUANTUM 0x002c 103 - #define mmSDMA0_PHASE0_QUANTUM_BASE_IDX 0 104 - #define mmSDMA0_PHASE1_QUANTUM 0x002d 105 - #define mmSDMA0_PHASE1_QUANTUM_BASE_IDX 0 106 - #define mmSDMA_POWER_GATING 0x002e 107 - #define mmSDMA_POWER_GATING_BASE_IDX 0 108 - #define mmSDMA_PGFSM_CONFIG 0x002f 109 - #define mmSDMA_PGFSM_CONFIG_BASE_IDX 0 110 - #define mmSDMA_PGFSM_WRITE 0x0030 111 - #define mmSDMA_PGFSM_WRITE_BASE_IDX 0 112 - #define mmSDMA_PGFSM_READ 0x0031 113 - #define mmSDMA_PGFSM_READ_BASE_IDX 0 114 - #define mmSDMA0_EDC_CONFIG 0x0032 115 - #define mmSDMA0_EDC_CONFIG_BASE_IDX 0 116 - #define mmSDMA0_BA_THRESHOLD 0x0033 117 - #define mmSDMA0_BA_THRESHOLD_BASE_IDX 0 118 - #define mmSDMA0_ID 0x0034 119 - #define mmSDMA0_ID_BASE_IDX 0 120 - #define mmSDMA0_VERSION 0x0035 121 - #define mmSDMA0_VERSION_BASE_IDX 0 122 - #define mmSDMA0_EDC_COUNTER 0x0036 123 - #define mmSDMA0_EDC_COUNTER_BASE_IDX 0 124 - #define mmSDMA0_EDC_COUNTER_CLEAR 0x0037 125 - #define mmSDMA0_EDC_COUNTER_CLEAR_BASE_IDX 0 126 - #define mmSDMA0_STATUS2_REG 0x0038 127 - #define mmSDMA0_STATUS2_REG_BASE_IDX 0 128 - #define mmSDMA0_ATOMIC_CNTL 0x0039 129 - #define mmSDMA0_ATOMIC_CNTL_BASE_IDX 0 130 - #define mmSDMA0_ATOMIC_PREOP_LO 0x003a 131 - #define mmSDMA0_ATOMIC_PREOP_LO_BASE_IDX 0 132 - #define mmSDMA0_ATOMIC_PREOP_HI 0x003b 133 - #define mmSDMA0_ATOMIC_PREOP_HI_BASE_IDX 0 134 - #define mmSDMA0_UTCL1_CNTL 0x003c 135 - #define mmSDMA0_UTCL1_CNTL_BASE_IDX 0 136 - #define mmSDMA0_UTCL1_WATERMK 0x003d 137 - #define mmSDMA0_UTCL1_WATERMK_BASE_IDX 0 138 - #define mmSDMA0_UTCL1_RD_STATUS 0x003e 139 - #define mmSDMA0_UTCL1_RD_STATUS_BASE_IDX 0 140 - #define mmSDMA0_UTCL1_WR_STATUS 0x003f 141 - #define mmSDMA0_UTCL1_WR_STATUS_BASE_IDX 0 142 - #define mmSDMA0_UTCL1_INV0 0x0040 143 - #define mmSDMA0_UTCL1_INV0_BASE_IDX 0 144 - #define mmSDMA0_UTCL1_INV1 0x0041 145 - #define mmSDMA0_UTCL1_INV1_BASE_IDX 0 146 - #define mmSDMA0_UTCL1_INV2 0x0042 147 - #define mmSDMA0_UTCL1_INV2_BASE_IDX 0 148 - #define mmSDMA0_UTCL1_RD_XNACK0 0x0043 149 - #define mmSDMA0_UTCL1_RD_XNACK0_BASE_IDX 0 150 - #define mmSDMA0_UTCL1_RD_XNACK1 0x0044 151 - #define mmSDMA0_UTCL1_RD_XNACK1_BASE_IDX 0 152 - #define mmSDMA0_UTCL1_WR_XNACK0 0x0045 153 - #define mmSDMA0_UTCL1_WR_XNACK0_BASE_IDX 0 154 - #define mmSDMA0_UTCL1_WR_XNACK1 0x0046 155 - #define mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX 0 156 - #define mmSDMA0_UTCL1_TIMEOUT 0x0047 157 - #define mmSDMA0_UTCL1_TIMEOUT_BASE_IDX 0 158 - #define mmSDMA0_UTCL1_PAGE 0x0048 159 - #define mmSDMA0_UTCL1_PAGE_BASE_IDX 0 160 - #define mmSDMA0_POWER_CNTL_IDLE 0x0049 161 - #define mmSDMA0_POWER_CNTL_IDLE_BASE_IDX 0 162 - #define mmSDMA0_RELAX_ORDERING_LUT 0x004a 163 - #define mmSDMA0_RELAX_ORDERING_LUT_BASE_IDX 0 164 - #define mmSDMA0_CHICKEN_BITS_2 0x004b 165 - #define mmSDMA0_CHICKEN_BITS_2_BASE_IDX 0 166 - #define mmSDMA0_STATUS3_REG 0x004c 167 - #define mmSDMA0_STATUS3_REG_BASE_IDX 0 168 - #define mmSDMA0_PHYSICAL_ADDR_LO 0x004d 169 - #define mmSDMA0_PHYSICAL_ADDR_LO_BASE_IDX 0 170 - #define mmSDMA0_PHYSICAL_ADDR_HI 0x004e 171 - #define mmSDMA0_PHYSICAL_ADDR_HI_BASE_IDX 0 172 - #define mmSDMA0_PHASE2_QUANTUM 0x004f 173 - #define mmSDMA0_PHASE2_QUANTUM_BASE_IDX 0 174 - #define mmSDMA0_ERROR_LOG 0x0050 175 - #define mmSDMA0_ERROR_LOG_BASE_IDX 0 176 - #define mmSDMA0_PUB_DUMMY_REG0 0x0051 177 - #define mmSDMA0_PUB_DUMMY_REG0_BASE_IDX 0 178 - #define mmSDMA0_PUB_DUMMY_REG1 0x0052 179 - #define mmSDMA0_PUB_DUMMY_REG1_BASE_IDX 0 180 - #define mmSDMA0_PUB_DUMMY_REG2 0x0053 181 - #define mmSDMA0_PUB_DUMMY_REG2_BASE_IDX 0 182 - #define mmSDMA0_PUB_DUMMY_REG3 0x0054 183 - #define mmSDMA0_PUB_DUMMY_REG3_BASE_IDX 0 184 - #define mmSDMA0_F32_COUNTER 0x0055 185 - #define mmSDMA0_F32_COUNTER_BASE_IDX 0 186 - #define mmSDMA0_UNBREAKABLE 0x0056 187 - #define mmSDMA0_UNBREAKABLE_BASE_IDX 0 188 - #define mmSDMA0_PERFMON_CNTL 0x0057 189 - #define mmSDMA0_PERFMON_CNTL_BASE_IDX 0 190 - #define mmSDMA0_PERFCOUNTER0_RESULT 0x0058 191 - #define mmSDMA0_PERFCOUNTER0_RESULT_BASE_IDX 0 192 - #define mmSDMA0_PERFCOUNTER1_RESULT 0x0059 193 - #define mmSDMA0_PERFCOUNTER1_RESULT_BASE_IDX 0 194 - #define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE 0x005a 195 - #define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0 196 - #define mmSDMA0_CRD_CNTL 0x005b 197 - #define mmSDMA0_CRD_CNTL_BASE_IDX 0 198 - #define mmSDMA0_MMHUB_TRUSTLVL 0x005c 199 - #define mmSDMA0_MMHUB_TRUSTLVL_BASE_IDX 0 200 - #define mmSDMA0_GPU_IOV_VIOLATION_LOG 0x005d 201 - #define mmSDMA0_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 202 - #define mmSDMA0_ULV_CNTL 0x005e 203 - #define mmSDMA0_ULV_CNTL_BASE_IDX 0 204 - #define mmSDMA0_EA_DBIT_ADDR_DATA 0x0060 205 - #define mmSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX 0 206 - #define mmSDMA0_EA_DBIT_ADDR_INDEX 0x0061 207 - #define mmSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX 0 208 - #define mmSDMA0_GFX_RB_CNTL 0x0080 209 - #define mmSDMA0_GFX_RB_CNTL_BASE_IDX 0 210 - #define mmSDMA0_GFX_RB_BASE 0x0081 211 - #define mmSDMA0_GFX_RB_BASE_BASE_IDX 0 212 - #define mmSDMA0_GFX_RB_BASE_HI 0x0082 213 - #define mmSDMA0_GFX_RB_BASE_HI_BASE_IDX 0 214 - #define mmSDMA0_GFX_RB_RPTR 0x0083 215 - #define mmSDMA0_GFX_RB_RPTR_BASE_IDX 0 216 - #define mmSDMA0_GFX_RB_RPTR_HI 0x0084 217 - #define mmSDMA0_GFX_RB_RPTR_HI_BASE_IDX 0 218 - #define mmSDMA0_GFX_RB_WPTR 0x0085 219 - #define mmSDMA0_GFX_RB_WPTR_BASE_IDX 0 220 - #define mmSDMA0_GFX_RB_WPTR_HI 0x0086 221 - #define mmSDMA0_GFX_RB_WPTR_HI_BASE_IDX 0 222 - #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x0087 223 - #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 224 - #define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x0088 225 - #define mmSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 226 - #define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x0089 227 - #define mmSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 228 - #define mmSDMA0_GFX_IB_CNTL 0x008a 229 - #define mmSDMA0_GFX_IB_CNTL_BASE_IDX 0 230 - #define mmSDMA0_GFX_IB_RPTR 0x008b 231 - #define mmSDMA0_GFX_IB_RPTR_BASE_IDX 0 232 - #define mmSDMA0_GFX_IB_OFFSET 0x008c 233 - #define mmSDMA0_GFX_IB_OFFSET_BASE_IDX 0 234 - #define mmSDMA0_GFX_IB_BASE_LO 0x008d 235 - #define mmSDMA0_GFX_IB_BASE_LO_BASE_IDX 0 236 - #define mmSDMA0_GFX_IB_BASE_HI 0x008e 237 - #define mmSDMA0_GFX_IB_BASE_HI_BASE_IDX 0 238 - #define mmSDMA0_GFX_IB_SIZE 0x008f 239 - #define mmSDMA0_GFX_IB_SIZE_BASE_IDX 0 240 - #define mmSDMA0_GFX_SKIP_CNTL 0x0090 241 - #define mmSDMA0_GFX_SKIP_CNTL_BASE_IDX 0 242 - #define mmSDMA0_GFX_CONTEXT_STATUS 0x0091 243 - #define mmSDMA0_GFX_CONTEXT_STATUS_BASE_IDX 0 244 - #define mmSDMA0_GFX_DOORBELL 0x0092 245 - #define mmSDMA0_GFX_DOORBELL_BASE_IDX 0 246 - #define mmSDMA0_GFX_CONTEXT_CNTL 0x0093 247 - #define mmSDMA0_GFX_CONTEXT_CNTL_BASE_IDX 0 248 - #define mmSDMA0_GFX_STATUS 0x00a8 249 - #define mmSDMA0_GFX_STATUS_BASE_IDX 0 250 - #define mmSDMA0_GFX_DOORBELL_LOG 0x00a9 251 - #define mmSDMA0_GFX_DOORBELL_LOG_BASE_IDX 0 252 - #define mmSDMA0_GFX_WATERMARK 0x00aa 253 - #define mmSDMA0_GFX_WATERMARK_BASE_IDX 0 254 - #define mmSDMA0_GFX_DOORBELL_OFFSET 0x00ab 255 - #define mmSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX 0 256 - #define mmSDMA0_GFX_CSA_ADDR_LO 0x00ac 257 - #define mmSDMA0_GFX_CSA_ADDR_LO_BASE_IDX 0 258 - #define mmSDMA0_GFX_CSA_ADDR_HI 0x00ad 259 - #define mmSDMA0_GFX_CSA_ADDR_HI_BASE_IDX 0 260 - #define mmSDMA0_GFX_IB_SUB_REMAIN 0x00af 261 - #define mmSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX 0 262 - #define mmSDMA0_GFX_PREEMPT 0x00b0 263 - #define mmSDMA0_GFX_PREEMPT_BASE_IDX 0 264 - #define mmSDMA0_GFX_DUMMY_REG 0x00b1 265 - #define mmSDMA0_GFX_DUMMY_REG_BASE_IDX 0 266 - #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 267 - #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 268 - #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 269 - #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 270 - #define mmSDMA0_GFX_RB_AQL_CNTL 0x00b4 271 - #define mmSDMA0_GFX_RB_AQL_CNTL_BASE_IDX 0 272 - #define mmSDMA0_GFX_MINOR_PTR_UPDATE 0x00b5 273 - #define mmSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 274 - #define mmSDMA0_GFX_MIDCMD_DATA0 0x00c0 275 - #define mmSDMA0_GFX_MIDCMD_DATA0_BASE_IDX 0 276 - #define mmSDMA0_GFX_MIDCMD_DATA1 0x00c1 277 - #define mmSDMA0_GFX_MIDCMD_DATA1_BASE_IDX 0 278 - #define mmSDMA0_GFX_MIDCMD_DATA2 0x00c2 279 - #define mmSDMA0_GFX_MIDCMD_DATA2_BASE_IDX 0 280 - #define mmSDMA0_GFX_MIDCMD_DATA3 0x00c3 281 - #define mmSDMA0_GFX_MIDCMD_DATA3_BASE_IDX 0 282 - #define mmSDMA0_GFX_MIDCMD_DATA4 0x00c4 283 - #define mmSDMA0_GFX_MIDCMD_DATA4_BASE_IDX 0 284 - #define mmSDMA0_GFX_MIDCMD_DATA5 0x00c5 285 - #define mmSDMA0_GFX_MIDCMD_DATA5_BASE_IDX 0 286 - #define mmSDMA0_GFX_MIDCMD_DATA6 0x00c6 287 - #define mmSDMA0_GFX_MIDCMD_DATA6_BASE_IDX 0 288 - #define mmSDMA0_GFX_MIDCMD_DATA7 0x00c7 289 - #define mmSDMA0_GFX_MIDCMD_DATA7_BASE_IDX 0 290 - #define mmSDMA0_GFX_MIDCMD_DATA8 0x00c8 291 - #define mmSDMA0_GFX_MIDCMD_DATA8_BASE_IDX 0 292 - #define mmSDMA0_GFX_MIDCMD_CNTL 0x00c9 293 - #define mmSDMA0_GFX_MIDCMD_CNTL_BASE_IDX 0 294 - #define mmSDMA0_PAGE_RB_CNTL 0x00e0 295 - #define mmSDMA0_PAGE_RB_CNTL_BASE_IDX 0 296 - #define mmSDMA0_PAGE_RB_BASE 0x00e1 297 - #define mmSDMA0_PAGE_RB_BASE_BASE_IDX 0 298 - #define mmSDMA0_PAGE_RB_BASE_HI 0x00e2 299 - #define mmSDMA0_PAGE_RB_BASE_HI_BASE_IDX 0 300 - #define mmSDMA0_PAGE_RB_RPTR 0x00e3 301 - #define mmSDMA0_PAGE_RB_RPTR_BASE_IDX 0 302 - #define mmSDMA0_PAGE_RB_RPTR_HI 0x00e4 303 - #define mmSDMA0_PAGE_RB_RPTR_HI_BASE_IDX 0 304 - #define mmSDMA0_PAGE_RB_WPTR 0x00e5 305 - #define mmSDMA0_PAGE_RB_WPTR_BASE_IDX 0 306 - #define mmSDMA0_PAGE_RB_WPTR_HI 0x00e6 307 - #define mmSDMA0_PAGE_RB_WPTR_HI_BASE_IDX 0 308 - #define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL 0x00e7 309 - #define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 310 - #define mmSDMA0_PAGE_RB_RPTR_ADDR_HI 0x00e8 311 - #define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 312 - #define mmSDMA0_PAGE_RB_RPTR_ADDR_LO 0x00e9 313 - #define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 314 - #define mmSDMA0_PAGE_IB_CNTL 0x00ea 315 - #define mmSDMA0_PAGE_IB_CNTL_BASE_IDX 0 316 - #define mmSDMA0_PAGE_IB_RPTR 0x00eb 317 - #define mmSDMA0_PAGE_IB_RPTR_BASE_IDX 0 318 - #define mmSDMA0_PAGE_IB_OFFSET 0x00ec 319 - #define mmSDMA0_PAGE_IB_OFFSET_BASE_IDX 0 320 - #define mmSDMA0_PAGE_IB_BASE_LO 0x00ed 321 - #define mmSDMA0_PAGE_IB_BASE_LO_BASE_IDX 0 322 - #define mmSDMA0_PAGE_IB_BASE_HI 0x00ee 323 - #define mmSDMA0_PAGE_IB_BASE_HI_BASE_IDX 0 324 - #define mmSDMA0_PAGE_IB_SIZE 0x00ef 325 - #define mmSDMA0_PAGE_IB_SIZE_BASE_IDX 0 326 - #define mmSDMA0_PAGE_SKIP_CNTL 0x00f0 327 - #define mmSDMA0_PAGE_SKIP_CNTL_BASE_IDX 0 328 - #define mmSDMA0_PAGE_CONTEXT_STATUS 0x00f1 329 - #define mmSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX 0 330 - #define mmSDMA0_PAGE_DOORBELL 0x00f2 331 - #define mmSDMA0_PAGE_DOORBELL_BASE_IDX 0 332 - #define mmSDMA0_PAGE_STATUS 0x0108 333 - #define mmSDMA0_PAGE_STATUS_BASE_IDX 0 334 - #define mmSDMA0_PAGE_DOORBELL_LOG 0x0109 335 - #define mmSDMA0_PAGE_DOORBELL_LOG_BASE_IDX 0 336 - #define mmSDMA0_PAGE_WATERMARK 0x010a 337 - #define mmSDMA0_PAGE_WATERMARK_BASE_IDX 0 338 - #define mmSDMA0_PAGE_DOORBELL_OFFSET 0x010b 339 - #define mmSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX 0 340 - #define mmSDMA0_PAGE_CSA_ADDR_LO 0x010c 341 - #define mmSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX 0 342 - #define mmSDMA0_PAGE_CSA_ADDR_HI 0x010d 343 - #define mmSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX 0 344 - #define mmSDMA0_PAGE_IB_SUB_REMAIN 0x010f 345 - #define mmSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX 0 346 - #define mmSDMA0_PAGE_PREEMPT 0x0110 347 - #define mmSDMA0_PAGE_PREEMPT_BASE_IDX 0 348 - #define mmSDMA0_PAGE_DUMMY_REG 0x0111 349 - #define mmSDMA0_PAGE_DUMMY_REG_BASE_IDX 0 350 - #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 0x0112 351 - #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 352 - #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 0x0113 353 - #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 354 - #define mmSDMA0_PAGE_RB_AQL_CNTL 0x0114 355 - #define mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX 0 356 - #define mmSDMA0_PAGE_MINOR_PTR_UPDATE 0x0115 357 - #define mmSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 358 - #define mmSDMA0_PAGE_MIDCMD_DATA0 0x0120 359 - #define mmSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX 0 360 - #define mmSDMA0_PAGE_MIDCMD_DATA1 0x0121 361 - #define mmSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX 0 362 - #define mmSDMA0_PAGE_MIDCMD_DATA2 0x0122 363 - #define mmSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX 0 364 - #define mmSDMA0_PAGE_MIDCMD_DATA3 0x0123 365 - #define mmSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX 0 366 - #define mmSDMA0_PAGE_MIDCMD_DATA4 0x0124 367 - #define mmSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX 0 368 - #define mmSDMA0_PAGE_MIDCMD_DATA5 0x0125 369 - #define mmSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX 0 370 - #define mmSDMA0_PAGE_MIDCMD_DATA6 0x0126 371 - #define mmSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX 0 372 - #define mmSDMA0_PAGE_MIDCMD_DATA7 0x0127 373 - #define mmSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX 0 374 - #define mmSDMA0_PAGE_MIDCMD_DATA8 0x0128 375 - #define mmSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX 0 376 - #define mmSDMA0_PAGE_MIDCMD_CNTL 0x0129 377 - #define mmSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX 0 378 - #define mmSDMA0_RLC0_RB_CNTL 0x0140 379 - #define mmSDMA0_RLC0_RB_CNTL_BASE_IDX 0 380 - #define mmSDMA0_RLC0_RB_BASE 0x0141 381 - #define mmSDMA0_RLC0_RB_BASE_BASE_IDX 0 382 - #define mmSDMA0_RLC0_RB_BASE_HI 0x0142 383 - #define mmSDMA0_RLC0_RB_BASE_HI_BASE_IDX 0 384 - #define mmSDMA0_RLC0_RB_RPTR 0x0143 385 - #define mmSDMA0_RLC0_RB_RPTR_BASE_IDX 0 386 - #define mmSDMA0_RLC0_RB_RPTR_HI 0x0144 387 - #define mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX 0 388 - #define mmSDMA0_RLC0_RB_WPTR 0x0145 389 - #define mmSDMA0_RLC0_RB_WPTR_BASE_IDX 0 390 - #define mmSDMA0_RLC0_RB_WPTR_HI 0x0146 391 - #define mmSDMA0_RLC0_RB_WPTR_HI_BASE_IDX 0 392 - #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x0147 393 - #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 394 - #define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x0148 395 - #define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 396 - #define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x0149 397 - #define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 398 - #define mmSDMA0_RLC0_IB_CNTL 0x014a 399 - #define mmSDMA0_RLC0_IB_CNTL_BASE_IDX 0 400 - #define mmSDMA0_RLC0_IB_RPTR 0x014b 401 - #define mmSDMA0_RLC0_IB_RPTR_BASE_IDX 0 402 - #define mmSDMA0_RLC0_IB_OFFSET 0x014c 403 - #define mmSDMA0_RLC0_IB_OFFSET_BASE_IDX 0 404 - #define mmSDMA0_RLC0_IB_BASE_LO 0x014d 405 - #define mmSDMA0_RLC0_IB_BASE_LO_BASE_IDX 0 406 - #define mmSDMA0_RLC0_IB_BASE_HI 0x014e 407 - #define mmSDMA0_RLC0_IB_BASE_HI_BASE_IDX 0 408 - #define mmSDMA0_RLC0_IB_SIZE 0x014f 409 - #define mmSDMA0_RLC0_IB_SIZE_BASE_IDX 0 410 - #define mmSDMA0_RLC0_SKIP_CNTL 0x0150 411 - #define mmSDMA0_RLC0_SKIP_CNTL_BASE_IDX 0 412 - #define mmSDMA0_RLC0_CONTEXT_STATUS 0x0151 413 - #define mmSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX 0 414 - #define mmSDMA0_RLC0_DOORBELL 0x0152 415 - #define mmSDMA0_RLC0_DOORBELL_BASE_IDX 0 416 - #define mmSDMA0_RLC0_STATUS 0x0168 417 - #define mmSDMA0_RLC0_STATUS_BASE_IDX 0 418 - #define mmSDMA0_RLC0_DOORBELL_LOG 0x0169 419 - #define mmSDMA0_RLC0_DOORBELL_LOG_BASE_IDX 0 420 - #define mmSDMA0_RLC0_WATERMARK 0x016a 421 - #define mmSDMA0_RLC0_WATERMARK_BASE_IDX 0 422 - #define mmSDMA0_RLC0_DOORBELL_OFFSET 0x016b 423 - #define mmSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX 0 424 - #define mmSDMA0_RLC0_CSA_ADDR_LO 0x016c 425 - #define mmSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX 0 426 - #define mmSDMA0_RLC0_CSA_ADDR_HI 0x016d 427 - #define mmSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX 0 428 - #define mmSDMA0_RLC0_IB_SUB_REMAIN 0x016f 429 - #define mmSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX 0 430 - #define mmSDMA0_RLC0_PREEMPT 0x0170 431 - #define mmSDMA0_RLC0_PREEMPT_BASE_IDX 0 432 - #define mmSDMA0_RLC0_DUMMY_REG 0x0171 433 - #define mmSDMA0_RLC0_DUMMY_REG_BASE_IDX 0 434 - #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x0172 435 - #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 436 - #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x0173 437 - #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 438 - #define mmSDMA0_RLC0_RB_AQL_CNTL 0x0174 439 - #define mmSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX 0 440 - #define mmSDMA0_RLC0_MINOR_PTR_UPDATE 0x0175 441 - #define mmSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 442 - #define mmSDMA0_RLC0_MIDCMD_DATA0 0x0180 443 - #define mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX 0 444 - #define mmSDMA0_RLC0_MIDCMD_DATA1 0x0181 445 - #define mmSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX 0 446 - #define mmSDMA0_RLC0_MIDCMD_DATA2 0x0182 447 - #define mmSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX 0 448 - #define mmSDMA0_RLC0_MIDCMD_DATA3 0x0183 449 - #define mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX 0 450 - #define mmSDMA0_RLC0_MIDCMD_DATA4 0x0184 451 - #define mmSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX 0 452 - #define mmSDMA0_RLC0_MIDCMD_DATA5 0x0185 453 - #define mmSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX 0 454 - #define mmSDMA0_RLC0_MIDCMD_DATA6 0x0186 455 - #define mmSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX 0 456 - #define mmSDMA0_RLC0_MIDCMD_DATA7 0x0187 457 - #define mmSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX 0 458 - #define mmSDMA0_RLC0_MIDCMD_DATA8 0x0188 459 - #define mmSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX 0 460 - #define mmSDMA0_RLC0_MIDCMD_CNTL 0x0189 461 - #define mmSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX 0 462 - #define mmSDMA0_RLC1_RB_CNTL 0x01a0 463 - #define mmSDMA0_RLC1_RB_CNTL_BASE_IDX 0 464 - #define mmSDMA0_RLC1_RB_BASE 0x01a1 465 - #define mmSDMA0_RLC1_RB_BASE_BASE_IDX 0 466 - #define mmSDMA0_RLC1_RB_BASE_HI 0x01a2 467 - #define mmSDMA0_RLC1_RB_BASE_HI_BASE_IDX 0 468 - #define mmSDMA0_RLC1_RB_RPTR 0x01a3 469 - #define mmSDMA0_RLC1_RB_RPTR_BASE_IDX 0 470 - #define mmSDMA0_RLC1_RB_RPTR_HI 0x01a4 471 - #define mmSDMA0_RLC1_RB_RPTR_HI_BASE_IDX 0 472 - #define mmSDMA0_RLC1_RB_WPTR 0x01a5 473 - #define mmSDMA0_RLC1_RB_WPTR_BASE_IDX 0 474 - #define mmSDMA0_RLC1_RB_WPTR_HI 0x01a6 475 - #define mmSDMA0_RLC1_RB_WPTR_HI_BASE_IDX 0 476 - #define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x01a7 477 - #define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 478 - #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x01a8 479 - #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 480 - #define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x01a9 481 - #define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 482 - #define mmSDMA0_RLC1_IB_CNTL 0x01aa 483 - #define mmSDMA0_RLC1_IB_CNTL_BASE_IDX 0 484 - #define mmSDMA0_RLC1_IB_RPTR 0x01ab 485 - #define mmSDMA0_RLC1_IB_RPTR_BASE_IDX 0 486 - #define mmSDMA0_RLC1_IB_OFFSET 0x01ac 487 - #define mmSDMA0_RLC1_IB_OFFSET_BASE_IDX 0 488 - #define mmSDMA0_RLC1_IB_BASE_LO 0x01ad 489 - #define mmSDMA0_RLC1_IB_BASE_LO_BASE_IDX 0 490 - #define mmSDMA0_RLC1_IB_BASE_HI 0x01ae 491 - #define mmSDMA0_RLC1_IB_BASE_HI_BASE_IDX 0 492 - #define mmSDMA0_RLC1_IB_SIZE 0x01af 493 - #define mmSDMA0_RLC1_IB_SIZE_BASE_IDX 0 494 - #define mmSDMA0_RLC1_SKIP_CNTL 0x01b0 495 - #define mmSDMA0_RLC1_SKIP_CNTL_BASE_IDX 0 496 - #define mmSDMA0_RLC1_CONTEXT_STATUS 0x01b1 497 - #define mmSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX 0 498 - #define mmSDMA0_RLC1_DOORBELL 0x01b2 499 - #define mmSDMA0_RLC1_DOORBELL_BASE_IDX 0 500 - #define mmSDMA0_RLC1_STATUS 0x01c8 501 - #define mmSDMA0_RLC1_STATUS_BASE_IDX 0 502 - #define mmSDMA0_RLC1_DOORBELL_LOG 0x01c9 503 - #define mmSDMA0_RLC1_DOORBELL_LOG_BASE_IDX 0 504 - #define mmSDMA0_RLC1_WATERMARK 0x01ca 505 - #define mmSDMA0_RLC1_WATERMARK_BASE_IDX 0 506 - #define mmSDMA0_RLC1_DOORBELL_OFFSET 0x01cb 507 - #define mmSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX 0 508 - #define mmSDMA0_RLC1_CSA_ADDR_LO 0x01cc 509 - #define mmSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX 0 510 - #define mmSDMA0_RLC1_CSA_ADDR_HI 0x01cd 511 - #define mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX 0 512 - #define mmSDMA0_RLC1_IB_SUB_REMAIN 0x01cf 513 - #define mmSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX 0 514 - #define mmSDMA0_RLC1_PREEMPT 0x01d0 515 - #define mmSDMA0_RLC1_PREEMPT_BASE_IDX 0 516 - #define mmSDMA0_RLC1_DUMMY_REG 0x01d1 517 - #define mmSDMA0_RLC1_DUMMY_REG_BASE_IDX 0 518 - #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x01d2 519 - #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 520 - #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x01d3 521 - #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 522 - #define mmSDMA0_RLC1_RB_AQL_CNTL 0x01d4 523 - #define mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX 0 524 - #define mmSDMA0_RLC1_MINOR_PTR_UPDATE 0x01d5 525 - #define mmSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 526 - #define mmSDMA0_RLC1_MIDCMD_DATA0 0x01e0 527 - #define mmSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX 0 528 - #define mmSDMA0_RLC1_MIDCMD_DATA1 0x01e1 529 - #define mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX 0 530 - #define mmSDMA0_RLC1_MIDCMD_DATA2 0x01e2 531 - #define mmSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX 0 532 - #define mmSDMA0_RLC1_MIDCMD_DATA3 0x01e3 533 - #define mmSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX 0 534 - #define mmSDMA0_RLC1_MIDCMD_DATA4 0x01e4 535 - #define mmSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX 0 536 - #define mmSDMA0_RLC1_MIDCMD_DATA5 0x01e5 537 - #define mmSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX 0 538 - #define mmSDMA0_RLC1_MIDCMD_DATA6 0x01e6 539 - #define mmSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX 0 540 - #define mmSDMA0_RLC1_MIDCMD_DATA7 0x01e7 541 - #define mmSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX 0 542 - #define mmSDMA0_RLC1_MIDCMD_DATA8 0x01e8 543 - #define mmSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX 0 544 - #define mmSDMA0_RLC1_MIDCMD_CNTL 0x01e9 545 - #define mmSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX 0 546 - 547 - #endif
-1852
drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h
··· 1 - /* 2 - * Copyright (C) 2017 Advanced Micro Devices, Inc. 3 - * 4 - * Permission is hereby granted, free of charge, to any person obtaining a 5 - * copy of this software and associated documentation files (the "Software"), 6 - * to deal in the Software without restriction, including without limitation 7 - * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 - * and/or sell copies of the Software, and to permit persons to whom the 9 - * Software is furnished to do so, subject to the following conditions: 10 - * 11 - * The above copyright notice and this permission notice shall be included 12 - * in all copies or substantial portions of the Software. 13 - * 14 - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 - */ 21 - #ifndef _sdma0_4_0_SH_MASK_HEADER 22 - #define _sdma0_4_0_SH_MASK_HEADER 23 - 24 - 25 - // addressBlock: sdma0_sdma0dec 26 - //SDMA0_UCODE_ADDR 27 - #define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 28 - #define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL 29 - //SDMA0_UCODE_DATA 30 - #define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 31 - #define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 32 - //SDMA0_VM_CNTL 33 - #define SDMA0_VM_CNTL__CMD__SHIFT 0x0 34 - #define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL 35 - //SDMA0_VM_CTX_LO 36 - #define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 37 - #define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL 38 - //SDMA0_VM_CTX_HI 39 - #define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 40 - #define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL 41 - //SDMA0_ACTIVE_FCN_ID 42 - #define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 43 - #define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 44 - #define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f 45 - #define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 46 - #define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L 47 - #define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L 48 - //SDMA0_VM_CTX_CNTL 49 - #define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 50 - #define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 51 - #define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L 52 - #define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L 53 - //SDMA0_VIRT_RESET_REQ 54 - #define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 55 - #define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f 56 - #define SDMA0_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 57 - #define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L 58 - //SDMA0_VF_ENABLE 59 - #define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0 60 - #define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x00000001L 61 - //SDMA0_CONTEXT_REG_TYPE0 62 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 63 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 64 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 65 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 66 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4 67 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5 68 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6 69 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 70 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 71 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 72 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa 73 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb 74 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc 75 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd 76 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe 77 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf 78 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 79 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 80 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 81 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 82 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L 83 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L 84 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L 85 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L 86 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L 87 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L 88 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L 89 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L 90 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L 91 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L 92 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L 93 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L 94 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L 95 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L 96 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L 97 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L 98 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L 99 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L 100 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L 101 - #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L 102 - //SDMA0_CONTEXT_REG_TYPE1 103 - #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8 104 - #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9 105 - #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa 106 - #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb 107 - #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc 108 - #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd 109 - #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe 110 - #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf 111 - #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 112 - #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 113 - #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 114 - #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 115 - #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14 116 - #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 117 - #define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 118 - #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L 119 - #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x00000200L 120 - #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L 121 - #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L 122 - #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L 123 - #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L 124 - #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L 125 - #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L 126 - #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L 127 - #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L 128 - #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L 129 - #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L 130 - #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L 131 - #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L 132 - #define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L 133 - //SDMA0_CONTEXT_REG_TYPE2 134 - #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 135 - #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 136 - #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 137 - #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 138 - #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 139 - #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 140 - #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6 141 - #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7 142 - #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8 143 - #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9 144 - #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa 145 - #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L 146 - #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L 147 - #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L 148 - #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L 149 - #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L 150 - #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L 151 - #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L 152 - #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L 153 - #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L 154 - #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L 155 - #define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L 156 - //SDMA0_CONTEXT_REG_TYPE3 157 - #define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 158 - #define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL 159 - //SDMA0_PUB_REG_TYPE0 160 - #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 161 - #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 162 - #define SDMA0_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 163 - #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT 0x4 164 - #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT 0x5 165 - #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT 0x6 166 - #define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT 0x7 167 - #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT 0x8 168 - #define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT 0x9 169 - #define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa 170 - #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT 0xb 171 - #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT 0xc 172 - #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT 0xd 173 - #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT 0xe 174 - #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT 0xf 175 - #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT 0x10 176 - #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT 0x11 177 - #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT 0x12 178 - #define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL__SHIFT 0x13 179 - #define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 180 - #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 181 - #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x1a 182 - #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x1b 183 - #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x1c 184 - #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d 185 - #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x1e 186 - #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x1f 187 - #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L 188 - #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L 189 - #define SDMA0_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L 190 - #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK 0x00000010L 191 - #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK 0x00000020L 192 - #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK 0x00000040L 193 - #define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK 0x00000080L 194 - #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK 0x00000100L 195 - #define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK 0x00000200L 196 - #define SDMA0_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L 197 - #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK 0x00000800L 198 - #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK 0x00001000L 199 - #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK 0x00002000L 200 - #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK 0x00004000L 201 - #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK 0x00008000L 202 - #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK 0x00010000L 203 - #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK 0x00020000L 204 - #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK 0x00040000L 205 - #define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL_MASK 0x00080000L 206 - #define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L 207 - #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L 208 - #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L 209 - #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x08000000L 210 - #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L 211 - #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L 212 - #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L 213 - #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L 214 - //SDMA0_PUB_REG_TYPE1 215 - #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x0 216 - #define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 217 - #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x2 218 - #define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x3 219 - #define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x4 220 - #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x5 221 - #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x6 222 - #define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT 0x7 223 - #define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x8 224 - #define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x9 225 - #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa 226 - #define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0xb 227 - #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT 0xc 228 - #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT 0xd 229 - #define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe 230 - #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf 231 - #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 232 - #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 233 - #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x12 234 - #define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x13 235 - #define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x14 236 - #define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x15 237 - #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x16 238 - #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x17 239 - #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x18 240 - #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x19 241 - #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x1a 242 - #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x1b 243 - #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x1c 244 - #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d 245 - #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT 0x1e 246 - #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT 0x1f 247 - #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000001L 248 - #define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L 249 - #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000004L 250 - #define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L 251 - #define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L 252 - #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L 253 - #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L 254 - #define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK 0x00000080L 255 - #define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L 256 - #define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L 257 - #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK 0x00000400L 258 - #define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L 259 - #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK 0x00001000L 260 - #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK 0x00002000L 261 - #define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L 262 - #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L 263 - #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L 264 - #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L 265 - #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L 266 - #define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L 267 - #define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L 268 - #define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L 269 - #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L 270 - #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L 271 - #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L 272 - #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L 273 - #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L 274 - #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L 275 - #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L 276 - #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L 277 - #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK 0x40000000L 278 - #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK 0x80000000L 279 - //SDMA0_PUB_REG_TYPE2 280 - #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x0 281 - #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x1 282 - #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x2 283 - #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x3 284 - #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x4 285 - #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x5 286 - #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x6 287 - #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT 0x7 288 - #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT 0x8 289 - #define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE__SHIFT 0x9 290 - #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa 291 - #define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0xb 292 - #define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0xc 293 - #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0xd 294 - #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0xe 295 - #define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM__SHIFT 0xf 296 - #define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x10 297 - #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x11 298 - #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x12 299 - #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x13 300 - #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x14 301 - #define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x15 302 - #define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE__SHIFT 0x16 303 - #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL__SHIFT 0x17 304 - #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x18 305 - #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x19 306 - #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a 307 - #define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x1b 308 - #define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL__SHIFT 0x1c 309 - #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d 310 - #define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL__SHIFT 0x1e 311 - #define SDMA0_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f 312 - #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000001L 313 - #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000002L 314 - #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000004L 315 - #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000008L 316 - #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000010L 317 - #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000020L 318 - #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000040L 319 - #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK 0x00000080L 320 - #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK 0x00000100L 321 - #define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE_MASK 0x00000200L 322 - #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L 323 - #define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L 324 - #define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L 325 - #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L 326 - #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L 327 - #define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM_MASK 0x00008000L 328 - #define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L 329 - #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L 330 - #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L 331 - #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L 332 - #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L 333 - #define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L 334 - #define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE_MASK 0x00400000L 335 - #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL_MASK 0x00800000L 336 - #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT_MASK 0x01000000L 337 - #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT_MASK 0x02000000L 338 - #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L 339 - #define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L 340 - #define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL_MASK 0x10000000L 341 - #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L 342 - #define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL_MASK 0x40000000L 343 - #define SDMA0_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L 344 - //SDMA0_PUB_REG_TYPE3 345 - #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x0 346 - #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x1 347 - #define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x2 348 - #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L 349 - #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L 350 - #define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL 351 - //SDMA0_MMHUB_CNTL 352 - #define SDMA0_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 353 - #define SDMA0_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL 354 - //SDMA0_CONTEXT_GROUP_BOUNDARY 355 - #define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 356 - #define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL 357 - //SDMA0_POWER_CNTL 358 - #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 359 - #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 360 - #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 361 - #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 362 - #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 363 - #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 364 - #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 365 - #define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 366 - #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L 367 - #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L 368 - #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L 369 - #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L 370 - #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L 371 - #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L 372 - #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L 373 - #define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L 374 - //SDMA0_CLK_CTRL 375 - #define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 376 - #define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 377 - #define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc 378 - #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 379 - #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 380 - #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 381 - #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 382 - #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 383 - #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 384 - #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 385 - #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 386 - #define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 387 - #define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 388 - #define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L 389 - #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 390 - #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 391 - #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 392 - #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 393 - #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 394 - #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 395 - #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 396 - #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 397 - //SDMA0_CNTL 398 - #define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 399 - #define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1 400 - #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 401 - #define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 402 - #define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 403 - #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 404 - #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 405 - #define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 406 - #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 407 - #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 408 - #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 409 - #define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L 410 - #define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L 411 - #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L 412 - #define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L 413 - #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L 414 - #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L 415 - #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 416 - #define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L 417 - #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L 418 - #define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L 419 - #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L 420 - //SDMA0_CHICKEN_BITS 421 - #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 422 - #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 423 - #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 424 - #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 425 - #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 426 - #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 427 - #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 428 - #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 429 - #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 430 - #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 431 - #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a 432 - #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c 433 - #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e 434 - #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L 435 - #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L 436 - #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L 437 - #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L 438 - #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L 439 - #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L 440 - #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L 441 - #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L 442 - #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L 443 - #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L 444 - #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L 445 - #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L 446 - #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L 447 - //SDMA0_GB_ADDR_CONFIG 448 - #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 449 - #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 450 - #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 451 - #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 452 - #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 453 - #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 454 - #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 455 - #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 456 - #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 457 - #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 458 - //SDMA0_GB_ADDR_CONFIG_READ 459 - #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 460 - #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 461 - #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 462 - #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc 463 - #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 464 - #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 465 - #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 466 - #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 467 - #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L 468 - #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 469 - //SDMA0_RB_RPTR_FETCH_HI 470 - #define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 471 - #define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 472 - //SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 473 - #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 474 - #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL 475 - //SDMA0_RB_RPTR_FETCH 476 - #define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 477 - #define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 478 - //SDMA0_IB_OFFSET_FETCH 479 - #define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 480 - #define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 481 - //SDMA0_PROGRAM 482 - #define SDMA0_PROGRAM__STREAM__SHIFT 0x0 483 - #define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL 484 - //SDMA0_STATUS_REG 485 - #define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 486 - #define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 487 - #define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 488 - #define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 489 - #define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 490 - #define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 491 - #define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 492 - #define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 493 - #define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 494 - #define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 495 - #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa 496 - #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 497 - #define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc 498 - #define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 499 - #define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe 500 - #define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 501 - #define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 502 - #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 503 - #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 504 - #define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 505 - #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 506 - #define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 507 - #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 508 - #define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 509 - #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a 510 - #define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 511 - #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 512 - #define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e 513 - #define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 514 - #define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L 515 - #define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L 516 - #define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L 517 - #define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L 518 - #define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L 519 - #define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L 520 - #define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L 521 - #define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L 522 - #define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L 523 - #define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L 524 - #define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L 525 - #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L 526 - #define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L 527 - #define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L 528 - #define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L 529 - #define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L 530 - #define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L 531 - #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L 532 - #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L 533 - #define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L 534 - #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L 535 - #define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L 536 - #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L 537 - #define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L 538 - #define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L 539 - #define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L 540 - #define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L 541 - #define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L 542 - #define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L 543 - //SDMA0_STATUS1_REG 544 - #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 545 - #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 546 - #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 547 - #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 548 - #define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 549 - #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 550 - #define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 551 - #define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 552 - #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 553 - #define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 554 - #define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 555 - #define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf 556 - #define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 557 - #define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 558 - #define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L 559 - #define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L 560 - #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L 561 - #define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L 562 - #define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L 563 - #define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L 564 - #define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L 565 - #define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L 566 - #define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L 567 - #define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L 568 - #define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L 569 - #define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L 570 - #define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L 571 - #define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L 572 - //SDMA0_RD_BURST_CNTL 573 - #define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 574 - #define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L 575 - //SDMA0_HBM_PAGE_CONFIG 576 - #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 577 - #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L 578 - //SDMA0_UCODE_CHECKSUM 579 - #define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0 580 - #define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 581 - //SDMA0_F32_CNTL 582 - #define SDMA0_F32_CNTL__HALT__SHIFT 0x0 583 - #define SDMA0_F32_CNTL__STEP__SHIFT 0x1 584 - #define SDMA0_F32_CNTL__HALT_MASK 0x00000001L 585 - #define SDMA0_F32_CNTL__STEP_MASK 0x00000002L 586 - //SDMA0_FREEZE 587 - #define SDMA0_FREEZE__PREEMPT__SHIFT 0x0 588 - #define SDMA0_FREEZE__FREEZE__SHIFT 0x4 589 - #define SDMA0_FREEZE__FROZEN__SHIFT 0x5 590 - #define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 591 - #define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L 592 - #define SDMA0_FREEZE__FREEZE_MASK 0x00000010L 593 - #define SDMA0_FREEZE__FROZEN_MASK 0x00000020L 594 - #define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L 595 - //SDMA0_PHASE0_QUANTUM 596 - #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 597 - #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 598 - #define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 599 - #define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL 600 - #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L 601 - #define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L 602 - //SDMA0_PHASE1_QUANTUM 603 - #define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 604 - #define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 605 - #define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 606 - #define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL 607 - #define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L 608 - #define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L 609 - //SDMA_POWER_GATING 610 - #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0 611 - #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1 612 - #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2 613 - #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3 614 - #define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 615 - #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L 616 - #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L 617 - #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L 618 - #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L 619 - #define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L 620 - //SDMA_PGFSM_CONFIG 621 - #define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 622 - #define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 623 - #define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 624 - #define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa 625 - #define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb 626 - #define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc 627 - #define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd 628 - #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b 629 - #define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c 630 - #define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL 631 - #define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L 632 - #define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L 633 - #define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L 634 - #define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L 635 - #define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L 636 - #define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L 637 - #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L 638 - #define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L 639 - //SDMA_PGFSM_WRITE 640 - #define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 641 - #define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL 642 - //SDMA_PGFSM_READ 643 - #define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 644 - #define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL 645 - //SDMA0_EDC_CONFIG 646 - #define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 647 - #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 648 - #define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 649 - #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L 650 - //SDMA0_BA_THRESHOLD 651 - #define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 652 - #define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 653 - #define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL 654 - #define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L 655 - //SDMA0_ID 656 - #define SDMA0_ID__DEVICE_ID__SHIFT 0x0 657 - #define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL 658 - //SDMA0_VERSION 659 - #define SDMA0_VERSION__MINVER__SHIFT 0x0 660 - #define SDMA0_VERSION__MAJVER__SHIFT 0x8 661 - #define SDMA0_VERSION__REV__SHIFT 0x10 662 - #define SDMA0_VERSION__MINVER_MASK 0x0000007FL 663 - #define SDMA0_VERSION__MAJVER_MASK 0x00007F00L 664 - #define SDMA0_VERSION__REV_MASK 0x003F0000L 665 - //SDMA0_EDC_COUNTER 666 - #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 667 - #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 668 - #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 669 - #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 670 - #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 671 - #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 672 - #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 673 - #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 674 - #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 675 - #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 676 - #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa 677 - #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb 678 - #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc 679 - #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd 680 - #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe 681 - #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf 682 - #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 683 - #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L 684 - #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L 685 - #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L 686 - #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L 687 - #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L 688 - #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L 689 - #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L 690 - #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L 691 - #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L 692 - #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L 693 - #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L 694 - #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L 695 - #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L 696 - #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L 697 - #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L 698 - #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L 699 - #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L 700 - //SDMA0_EDC_COUNTER_CLEAR 701 - #define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 702 - #define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L 703 - //SDMA0_STATUS2_REG 704 - #define SDMA0_STATUS2_REG__ID__SHIFT 0x0 705 - #define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 706 - #define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 707 - #define SDMA0_STATUS2_REG__ID_MASK 0x00000003L 708 - #define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL 709 - #define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L 710 - //SDMA0_ATOMIC_CNTL 711 - #define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 712 - #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 713 - #define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 714 - #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L 715 - //SDMA0_ATOMIC_PREOP_LO 716 - #define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 717 - #define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 718 - //SDMA0_ATOMIC_PREOP_HI 719 - #define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 720 - #define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 721 - //SDMA0_UTCL1_CNTL 722 - #define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 723 - #define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 724 - #define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb 725 - #define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe 726 - #define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 727 - #define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d 728 - #define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L 729 - #define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL 730 - #define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L 731 - #define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L 732 - #define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L 733 - #define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L 734 - //SDMA0_UTCL1_WATERMK 735 - #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 736 - #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa 737 - #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 738 - #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a 739 - #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL 740 - #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L 741 - #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L 742 - #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L 743 - //SDMA0_UTCL1_RD_STATUS 744 - #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 745 - #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 746 - #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 747 - #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 748 - #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 749 - #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 750 - #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 751 - #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 752 - #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 753 - #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 754 - #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 755 - #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 756 - #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 757 - #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 758 - #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 759 - #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 760 - #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 761 - #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 762 - #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 763 - #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 764 - #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 765 - #define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 766 - #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 767 - #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 768 - #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d 769 - #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e 770 - #define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f 771 - #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 772 - #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 773 - #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 774 - #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 775 - #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 776 - #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 777 - #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 778 - #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 779 - #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 780 - #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 781 - #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 782 - #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 783 - #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 784 - #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 785 - #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 786 - #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 787 - #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 788 - #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 789 - #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L 790 - #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L 791 - #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L 792 - #define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L 793 - #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L 794 - #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L 795 - #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L 796 - #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L 797 - #define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L 798 - //SDMA0_UTCL1_WR_STATUS 799 - #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 800 - #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 801 - #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 802 - #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 803 - #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 804 - #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 805 - #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 806 - #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 807 - #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 808 - #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 809 - #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 810 - #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 811 - #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 812 - #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 813 - #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 814 - #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 815 - #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 816 - #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 817 - #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 818 - #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 819 - #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 820 - #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 821 - #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 822 - #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 823 - #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c 824 - #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d 825 - #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e 826 - #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f 827 - #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 828 - #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 829 - #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 830 - #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 831 - #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 832 - #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 833 - #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 834 - #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 835 - #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 836 - #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 837 - #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 838 - #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 839 - #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 840 - #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 841 - #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 842 - #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 843 - #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 844 - #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 845 - #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L 846 - #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L 847 - #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L 848 - #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L 849 - #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L 850 - #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L 851 - #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L 852 - #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L 853 - #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L 854 - #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L 855 - //SDMA0_UTCL1_INV0 856 - #define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 857 - #define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 858 - #define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 859 - #define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 860 - #define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 861 - #define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 862 - #define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 863 - #define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 864 - #define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 865 - #define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 866 - #define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa 867 - #define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 868 - #define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc 869 - #define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 870 - #define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L 871 - #define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L 872 - #define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L 873 - #define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L 874 - #define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L 875 - #define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L 876 - #define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L 877 - #define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L 878 - #define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L 879 - #define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L 880 - #define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L 881 - #define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L 882 - #define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L 883 - #define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L 884 - //SDMA0_UTCL1_INV1 885 - #define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 886 - #define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL 887 - //SDMA0_UTCL1_INV2 888 - #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 889 - #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL 890 - //SDMA0_UTCL1_RD_XNACK0 891 - #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 892 - #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 893 - //SDMA0_UTCL1_RD_XNACK1 894 - #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 895 - #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 896 - #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 897 - #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a 898 - #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 899 - #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L 900 - #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 901 - #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L 902 - //SDMA0_UTCL1_WR_XNACK0 903 - #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 904 - #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 905 - //SDMA0_UTCL1_WR_XNACK1 906 - #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 907 - #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 908 - #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 909 - #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a 910 - #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 911 - #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L 912 - #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 913 - #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L 914 - //SDMA0_UTCL1_TIMEOUT 915 - #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 916 - #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 917 - #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL 918 - #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L 919 - //SDMA0_UTCL1_PAGE 920 - #define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 921 - #define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 922 - #define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 923 - #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 924 - #define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L 925 - #define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL 926 - #define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L 927 - #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L 928 - //SDMA0_POWER_CNTL_IDLE 929 - #define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 930 - #define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 931 - #define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 932 - #define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL 933 - #define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L 934 - #define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L 935 - //SDMA0_RELAX_ORDERING_LUT 936 - #define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 937 - #define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 938 - #define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 939 - #define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 940 - #define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 941 - #define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 942 - #define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 943 - #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 944 - #define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 945 - #define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 946 - #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb 947 - #define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc 948 - #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 949 - #define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 950 - #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 951 - #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 952 - #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d 953 - #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 954 - #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 955 - #define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 956 - #define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L 957 - #define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L 958 - #define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 959 - #define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 960 - #define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 961 - #define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 962 - #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 963 - #define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 964 - #define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 965 - #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L 966 - #define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L 967 - #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 968 - #define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 969 - #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 970 - #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 971 - #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L 972 - #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 973 - #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 974 - //SDMA0_CHICKEN_BITS_2 975 - #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 976 - #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 977 - //SDMA0_STATUS3_REG 978 - #define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 979 - #define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 980 - #define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 981 - #define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL 982 - #define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L 983 - #define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L 984 - //SDMA0_PHYSICAL_ADDR_LO 985 - #define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 986 - #define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 987 - #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 988 - #define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc 989 - #define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L 990 - #define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L 991 - #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L 992 - #define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L 993 - //SDMA0_PHYSICAL_ADDR_HI 994 - #define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 995 - #define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL 996 - //SDMA0_PHASE2_QUANTUM 997 - #define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT 0x0 998 - #define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT 0x8 999 - #define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT 0x1e 1000 - #define SDMA0_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL 1001 - #define SDMA0_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L 1002 - #define SDMA0_PHASE2_QUANTUM__PREFER_MASK 0x40000000L 1003 - //SDMA0_ERROR_LOG 1004 - #define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0 1005 - #define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10 1006 - #define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 1007 - #define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L 1008 - //SDMA0_PUB_DUMMY_REG0 1009 - #define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 1010 - #define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL 1011 - //SDMA0_PUB_DUMMY_REG1 1012 - #define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 1013 - #define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL 1014 - //SDMA0_PUB_DUMMY_REG2 1015 - #define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 1016 - #define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL 1017 - //SDMA0_PUB_DUMMY_REG3 1018 - #define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 1019 - #define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL 1020 - //SDMA0_F32_COUNTER 1021 - #define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0 1022 - #define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 1023 - //SDMA0_UNBREAKABLE 1024 - #define SDMA0_UNBREAKABLE__VALUE__SHIFT 0x0 1025 - #define SDMA0_UNBREAKABLE__VALUE_MASK 0x00000001L 1026 - //SDMA0_PERFMON_CNTL 1027 - #define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 1028 - #define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 1029 - #define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 1030 - #define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa 1031 - #define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb 1032 - #define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc 1033 - #define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L 1034 - #define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L 1035 - #define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL 1036 - #define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L 1037 - #define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L 1038 - #define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L 1039 - //SDMA0_PERFCOUNTER0_RESULT 1040 - #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 1041 - #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1042 - //SDMA0_PERFCOUNTER1_RESULT 1043 - #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 1044 - #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1045 - //SDMA0_PERFCOUNTER_TAG_DELAY_RANGE 1046 - #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 1047 - #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe 1048 - #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c 1049 - #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL 1050 - #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L 1051 - #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L 1052 - //SDMA0_CRD_CNTL 1053 - #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 1054 - #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 1055 - #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 1056 - #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 1057 - //SDMA0_MMHUB_TRUSTLVL 1058 - #define SDMA0_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0 1059 - #define SDMA0_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x3 1060 - #define SDMA0_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x6 1061 - #define SDMA0_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x9 1062 - #define SDMA0_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0xc 1063 - #define SDMA0_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0xf 1064 - #define SDMA0_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x12 1065 - #define SDMA0_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x15 1066 - #define SDMA0_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L 1067 - #define SDMA0_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L 1068 - #define SDMA0_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001C0L 1069 - #define SDMA0_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000E00L 1070 - #define SDMA0_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L 1071 - #define SDMA0_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L 1072 - #define SDMA0_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001C0000L 1073 - #define SDMA0_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00E00000L 1074 - //SDMA0_GPU_IOV_VIOLATION_LOG 1075 - #define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 1076 - #define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 1077 - #define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 1078 - #define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12 1079 - #define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 1080 - #define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 1081 - #define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 1082 - #define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 1083 - #define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 1084 - #define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL 1085 - #define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L 1086 - #define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L 1087 - #define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L 1088 - #define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L 1089 - //SDMA0_ULV_CNTL 1090 - #define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0 1091 - #define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d 1092 - #define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e 1093 - #define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f 1094 - #define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL 1095 - #define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L 1096 - #define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L 1097 - #define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L 1098 - //SDMA0_EA_DBIT_ADDR_DATA 1099 - #define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 1100 - #define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL 1101 - //SDMA0_EA_DBIT_ADDR_INDEX 1102 - #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 1103 - #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L 1104 - //SDMA0_GFX_RB_CNTL 1105 - #define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 1106 - #define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 1107 - #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1108 - #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1109 - #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1110 - #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1111 - #define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 1112 - #define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 1113 - #define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1114 - #define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1115 - #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1116 - #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1117 - #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1118 - #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1119 - #define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L 1120 - #define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L 1121 - //SDMA0_GFX_RB_BASE 1122 - #define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 1123 - #define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1124 - //SDMA0_GFX_RB_BASE_HI 1125 - #define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 1126 - #define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1127 - //SDMA0_GFX_RB_RPTR 1128 - #define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0 1129 - #define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1130 - //SDMA0_GFX_RB_RPTR_HI 1131 - #define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 1132 - #define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1133 - //SDMA0_GFX_RB_WPTR 1134 - #define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0 1135 - #define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1136 - //SDMA0_GFX_RB_WPTR_HI 1137 - #define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 1138 - #define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1139 - //SDMA0_GFX_RB_WPTR_POLL_CNTL 1140 - #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1141 - #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1142 - #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1143 - #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1144 - #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1145 - #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1146 - #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1147 - #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1148 - #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1149 - #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1150 - //SDMA0_GFX_RB_RPTR_ADDR_HI 1151 - #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1152 - #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1153 - //SDMA0_GFX_RB_RPTR_ADDR_LO 1154 - #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1155 - #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1156 - //SDMA0_GFX_IB_CNTL 1157 - #define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 1158 - #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1159 - #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1160 - #define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 1161 - #define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1162 - #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1163 - #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1164 - #define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1165 - //SDMA0_GFX_IB_RPTR 1166 - #define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 1167 - #define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1168 - //SDMA0_GFX_IB_OFFSET 1169 - #define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 1170 - #define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1171 - //SDMA0_GFX_IB_BASE_LO 1172 - #define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 1173 - #define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1174 - //SDMA0_GFX_IB_BASE_HI 1175 - #define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 1176 - #define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1177 - //SDMA0_GFX_IB_SIZE 1178 - #define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 1179 - #define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL 1180 - //SDMA0_GFX_SKIP_CNTL 1181 - #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1182 - #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1183 - //SDMA0_GFX_CONTEXT_STATUS 1184 - #define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1185 - #define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 1186 - #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1187 - #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1188 - #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1189 - #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1190 - #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1191 - #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1192 - #define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1193 - #define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1194 - #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1195 - #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1196 - #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1197 - #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1198 - #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1199 - #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1200 - //SDMA0_GFX_DOORBELL 1201 - #define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c 1202 - #define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 1203 - #define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L 1204 - #define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L 1205 - //SDMA0_GFX_CONTEXT_CNTL 1206 - #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 1207 - #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L 1208 - //SDMA0_GFX_STATUS 1209 - #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1210 - #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1211 - #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1212 - #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1213 - //SDMA0_GFX_DOORBELL_LOG 1214 - #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1215 - #define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 1216 - #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1217 - #define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1218 - //SDMA0_GFX_WATERMARK 1219 - #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1220 - #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1221 - #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1222 - #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1223 - //SDMA0_GFX_DOORBELL_OFFSET 1224 - #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1225 - #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1226 - //SDMA0_GFX_CSA_ADDR_LO 1227 - #define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 1228 - #define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1229 - //SDMA0_GFX_CSA_ADDR_HI 1230 - #define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 1231 - #define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1232 - //SDMA0_GFX_IB_SUB_REMAIN 1233 - #define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1234 - #define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1235 - //SDMA0_GFX_PREEMPT 1236 - #define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 1237 - #define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1238 - //SDMA0_GFX_DUMMY_REG 1239 - #define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 1240 - #define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1241 - //SDMA0_GFX_RB_WPTR_POLL_ADDR_HI 1242 - #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1243 - #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1244 - //SDMA0_GFX_RB_WPTR_POLL_ADDR_LO 1245 - #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1246 - #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1247 - //SDMA0_GFX_RB_AQL_CNTL 1248 - #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1249 - #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1250 - #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1251 - #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1252 - #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1253 - #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1254 - //SDMA0_GFX_MINOR_PTR_UPDATE 1255 - #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1256 - #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1257 - //SDMA0_GFX_MIDCMD_DATA0 1258 - #define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 1259 - #define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1260 - //SDMA0_GFX_MIDCMD_DATA1 1261 - #define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 1262 - #define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1263 - //SDMA0_GFX_MIDCMD_DATA2 1264 - #define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 1265 - #define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1266 - //SDMA0_GFX_MIDCMD_DATA3 1267 - #define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 1268 - #define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1269 - //SDMA0_GFX_MIDCMD_DATA4 1270 - #define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 1271 - #define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1272 - //SDMA0_GFX_MIDCMD_DATA5 1273 - #define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 1274 - #define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1275 - //SDMA0_GFX_MIDCMD_DATA6 1276 - #define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 1277 - #define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1278 - //SDMA0_GFX_MIDCMD_DATA7 1279 - #define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 1280 - #define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1281 - //SDMA0_GFX_MIDCMD_DATA8 1282 - #define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 1283 - #define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1284 - //SDMA0_GFX_MIDCMD_CNTL 1285 - #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1286 - #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1287 - #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1288 - #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1289 - #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1290 - #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1291 - #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1292 - #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1293 - //SDMA0_PAGE_RB_CNTL 1294 - #define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 1295 - #define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 1296 - #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1297 - #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1298 - #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1299 - #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1300 - #define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 1301 - #define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 1302 - #define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1303 - #define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1304 - #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1305 - #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1306 - #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1307 - #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1308 - #define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L 1309 - #define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L 1310 - //SDMA0_PAGE_RB_BASE 1311 - #define SDMA0_PAGE_RB_BASE__ADDR__SHIFT 0x0 1312 - #define SDMA0_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1313 - //SDMA0_PAGE_RB_BASE_HI 1314 - #define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 1315 - #define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1316 - //SDMA0_PAGE_RB_RPTR 1317 - #define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 1318 - #define SDMA0_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1319 - //SDMA0_PAGE_RB_RPTR_HI 1320 - #define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 1321 - #define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1322 - //SDMA0_PAGE_RB_WPTR 1323 - #define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 1324 - #define SDMA0_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1325 - //SDMA0_PAGE_RB_WPTR_HI 1326 - #define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 1327 - #define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1328 - //SDMA0_PAGE_RB_WPTR_POLL_CNTL 1329 - #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1330 - #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1331 - #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1332 - #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1333 - #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1334 - #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1335 - #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1336 - #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1337 - #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1338 - #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1339 - //SDMA0_PAGE_RB_RPTR_ADDR_HI 1340 - #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1341 - #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1342 - //SDMA0_PAGE_RB_RPTR_ADDR_LO 1343 - #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1344 - #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1345 - //SDMA0_PAGE_IB_CNTL 1346 - #define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 1347 - #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1348 - #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1349 - #define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 1350 - #define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1351 - #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1352 - #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1353 - #define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1354 - //SDMA0_PAGE_IB_RPTR 1355 - #define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 1356 - #define SDMA0_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1357 - //SDMA0_PAGE_IB_OFFSET 1358 - #define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 1359 - #define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1360 - //SDMA0_PAGE_IB_BASE_LO 1361 - #define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 1362 - #define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1363 - //SDMA0_PAGE_IB_BASE_HI 1364 - #define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 1365 - #define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1366 - //SDMA0_PAGE_IB_SIZE 1367 - #define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT 0x0 1368 - #define SDMA0_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL 1369 - //SDMA0_PAGE_SKIP_CNTL 1370 - #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1371 - #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1372 - //SDMA0_PAGE_CONTEXT_STATUS 1373 - #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1374 - #define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 1375 - #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1376 - #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1377 - #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1378 - #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1379 - #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1380 - #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1381 - #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1382 - #define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1383 - #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1384 - #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1385 - #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1386 - #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1387 - #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1388 - #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1389 - //SDMA0_PAGE_DOORBELL 1390 - #define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT 0x1c 1391 - #define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e 1392 - #define SDMA0_PAGE_DOORBELL__ENABLE_MASK 0x10000000L 1393 - #define SDMA0_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L 1394 - //SDMA0_PAGE_STATUS 1395 - #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1396 - #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1397 - #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1398 - #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1399 - //SDMA0_PAGE_DOORBELL_LOG 1400 - #define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1401 - #define SDMA0_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 1402 - #define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1403 - #define SDMA0_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1404 - //SDMA0_PAGE_WATERMARK 1405 - #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1406 - #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1407 - #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1408 - #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1409 - //SDMA0_PAGE_DOORBELL_OFFSET 1410 - #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1411 - #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1412 - //SDMA0_PAGE_CSA_ADDR_LO 1413 - #define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 1414 - #define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1415 - //SDMA0_PAGE_CSA_ADDR_HI 1416 - #define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 1417 - #define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1418 - //SDMA0_PAGE_IB_SUB_REMAIN 1419 - #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1420 - #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1421 - //SDMA0_PAGE_PREEMPT 1422 - #define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 1423 - #define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1424 - //SDMA0_PAGE_DUMMY_REG 1425 - #define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 1426 - #define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1427 - //SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 1428 - #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1429 - #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1430 - //SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 1431 - #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1432 - #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1433 - //SDMA0_PAGE_RB_AQL_CNTL 1434 - #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1435 - #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1436 - #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1437 - #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1438 - #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1439 - #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1440 - //SDMA0_PAGE_MINOR_PTR_UPDATE 1441 - #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1442 - #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1443 - //SDMA0_PAGE_MIDCMD_DATA0 1444 - #define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 1445 - #define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1446 - //SDMA0_PAGE_MIDCMD_DATA1 1447 - #define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 1448 - #define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1449 - //SDMA0_PAGE_MIDCMD_DATA2 1450 - #define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 1451 - #define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1452 - //SDMA0_PAGE_MIDCMD_DATA3 1453 - #define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 1454 - #define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1455 - //SDMA0_PAGE_MIDCMD_DATA4 1456 - #define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 1457 - #define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1458 - //SDMA0_PAGE_MIDCMD_DATA5 1459 - #define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 1460 - #define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1461 - //SDMA0_PAGE_MIDCMD_DATA6 1462 - #define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 1463 - #define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1464 - //SDMA0_PAGE_MIDCMD_DATA7 1465 - #define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 1466 - #define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1467 - //SDMA0_PAGE_MIDCMD_DATA8 1468 - #define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 1469 - #define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1470 - //SDMA0_PAGE_MIDCMD_CNTL 1471 - #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1472 - #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1473 - #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1474 - #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1475 - #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1476 - #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1477 - #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1478 - #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1479 - //SDMA0_RLC0_RB_CNTL 1480 - #define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 1481 - #define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 1482 - #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1483 - #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1484 - #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1485 - #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1486 - #define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 1487 - #define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 1488 - #define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1489 - #define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1490 - #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1491 - #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1492 - #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1493 - #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1494 - #define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L 1495 - #define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L 1496 - //SDMA0_RLC0_RB_BASE 1497 - #define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 1498 - #define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1499 - //SDMA0_RLC0_RB_BASE_HI 1500 - #define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 1501 - #define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1502 - //SDMA0_RLC0_RB_RPTR 1503 - #define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 1504 - #define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1505 - //SDMA0_RLC0_RB_RPTR_HI 1506 - #define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 1507 - #define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1508 - //SDMA0_RLC0_RB_WPTR 1509 - #define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 1510 - #define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1511 - //SDMA0_RLC0_RB_WPTR_HI 1512 - #define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 1513 - #define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1514 - //SDMA0_RLC0_RB_WPTR_POLL_CNTL 1515 - #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1516 - #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1517 - #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1518 - #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1519 - #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1520 - #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1521 - #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1522 - #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1523 - #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1524 - #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1525 - //SDMA0_RLC0_RB_RPTR_ADDR_HI 1526 - #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1527 - #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1528 - //SDMA0_RLC0_RB_RPTR_ADDR_LO 1529 - #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1530 - #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1531 - //SDMA0_RLC0_IB_CNTL 1532 - #define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 1533 - #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1534 - #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1535 - #define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 1536 - #define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1537 - #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1538 - #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1539 - #define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1540 - //SDMA0_RLC0_IB_RPTR 1541 - #define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 1542 - #define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1543 - //SDMA0_RLC0_IB_OFFSET 1544 - #define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 1545 - #define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1546 - //SDMA0_RLC0_IB_BASE_LO 1547 - #define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 1548 - #define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1549 - //SDMA0_RLC0_IB_BASE_HI 1550 - #define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 1551 - #define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1552 - //SDMA0_RLC0_IB_SIZE 1553 - #define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 1554 - #define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL 1555 - //SDMA0_RLC0_SKIP_CNTL 1556 - #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1557 - #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1558 - //SDMA0_RLC0_CONTEXT_STATUS 1559 - #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1560 - #define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 1561 - #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1562 - #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1563 - #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1564 - #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1565 - #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1566 - #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1567 - #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1568 - #define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1569 - #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1570 - #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1571 - #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1572 - #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1573 - #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1574 - #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1575 - //SDMA0_RLC0_DOORBELL 1576 - #define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 1577 - #define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 1578 - #define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L 1579 - #define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L 1580 - //SDMA0_RLC0_STATUS 1581 - #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1582 - #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1583 - #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1584 - #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1585 - //SDMA0_RLC0_DOORBELL_LOG 1586 - #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1587 - #define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 1588 - #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1589 - #define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1590 - //SDMA0_RLC0_WATERMARK 1591 - #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1592 - #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1593 - #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1594 - #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1595 - //SDMA0_RLC0_DOORBELL_OFFSET 1596 - #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1597 - #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1598 - //SDMA0_RLC0_CSA_ADDR_LO 1599 - #define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 1600 - #define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1601 - //SDMA0_RLC0_CSA_ADDR_HI 1602 - #define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 1603 - #define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1604 - //SDMA0_RLC0_IB_SUB_REMAIN 1605 - #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1606 - #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1607 - //SDMA0_RLC0_PREEMPT 1608 - #define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 1609 - #define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1610 - //SDMA0_RLC0_DUMMY_REG 1611 - #define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 1612 - #define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1613 - //SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 1614 - #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1615 - #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1616 - //SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 1617 - #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1618 - #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1619 - //SDMA0_RLC0_RB_AQL_CNTL 1620 - #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1621 - #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1622 - #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1623 - #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1624 - #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1625 - #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1626 - //SDMA0_RLC0_MINOR_PTR_UPDATE 1627 - #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1628 - #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1629 - //SDMA0_RLC0_MIDCMD_DATA0 1630 - #define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 1631 - #define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1632 - //SDMA0_RLC0_MIDCMD_DATA1 1633 - #define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 1634 - #define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1635 - //SDMA0_RLC0_MIDCMD_DATA2 1636 - #define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 1637 - #define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1638 - //SDMA0_RLC0_MIDCMD_DATA3 1639 - #define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 1640 - #define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1641 - //SDMA0_RLC0_MIDCMD_DATA4 1642 - #define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 1643 - #define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1644 - //SDMA0_RLC0_MIDCMD_DATA5 1645 - #define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 1646 - #define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1647 - //SDMA0_RLC0_MIDCMD_DATA6 1648 - #define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 1649 - #define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1650 - //SDMA0_RLC0_MIDCMD_DATA7 1651 - #define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 1652 - #define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1653 - //SDMA0_RLC0_MIDCMD_DATA8 1654 - #define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 1655 - #define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1656 - //SDMA0_RLC0_MIDCMD_CNTL 1657 - #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1658 - #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1659 - #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1660 - #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1661 - #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1662 - #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1663 - #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1664 - #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1665 - //SDMA0_RLC1_RB_CNTL 1666 - #define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 1667 - #define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 1668 - #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1669 - #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1670 - #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1671 - #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1672 - #define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 1673 - #define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 1674 - #define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1675 - #define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1676 - #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1677 - #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1678 - #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1679 - #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1680 - #define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L 1681 - #define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L 1682 - //SDMA0_RLC1_RB_BASE 1683 - #define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 1684 - #define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1685 - //SDMA0_RLC1_RB_BASE_HI 1686 - #define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 1687 - #define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1688 - //SDMA0_RLC1_RB_RPTR 1689 - #define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 1690 - #define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1691 - //SDMA0_RLC1_RB_RPTR_HI 1692 - #define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 1693 - #define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1694 - //SDMA0_RLC1_RB_WPTR 1695 - #define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 1696 - #define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1697 - //SDMA0_RLC1_RB_WPTR_HI 1698 - #define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 1699 - #define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1700 - //SDMA0_RLC1_RB_WPTR_POLL_CNTL 1701 - #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1702 - #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1703 - #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1704 - #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1705 - #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1706 - #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1707 - #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1708 - #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1709 - #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1710 - #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1711 - //SDMA0_RLC1_RB_RPTR_ADDR_HI 1712 - #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1713 - #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1714 - //SDMA0_RLC1_RB_RPTR_ADDR_LO 1715 - #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1716 - #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1717 - //SDMA0_RLC1_IB_CNTL 1718 - #define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 1719 - #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1720 - #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1721 - #define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 1722 - #define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1723 - #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1724 - #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1725 - #define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1726 - //SDMA0_RLC1_IB_RPTR 1727 - #define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 1728 - #define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1729 - //SDMA0_RLC1_IB_OFFSET 1730 - #define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 1731 - #define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1732 - //SDMA0_RLC1_IB_BASE_LO 1733 - #define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 1734 - #define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1735 - //SDMA0_RLC1_IB_BASE_HI 1736 - #define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 1737 - #define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1738 - //SDMA0_RLC1_IB_SIZE 1739 - #define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 1740 - #define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL 1741 - //SDMA0_RLC1_SKIP_CNTL 1742 - #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1743 - #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1744 - //SDMA0_RLC1_CONTEXT_STATUS 1745 - #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1746 - #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 1747 - #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1748 - #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1749 - #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1750 - #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1751 - #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1752 - #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1753 - #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1754 - #define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1755 - #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1756 - #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1757 - #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1758 - #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1759 - #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1760 - #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1761 - //SDMA0_RLC1_DOORBELL 1762 - #define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 1763 - #define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 1764 - #define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L 1765 - #define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L 1766 - //SDMA0_RLC1_STATUS 1767 - #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1768 - #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1769 - #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1770 - #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1771 - //SDMA0_RLC1_DOORBELL_LOG 1772 - #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1773 - #define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 1774 - #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1775 - #define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1776 - //SDMA0_RLC1_WATERMARK 1777 - #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1778 - #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1779 - #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1780 - #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1781 - //SDMA0_RLC1_DOORBELL_OFFSET 1782 - #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1783 - #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1784 - //SDMA0_RLC1_CSA_ADDR_LO 1785 - #define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 1786 - #define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1787 - //SDMA0_RLC1_CSA_ADDR_HI 1788 - #define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 1789 - #define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1790 - //SDMA0_RLC1_IB_SUB_REMAIN 1791 - #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1792 - #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1793 - //SDMA0_RLC1_PREEMPT 1794 - #define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 1795 - #define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1796 - //SDMA0_RLC1_DUMMY_REG 1797 - #define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 1798 - #define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1799 - //SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 1800 - #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1801 - #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1802 - //SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 1803 - #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1804 - #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1805 - //SDMA0_RLC1_RB_AQL_CNTL 1806 - #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1807 - #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1808 - #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1809 - #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1810 - #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1811 - #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1812 - //SDMA0_RLC1_MINOR_PTR_UPDATE 1813 - #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1814 - #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1815 - //SDMA0_RLC1_MIDCMD_DATA0 1816 - #define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 1817 - #define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1818 - //SDMA0_RLC1_MIDCMD_DATA1 1819 - #define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 1820 - #define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1821 - //SDMA0_RLC1_MIDCMD_DATA2 1822 - #define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 1823 - #define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1824 - //SDMA0_RLC1_MIDCMD_DATA3 1825 - #define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 1826 - #define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1827 - //SDMA0_RLC1_MIDCMD_DATA4 1828 - #define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 1829 - #define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1830 - //SDMA0_RLC1_MIDCMD_DATA5 1831 - #define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 1832 - #define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1833 - //SDMA0_RLC1_MIDCMD_DATA6 1834 - #define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 1835 - #define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1836 - //SDMA0_RLC1_MIDCMD_DATA7 1837 - #define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 1838 - #define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1839 - //SDMA0_RLC1_MIDCMD_DATA8 1840 - #define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 1841 - #define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1842 - //SDMA0_RLC1_MIDCMD_CNTL 1843 - #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1844 - #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1845 - #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1846 - #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1847 - #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1848 - #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1849 - #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1850 - #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1851 - 1852 - #endif
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drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_default.h
··· 1 - /* 2 - * Copyright (C) 2017 Advanced Micro Devices, Inc. 3 - * 4 - * Permission is hereby granted, free of charge, to any person obtaining a 5 - * copy of this software and associated documentation files (the "Software"), 6 - * to deal in the Software without restriction, including without limitation 7 - * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 - * and/or sell copies of the Software, and to permit persons to whom the 9 - * Software is furnished to do so, subject to the following conditions: 10 - * 11 - * The above copyright notice and this permission notice shall be included 12 - * in all copies or substantial portions of the Software. 13 - * 14 - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 - */ 21 - #ifndef _sdma1_4_0_DEFAULT_HEADER 22 - #define _sdma1_4_0_DEFAULT_HEADER 23 - 24 - 25 - // addressBlock: sdma1_sdma1dec 26 - #define mmSDMA1_UCODE_ADDR_DEFAULT 0x00000000 27 - #define mmSDMA1_UCODE_DATA_DEFAULT 0x00000000 28 - #define mmSDMA1_VM_CNTL_DEFAULT 0x00000000 29 - #define mmSDMA1_VM_CTX_LO_DEFAULT 0x00000000 30 - #define mmSDMA1_VM_CTX_HI_DEFAULT 0x00000000 31 - #define mmSDMA1_ACTIVE_FCN_ID_DEFAULT 0x00000000 32 - #define mmSDMA1_VM_CTX_CNTL_DEFAULT 0x00000000 33 - #define mmSDMA1_VIRT_RESET_REQ_DEFAULT 0x00000000 34 - #define mmSDMA1_VF_ENABLE_DEFAULT 0x00000000 35 - #define mmSDMA1_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f 36 - #define mmSDMA1_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff 37 - #define mmSDMA1_CONTEXT_REG_TYPE2_DEFAULT 0x000003ff 38 - #define mmSDMA1_CONTEXT_REG_TYPE3_DEFAULT 0x00000000 39 - #define mmSDMA1_PUB_REG_TYPE0_DEFAULT 0x3c000000 40 - #define mmSDMA1_PUB_REG_TYPE1_DEFAULT 0x30003882 41 - #define mmSDMA1_PUB_REG_TYPE2_DEFAULT 0x0fc6e880 42 - #define mmSDMA1_PUB_REG_TYPE3_DEFAULT 0x00000000 43 - #define mmSDMA1_MMHUB_CNTL_DEFAULT 0x00000000 44 - #define mmSDMA1_CONTEXT_GROUP_BOUNDARY_DEFAULT 0x00000000 45 - #define mmSDMA1_POWER_CNTL_DEFAULT 0x0003c000 46 - #define mmSDMA1_CLK_CTRL_DEFAULT 0xff000100 47 - #define mmSDMA1_CNTL_DEFAULT 0x00000002 48 - #define mmSDMA1_CHICKEN_BITS_DEFAULT 0x00831f07 49 - #define mmSDMA1_GB_ADDR_CONFIG_DEFAULT 0x00100012 50 - #define mmSDMA1_GB_ADDR_CONFIG_READ_DEFAULT 0x00100012 51 - #define mmSDMA1_RB_RPTR_FETCH_HI_DEFAULT 0x00000000 52 - #define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT 0x00000000 53 - #define mmSDMA1_RB_RPTR_FETCH_DEFAULT 0x00000000 54 - #define mmSDMA1_IB_OFFSET_FETCH_DEFAULT 0x00000000 55 - #define mmSDMA1_PROGRAM_DEFAULT 0x00000000 56 - #define mmSDMA1_STATUS_REG_DEFAULT 0x46dee557 57 - #define mmSDMA1_STATUS1_REG_DEFAULT 0x000003ff 58 - #define mmSDMA1_RD_BURST_CNTL_DEFAULT 0x00000003 59 - #define mmSDMA1_HBM_PAGE_CONFIG_DEFAULT 0x00000000 60 - #define mmSDMA1_UCODE_CHECKSUM_DEFAULT 0x00000000 61 - #define mmSDMA1_F32_CNTL_DEFAULT 0x00000001 62 - #define mmSDMA1_FREEZE_DEFAULT 0x00000000 63 - #define mmSDMA1_PHASE0_QUANTUM_DEFAULT 0x00010002 64 - #define mmSDMA1_PHASE1_QUANTUM_DEFAULT 0x00010002 65 - #define mmSDMA1_EDC_CONFIG_DEFAULT 0x00000002 66 - #define mmSDMA1_BA_THRESHOLD_DEFAULT 0x03ff03ff 67 - #define mmSDMA1_ID_DEFAULT 0x00000001 68 - #define mmSDMA1_VERSION_DEFAULT 0x00000400 69 - #define mmSDMA1_EDC_COUNTER_DEFAULT 0x00000000 70 - #define mmSDMA1_EDC_COUNTER_CLEAR_DEFAULT 0x00000000 71 - #define mmSDMA1_STATUS2_REG_DEFAULT 0x00000001 72 - #define mmSDMA1_ATOMIC_CNTL_DEFAULT 0x00000200 73 - #define mmSDMA1_ATOMIC_PREOP_LO_DEFAULT 0x00000000 74 - #define mmSDMA1_ATOMIC_PREOP_HI_DEFAULT 0x00000000 75 - #define mmSDMA1_UTCL1_CNTL_DEFAULT 0xd0003019 76 - #define mmSDMA1_UTCL1_WATERMK_DEFAULT 0xfffbe1fe 77 - #define mmSDMA1_UTCL1_RD_STATUS_DEFAULT 0x201001ff 78 - #define mmSDMA1_UTCL1_WR_STATUS_DEFAULT 0x503001ff 79 - #define mmSDMA1_UTCL1_INV0_DEFAULT 0x00000600 80 - #define mmSDMA1_UTCL1_INV1_DEFAULT 0x00000000 81 - #define mmSDMA1_UTCL1_INV2_DEFAULT 0x00000000 82 - #define mmSDMA1_UTCL1_RD_XNACK0_DEFAULT 0x00000000 83 - #define mmSDMA1_UTCL1_RD_XNACK1_DEFAULT 0x00000000 84 - #define mmSDMA1_UTCL1_WR_XNACK0_DEFAULT 0x00000000 85 - #define mmSDMA1_UTCL1_WR_XNACK1_DEFAULT 0x00000000 86 - #define mmSDMA1_UTCL1_TIMEOUT_DEFAULT 0x00010001 87 - #define mmSDMA1_UTCL1_PAGE_DEFAULT 0x000003e0 88 - #define mmSDMA1_POWER_CNTL_IDLE_DEFAULT 0x06060200 89 - #define mmSDMA1_RELAX_ORDERING_LUT_DEFAULT 0xc0000006 90 - #define mmSDMA1_CHICKEN_BITS_2_DEFAULT 0x00000005 91 - #define mmSDMA1_STATUS3_REG_DEFAULT 0x00100000 92 - #define mmSDMA1_PHYSICAL_ADDR_LO_DEFAULT 0x00000000 93 - #define mmSDMA1_PHYSICAL_ADDR_HI_DEFAULT 0x00000000 94 - #define mmSDMA1_PHASE2_QUANTUM_DEFAULT 0x00010002 95 - #define mmSDMA1_ERROR_LOG_DEFAULT 0x0000000f 96 - #define mmSDMA1_PUB_DUMMY_REG0_DEFAULT 0x00000000 97 - #define mmSDMA1_PUB_DUMMY_REG1_DEFAULT 0x00000000 98 - #define mmSDMA1_PUB_DUMMY_REG2_DEFAULT 0x00000000 99 - #define mmSDMA1_PUB_DUMMY_REG3_DEFAULT 0x00000000 100 - #define mmSDMA1_F32_COUNTER_DEFAULT 0x00000000 101 - #define mmSDMA1_UNBREAKABLE_DEFAULT 0x00000000 102 - #define mmSDMA1_PERFMON_CNTL_DEFAULT 0x000ff7fd 103 - #define mmSDMA1_PERFCOUNTER0_RESULT_DEFAULT 0x00000000 104 - #define mmSDMA1_PERFCOUNTER1_RESULT_DEFAULT 0x00000000 105 - #define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_DEFAULT 0x00640000 106 - #define mmSDMA1_CRD_CNTL_DEFAULT 0x000085c0 107 - #define mmSDMA1_MMHUB_TRUSTLVL_DEFAULT 0x00000000 108 - #define mmSDMA1_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000 109 - #define mmSDMA1_ULV_CNTL_DEFAULT 0x00000000 110 - #define mmSDMA1_EA_DBIT_ADDR_DATA_DEFAULT 0x00000000 111 - #define mmSDMA1_EA_DBIT_ADDR_INDEX_DEFAULT 0x00000000 112 - #define mmSDMA1_GFX_RB_CNTL_DEFAULT 0x00040000 113 - #define mmSDMA1_GFX_RB_BASE_DEFAULT 0x00000000 114 - #define mmSDMA1_GFX_RB_BASE_HI_DEFAULT 0x00000000 115 - #define mmSDMA1_GFX_RB_RPTR_DEFAULT 0x00000000 116 - #define mmSDMA1_GFX_RB_RPTR_HI_DEFAULT 0x00000000 117 - #define mmSDMA1_GFX_RB_WPTR_DEFAULT 0x00000000 118 - #define mmSDMA1_GFX_RB_WPTR_HI_DEFAULT 0x00000000 119 - #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 120 - #define mmSDMA1_GFX_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 121 - #define mmSDMA1_GFX_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 122 - #define mmSDMA1_GFX_IB_CNTL_DEFAULT 0x00000100 123 - #define mmSDMA1_GFX_IB_RPTR_DEFAULT 0x00000000 124 - #define mmSDMA1_GFX_IB_OFFSET_DEFAULT 0x00000000 125 - #define mmSDMA1_GFX_IB_BASE_LO_DEFAULT 0x00000000 126 - #define mmSDMA1_GFX_IB_BASE_HI_DEFAULT 0x00000000 127 - #define mmSDMA1_GFX_IB_SIZE_DEFAULT 0x00000000 128 - #define mmSDMA1_GFX_SKIP_CNTL_DEFAULT 0x00000000 129 - #define mmSDMA1_GFX_CONTEXT_STATUS_DEFAULT 0x00000005 130 - #define mmSDMA1_GFX_DOORBELL_DEFAULT 0x00000000 131 - #define mmSDMA1_GFX_CONTEXT_CNTL_DEFAULT 0x00000000 132 - #define mmSDMA1_GFX_STATUS_DEFAULT 0x00000000 133 - #define mmSDMA1_GFX_DOORBELL_LOG_DEFAULT 0x00000000 134 - #define mmSDMA1_GFX_WATERMARK_DEFAULT 0x00000000 135 - #define mmSDMA1_GFX_DOORBELL_OFFSET_DEFAULT 0x00000000 136 - #define mmSDMA1_GFX_CSA_ADDR_LO_DEFAULT 0x00000000 137 - #define mmSDMA1_GFX_CSA_ADDR_HI_DEFAULT 0x00000000 138 - #define mmSDMA1_GFX_IB_SUB_REMAIN_DEFAULT 0x00000000 139 - #define mmSDMA1_GFX_PREEMPT_DEFAULT 0x00000000 140 - #define mmSDMA1_GFX_DUMMY_REG_DEFAULT 0x0000000f 141 - #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 142 - #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 143 - #define mmSDMA1_GFX_RB_AQL_CNTL_DEFAULT 0x00004000 144 - #define mmSDMA1_GFX_MINOR_PTR_UPDATE_DEFAULT 0x00000000 145 - #define mmSDMA1_GFX_MIDCMD_DATA0_DEFAULT 0x00000000 146 - #define mmSDMA1_GFX_MIDCMD_DATA1_DEFAULT 0x00000000 147 - #define mmSDMA1_GFX_MIDCMD_DATA2_DEFAULT 0x00000000 148 - #define mmSDMA1_GFX_MIDCMD_DATA3_DEFAULT 0x00000000 149 - #define mmSDMA1_GFX_MIDCMD_DATA4_DEFAULT 0x00000000 150 - #define mmSDMA1_GFX_MIDCMD_DATA5_DEFAULT 0x00000000 151 - #define mmSDMA1_GFX_MIDCMD_DATA6_DEFAULT 0x00000000 152 - #define mmSDMA1_GFX_MIDCMD_DATA7_DEFAULT 0x00000000 153 - #define mmSDMA1_GFX_MIDCMD_DATA8_DEFAULT 0x00000000 154 - #define mmSDMA1_GFX_MIDCMD_CNTL_DEFAULT 0x00000000 155 - #define mmSDMA1_PAGE_RB_CNTL_DEFAULT 0x00040000 156 - #define mmSDMA1_PAGE_RB_BASE_DEFAULT 0x00000000 157 - #define mmSDMA1_PAGE_RB_BASE_HI_DEFAULT 0x00000000 158 - #define mmSDMA1_PAGE_RB_RPTR_DEFAULT 0x00000000 159 - #define mmSDMA1_PAGE_RB_RPTR_HI_DEFAULT 0x00000000 160 - #define mmSDMA1_PAGE_RB_WPTR_DEFAULT 0x00000000 161 - #define mmSDMA1_PAGE_RB_WPTR_HI_DEFAULT 0x00000000 162 - #define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 163 - #define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 164 - #define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 165 - #define mmSDMA1_PAGE_IB_CNTL_DEFAULT 0x00000100 166 - #define mmSDMA1_PAGE_IB_RPTR_DEFAULT 0x00000000 167 - #define mmSDMA1_PAGE_IB_OFFSET_DEFAULT 0x00000000 168 - #define mmSDMA1_PAGE_IB_BASE_LO_DEFAULT 0x00000000 169 - #define mmSDMA1_PAGE_IB_BASE_HI_DEFAULT 0x00000000 170 - #define mmSDMA1_PAGE_IB_SIZE_DEFAULT 0x00000000 171 - #define mmSDMA1_PAGE_SKIP_CNTL_DEFAULT 0x00000000 172 - #define mmSDMA1_PAGE_CONTEXT_STATUS_DEFAULT 0x00000004 173 - #define mmSDMA1_PAGE_DOORBELL_DEFAULT 0x00000000 174 - #define mmSDMA1_PAGE_STATUS_DEFAULT 0x00000000 175 - #define mmSDMA1_PAGE_DOORBELL_LOG_DEFAULT 0x00000000 176 - #define mmSDMA1_PAGE_WATERMARK_DEFAULT 0x00000000 177 - #define mmSDMA1_PAGE_DOORBELL_OFFSET_DEFAULT 0x00000000 178 - #define mmSDMA1_PAGE_CSA_ADDR_LO_DEFAULT 0x00000000 179 - #define mmSDMA1_PAGE_CSA_ADDR_HI_DEFAULT 0x00000000 180 - #define mmSDMA1_PAGE_IB_SUB_REMAIN_DEFAULT 0x00000000 181 - #define mmSDMA1_PAGE_PREEMPT_DEFAULT 0x00000000 182 - #define mmSDMA1_PAGE_DUMMY_REG_DEFAULT 0x0000000f 183 - #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 184 - #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 185 - #define mmSDMA1_PAGE_RB_AQL_CNTL_DEFAULT 0x00004000 186 - #define mmSDMA1_PAGE_MINOR_PTR_UPDATE_DEFAULT 0x00000000 187 - #define mmSDMA1_PAGE_MIDCMD_DATA0_DEFAULT 0x00000000 188 - #define mmSDMA1_PAGE_MIDCMD_DATA1_DEFAULT 0x00000000 189 - #define mmSDMA1_PAGE_MIDCMD_DATA2_DEFAULT 0x00000000 190 - #define mmSDMA1_PAGE_MIDCMD_DATA3_DEFAULT 0x00000000 191 - #define mmSDMA1_PAGE_MIDCMD_DATA4_DEFAULT 0x00000000 192 - #define mmSDMA1_PAGE_MIDCMD_DATA5_DEFAULT 0x00000000 193 - #define mmSDMA1_PAGE_MIDCMD_DATA6_DEFAULT 0x00000000 194 - #define mmSDMA1_PAGE_MIDCMD_DATA7_DEFAULT 0x00000000 195 - #define mmSDMA1_PAGE_MIDCMD_DATA8_DEFAULT 0x00000000 196 - #define mmSDMA1_PAGE_MIDCMD_CNTL_DEFAULT 0x00000000 197 - #define mmSDMA1_RLC0_RB_CNTL_DEFAULT 0x00040000 198 - #define mmSDMA1_RLC0_RB_BASE_DEFAULT 0x00000000 199 - #define mmSDMA1_RLC0_RB_BASE_HI_DEFAULT 0x00000000 200 - #define mmSDMA1_RLC0_RB_RPTR_DEFAULT 0x00000000 201 - #define mmSDMA1_RLC0_RB_RPTR_HI_DEFAULT 0x00000000 202 - #define mmSDMA1_RLC0_RB_WPTR_DEFAULT 0x00000000 203 - #define mmSDMA1_RLC0_RB_WPTR_HI_DEFAULT 0x00000000 204 - #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 205 - #define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 206 - #define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 207 - #define mmSDMA1_RLC0_IB_CNTL_DEFAULT 0x00000100 208 - #define mmSDMA1_RLC0_IB_RPTR_DEFAULT 0x00000000 209 - #define mmSDMA1_RLC0_IB_OFFSET_DEFAULT 0x00000000 210 - #define mmSDMA1_RLC0_IB_BASE_LO_DEFAULT 0x00000000 211 - #define mmSDMA1_RLC0_IB_BASE_HI_DEFAULT 0x00000000 212 - #define mmSDMA1_RLC0_IB_SIZE_DEFAULT 0x00000000 213 - #define mmSDMA1_RLC0_SKIP_CNTL_DEFAULT 0x00000000 214 - #define mmSDMA1_RLC0_CONTEXT_STATUS_DEFAULT 0x00000004 215 - #define mmSDMA1_RLC0_DOORBELL_DEFAULT 0x00000000 216 - #define mmSDMA1_RLC0_STATUS_DEFAULT 0x00000000 217 - #define mmSDMA1_RLC0_DOORBELL_LOG_DEFAULT 0x00000000 218 - #define mmSDMA1_RLC0_WATERMARK_DEFAULT 0x00000000 219 - #define mmSDMA1_RLC0_DOORBELL_OFFSET_DEFAULT 0x00000000 220 - #define mmSDMA1_RLC0_CSA_ADDR_LO_DEFAULT 0x00000000 221 - #define mmSDMA1_RLC0_CSA_ADDR_HI_DEFAULT 0x00000000 222 - #define mmSDMA1_RLC0_IB_SUB_REMAIN_DEFAULT 0x00000000 223 - #define mmSDMA1_RLC0_PREEMPT_DEFAULT 0x00000000 224 - #define mmSDMA1_RLC0_DUMMY_REG_DEFAULT 0x0000000f 225 - #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 226 - #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 227 - #define mmSDMA1_RLC0_RB_AQL_CNTL_DEFAULT 0x00004000 228 - #define mmSDMA1_RLC0_MINOR_PTR_UPDATE_DEFAULT 0x00000000 229 - #define mmSDMA1_RLC0_MIDCMD_DATA0_DEFAULT 0x00000000 230 - #define mmSDMA1_RLC0_MIDCMD_DATA1_DEFAULT 0x00000000 231 - #define mmSDMA1_RLC0_MIDCMD_DATA2_DEFAULT 0x00000000 232 - #define mmSDMA1_RLC0_MIDCMD_DATA3_DEFAULT 0x00000000 233 - #define mmSDMA1_RLC0_MIDCMD_DATA4_DEFAULT 0x00000000 234 - #define mmSDMA1_RLC0_MIDCMD_DATA5_DEFAULT 0x00000000 235 - #define mmSDMA1_RLC0_MIDCMD_DATA6_DEFAULT 0x00000000 236 - #define mmSDMA1_RLC0_MIDCMD_DATA7_DEFAULT 0x00000000 237 - #define mmSDMA1_RLC0_MIDCMD_DATA8_DEFAULT 0x00000000 238 - #define mmSDMA1_RLC0_MIDCMD_CNTL_DEFAULT 0x00000000 239 - #define mmSDMA1_RLC1_RB_CNTL_DEFAULT 0x00040000 240 - #define mmSDMA1_RLC1_RB_BASE_DEFAULT 0x00000000 241 - #define mmSDMA1_RLC1_RB_BASE_HI_DEFAULT 0x00000000 242 - #define mmSDMA1_RLC1_RB_RPTR_DEFAULT 0x00000000 243 - #define mmSDMA1_RLC1_RB_RPTR_HI_DEFAULT 0x00000000 244 - #define mmSDMA1_RLC1_RB_WPTR_DEFAULT 0x00000000 245 - #define mmSDMA1_RLC1_RB_WPTR_HI_DEFAULT 0x00000000 246 - #define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 247 - #define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 248 - #define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 249 - #define mmSDMA1_RLC1_IB_CNTL_DEFAULT 0x00000100 250 - #define mmSDMA1_RLC1_IB_RPTR_DEFAULT 0x00000000 251 - #define mmSDMA1_RLC1_IB_OFFSET_DEFAULT 0x00000000 252 - #define mmSDMA1_RLC1_IB_BASE_LO_DEFAULT 0x00000000 253 - #define mmSDMA1_RLC1_IB_BASE_HI_DEFAULT 0x00000000 254 - #define mmSDMA1_RLC1_IB_SIZE_DEFAULT 0x00000000 255 - #define mmSDMA1_RLC1_SKIP_CNTL_DEFAULT 0x00000000 256 - #define mmSDMA1_RLC1_CONTEXT_STATUS_DEFAULT 0x00000004 257 - #define mmSDMA1_RLC1_DOORBELL_DEFAULT 0x00000000 258 - #define mmSDMA1_RLC1_STATUS_DEFAULT 0x00000000 259 - #define mmSDMA1_RLC1_DOORBELL_LOG_DEFAULT 0x00000000 260 - #define mmSDMA1_RLC1_WATERMARK_DEFAULT 0x00000000 261 - #define mmSDMA1_RLC1_DOORBELL_OFFSET_DEFAULT 0x00000000 262 - #define mmSDMA1_RLC1_CSA_ADDR_LO_DEFAULT 0x00000000 263 - #define mmSDMA1_RLC1_CSA_ADDR_HI_DEFAULT 0x00000000 264 - #define mmSDMA1_RLC1_IB_SUB_REMAIN_DEFAULT 0x00000000 265 - #define mmSDMA1_RLC1_PREEMPT_DEFAULT 0x00000000 266 - #define mmSDMA1_RLC1_DUMMY_REG_DEFAULT 0x0000000f 267 - #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 268 - #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 269 - #define mmSDMA1_RLC1_RB_AQL_CNTL_DEFAULT 0x00004000 270 - #define mmSDMA1_RLC1_MINOR_PTR_UPDATE_DEFAULT 0x00000000 271 - #define mmSDMA1_RLC1_MIDCMD_DATA0_DEFAULT 0x00000000 272 - #define mmSDMA1_RLC1_MIDCMD_DATA1_DEFAULT 0x00000000 273 - #define mmSDMA1_RLC1_MIDCMD_DATA2_DEFAULT 0x00000000 274 - #define mmSDMA1_RLC1_MIDCMD_DATA3_DEFAULT 0x00000000 275 - #define mmSDMA1_RLC1_MIDCMD_DATA4_DEFAULT 0x00000000 276 - #define mmSDMA1_RLC1_MIDCMD_DATA5_DEFAULT 0x00000000 277 - #define mmSDMA1_RLC1_MIDCMD_DATA6_DEFAULT 0x00000000 278 - #define mmSDMA1_RLC1_MIDCMD_DATA7_DEFAULT 0x00000000 279 - #define mmSDMA1_RLC1_MIDCMD_DATA8_DEFAULT 0x00000000 280 - #define mmSDMA1_RLC1_MIDCMD_CNTL_DEFAULT 0x00000000 281 - 282 - #endif
-539
drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_offset.h
··· 1 - /* 2 - * Copyright (C) 2017 Advanced Micro Devices, Inc. 3 - * 4 - * Permission is hereby granted, free of charge, to any person obtaining a 5 - * copy of this software and associated documentation files (the "Software"), 6 - * to deal in the Software without restriction, including without limitation 7 - * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 - * and/or sell copies of the Software, and to permit persons to whom the 9 - * Software is furnished to do so, subject to the following conditions: 10 - * 11 - * The above copyright notice and this permission notice shall be included 12 - * in all copies or substantial portions of the Software. 13 - * 14 - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 - */ 21 - #ifndef _sdma1_4_0_OFFSET_HEADER 22 - #define _sdma1_4_0_OFFSET_HEADER 23 - 24 - 25 - 26 - // addressBlock: sdma1_sdma1dec 27 - // base address: 0x5180 28 - #define mmSDMA1_UCODE_ADDR 0x0000 29 - #define mmSDMA1_UCODE_ADDR_BASE_IDX 0 30 - #define mmSDMA1_UCODE_DATA 0x0001 31 - #define mmSDMA1_UCODE_DATA_BASE_IDX 0 32 - #define mmSDMA1_VM_CNTL 0x0004 33 - #define mmSDMA1_VM_CNTL_BASE_IDX 0 34 - #define mmSDMA1_VM_CTX_LO 0x0005 35 - #define mmSDMA1_VM_CTX_LO_BASE_IDX 0 36 - #define mmSDMA1_VM_CTX_HI 0x0006 37 - #define mmSDMA1_VM_CTX_HI_BASE_IDX 0 38 - #define mmSDMA1_ACTIVE_FCN_ID 0x0007 39 - #define mmSDMA1_ACTIVE_FCN_ID_BASE_IDX 0 40 - #define mmSDMA1_VM_CTX_CNTL 0x0008 41 - #define mmSDMA1_VM_CTX_CNTL_BASE_IDX 0 42 - #define mmSDMA1_VIRT_RESET_REQ 0x0009 43 - #define mmSDMA1_VIRT_RESET_REQ_BASE_IDX 0 44 - #define mmSDMA1_VF_ENABLE 0x000a 45 - #define mmSDMA1_VF_ENABLE_BASE_IDX 0 46 - #define mmSDMA1_CONTEXT_REG_TYPE0 0x000b 47 - #define mmSDMA1_CONTEXT_REG_TYPE0_BASE_IDX 0 48 - #define mmSDMA1_CONTEXT_REG_TYPE1 0x000c 49 - #define mmSDMA1_CONTEXT_REG_TYPE1_BASE_IDX 0 50 - #define mmSDMA1_CONTEXT_REG_TYPE2 0x000d 51 - #define mmSDMA1_CONTEXT_REG_TYPE2_BASE_IDX 0 52 - #define mmSDMA1_CONTEXT_REG_TYPE3 0x000e 53 - #define mmSDMA1_CONTEXT_REG_TYPE3_BASE_IDX 0 54 - #define mmSDMA1_PUB_REG_TYPE0 0x000f 55 - #define mmSDMA1_PUB_REG_TYPE0_BASE_IDX 0 56 - #define mmSDMA1_PUB_REG_TYPE1 0x0010 57 - #define mmSDMA1_PUB_REG_TYPE1_BASE_IDX 0 58 - #define mmSDMA1_PUB_REG_TYPE2 0x0011 59 - #define mmSDMA1_PUB_REG_TYPE2_BASE_IDX 0 60 - #define mmSDMA1_PUB_REG_TYPE3 0x0012 61 - #define mmSDMA1_PUB_REG_TYPE3_BASE_IDX 0 62 - #define mmSDMA1_MMHUB_CNTL 0x0013 63 - #define mmSDMA1_MMHUB_CNTL_BASE_IDX 0 64 - #define mmSDMA1_CONTEXT_GROUP_BOUNDARY 0x0019 65 - #define mmSDMA1_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 66 - #define mmSDMA1_POWER_CNTL 0x001a 67 - #define mmSDMA1_POWER_CNTL_BASE_IDX 0 68 - #define mmSDMA1_CLK_CTRL 0x001b 69 - #define mmSDMA1_CLK_CTRL_BASE_IDX 0 70 - #define mmSDMA1_CNTL 0x001c 71 - #define mmSDMA1_CNTL_BASE_IDX 0 72 - #define mmSDMA1_CHICKEN_BITS 0x001d 73 - #define mmSDMA1_CHICKEN_BITS_BASE_IDX 0 74 - #define mmSDMA1_GB_ADDR_CONFIG 0x001e 75 - #define mmSDMA1_GB_ADDR_CONFIG_BASE_IDX 0 76 - #define mmSDMA1_GB_ADDR_CONFIG_READ 0x001f 77 - #define mmSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX 0 78 - #define mmSDMA1_RB_RPTR_FETCH_HI 0x0020 79 - #define mmSDMA1_RB_RPTR_FETCH_HI_BASE_IDX 0 80 - #define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 81 - #define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 82 - #define mmSDMA1_RB_RPTR_FETCH 0x0022 83 - #define mmSDMA1_RB_RPTR_FETCH_BASE_IDX 0 84 - #define mmSDMA1_IB_OFFSET_FETCH 0x0023 85 - #define mmSDMA1_IB_OFFSET_FETCH_BASE_IDX 0 86 - #define mmSDMA1_PROGRAM 0x0024 87 - #define mmSDMA1_PROGRAM_BASE_IDX 0 88 - #define mmSDMA1_STATUS_REG 0x0025 89 - #define mmSDMA1_STATUS_REG_BASE_IDX 0 90 - #define mmSDMA1_STATUS1_REG 0x0026 91 - #define mmSDMA1_STATUS1_REG_BASE_IDX 0 92 - #define mmSDMA1_RD_BURST_CNTL 0x0027 93 - #define mmSDMA1_RD_BURST_CNTL_BASE_IDX 0 94 - #define mmSDMA1_HBM_PAGE_CONFIG 0x0028 95 - #define mmSDMA1_HBM_PAGE_CONFIG_BASE_IDX 0 96 - #define mmSDMA1_UCODE_CHECKSUM 0x0029 97 - #define mmSDMA1_UCODE_CHECKSUM_BASE_IDX 0 98 - #define mmSDMA1_F32_CNTL 0x002a 99 - #define mmSDMA1_F32_CNTL_BASE_IDX 0 100 - #define mmSDMA1_FREEZE 0x002b 101 - #define mmSDMA1_FREEZE_BASE_IDX 0 102 - #define mmSDMA1_PHASE0_QUANTUM 0x002c 103 - #define mmSDMA1_PHASE0_QUANTUM_BASE_IDX 0 104 - #define mmSDMA1_PHASE1_QUANTUM 0x002d 105 - #define mmSDMA1_PHASE1_QUANTUM_BASE_IDX 0 106 - #define mmSDMA1_EDC_CONFIG 0x0032 107 - #define mmSDMA1_EDC_CONFIG_BASE_IDX 0 108 - #define mmSDMA1_BA_THRESHOLD 0x0033 109 - #define mmSDMA1_BA_THRESHOLD_BASE_IDX 0 110 - #define mmSDMA1_ID 0x0034 111 - #define mmSDMA1_ID_BASE_IDX 0 112 - #define mmSDMA1_VERSION 0x0035 113 - #define mmSDMA1_VERSION_BASE_IDX 0 114 - #define mmSDMA1_EDC_COUNTER 0x0036 115 - #define mmSDMA1_EDC_COUNTER_BASE_IDX 0 116 - #define mmSDMA1_EDC_COUNTER_CLEAR 0x0037 117 - #define mmSDMA1_EDC_COUNTER_CLEAR_BASE_IDX 0 118 - #define mmSDMA1_STATUS2_REG 0x0038 119 - #define mmSDMA1_STATUS2_REG_BASE_IDX 0 120 - #define mmSDMA1_ATOMIC_CNTL 0x0039 121 - #define mmSDMA1_ATOMIC_CNTL_BASE_IDX 0 122 - #define mmSDMA1_ATOMIC_PREOP_LO 0x003a 123 - #define mmSDMA1_ATOMIC_PREOP_LO_BASE_IDX 0 124 - #define mmSDMA1_ATOMIC_PREOP_HI 0x003b 125 - #define mmSDMA1_ATOMIC_PREOP_HI_BASE_IDX 0 126 - #define mmSDMA1_UTCL1_CNTL 0x003c 127 - #define mmSDMA1_UTCL1_CNTL_BASE_IDX 0 128 - #define mmSDMA1_UTCL1_WATERMK 0x003d 129 - #define mmSDMA1_UTCL1_WATERMK_BASE_IDX 0 130 - #define mmSDMA1_UTCL1_RD_STATUS 0x003e 131 - #define mmSDMA1_UTCL1_RD_STATUS_BASE_IDX 0 132 - #define mmSDMA1_UTCL1_WR_STATUS 0x003f 133 - #define mmSDMA1_UTCL1_WR_STATUS_BASE_IDX 0 134 - #define mmSDMA1_UTCL1_INV0 0x0040 135 - #define mmSDMA1_UTCL1_INV0_BASE_IDX 0 136 - #define mmSDMA1_UTCL1_INV1 0x0041 137 - #define mmSDMA1_UTCL1_INV1_BASE_IDX 0 138 - #define mmSDMA1_UTCL1_INV2 0x0042 139 - #define mmSDMA1_UTCL1_INV2_BASE_IDX 0 140 - #define mmSDMA1_UTCL1_RD_XNACK0 0x0043 141 - #define mmSDMA1_UTCL1_RD_XNACK0_BASE_IDX 0 142 - #define mmSDMA1_UTCL1_RD_XNACK1 0x0044 143 - #define mmSDMA1_UTCL1_RD_XNACK1_BASE_IDX 0 144 - #define mmSDMA1_UTCL1_WR_XNACK0 0x0045 145 - #define mmSDMA1_UTCL1_WR_XNACK0_BASE_IDX 0 146 - #define mmSDMA1_UTCL1_WR_XNACK1 0x0046 147 - #define mmSDMA1_UTCL1_WR_XNACK1_BASE_IDX 0 148 - #define mmSDMA1_UTCL1_TIMEOUT 0x0047 149 - #define mmSDMA1_UTCL1_TIMEOUT_BASE_IDX 0 150 - #define mmSDMA1_UTCL1_PAGE 0x0048 151 - #define mmSDMA1_UTCL1_PAGE_BASE_IDX 0 152 - #define mmSDMA1_POWER_CNTL_IDLE 0x0049 153 - #define mmSDMA1_POWER_CNTL_IDLE_BASE_IDX 0 154 - #define mmSDMA1_RELAX_ORDERING_LUT 0x004a 155 - #define mmSDMA1_RELAX_ORDERING_LUT_BASE_IDX 0 156 - #define mmSDMA1_CHICKEN_BITS_2 0x004b 157 - #define mmSDMA1_CHICKEN_BITS_2_BASE_IDX 0 158 - #define mmSDMA1_STATUS3_REG 0x004c 159 - #define mmSDMA1_STATUS3_REG_BASE_IDX 0 160 - #define mmSDMA1_PHYSICAL_ADDR_LO 0x004d 161 - #define mmSDMA1_PHYSICAL_ADDR_LO_BASE_IDX 0 162 - #define mmSDMA1_PHYSICAL_ADDR_HI 0x004e 163 - #define mmSDMA1_PHYSICAL_ADDR_HI_BASE_IDX 0 164 - #define mmSDMA1_PHASE2_QUANTUM 0x004f 165 - #define mmSDMA1_PHASE2_QUANTUM_BASE_IDX 0 166 - #define mmSDMA1_ERROR_LOG 0x0050 167 - #define mmSDMA1_ERROR_LOG_BASE_IDX 0 168 - #define mmSDMA1_PUB_DUMMY_REG0 0x0051 169 - #define mmSDMA1_PUB_DUMMY_REG0_BASE_IDX 0 170 - #define mmSDMA1_PUB_DUMMY_REG1 0x0052 171 - #define mmSDMA1_PUB_DUMMY_REG1_BASE_IDX 0 172 - #define mmSDMA1_PUB_DUMMY_REG2 0x0053 173 - #define mmSDMA1_PUB_DUMMY_REG2_BASE_IDX 0 174 - #define mmSDMA1_PUB_DUMMY_REG3 0x0054 175 - #define mmSDMA1_PUB_DUMMY_REG3_BASE_IDX 0 176 - #define mmSDMA1_F32_COUNTER 0x0055 177 - #define mmSDMA1_F32_COUNTER_BASE_IDX 0 178 - #define mmSDMA1_UNBREAKABLE 0x0056 179 - #define mmSDMA1_UNBREAKABLE_BASE_IDX 0 180 - #define mmSDMA1_PERFMON_CNTL 0x0057 181 - #define mmSDMA1_PERFMON_CNTL_BASE_IDX 0 182 - #define mmSDMA1_PERFCOUNTER0_RESULT 0x0058 183 - #define mmSDMA1_PERFCOUNTER0_RESULT_BASE_IDX 0 184 - #define mmSDMA1_PERFCOUNTER1_RESULT 0x0059 185 - #define mmSDMA1_PERFCOUNTER1_RESULT_BASE_IDX 0 186 - #define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE 0x005a 187 - #define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0 188 - #define mmSDMA1_CRD_CNTL 0x005b 189 - #define mmSDMA1_CRD_CNTL_BASE_IDX 0 190 - #define mmSDMA1_MMHUB_TRUSTLVL 0x005c 191 - #define mmSDMA1_MMHUB_TRUSTLVL_BASE_IDX 0 192 - #define mmSDMA1_GPU_IOV_VIOLATION_LOG 0x005d 193 - #define mmSDMA1_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 194 - #define mmSDMA1_ULV_CNTL 0x005e 195 - #define mmSDMA1_ULV_CNTL_BASE_IDX 0 196 - #define mmSDMA1_EA_DBIT_ADDR_DATA 0x0060 197 - #define mmSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX 0 198 - #define mmSDMA1_EA_DBIT_ADDR_INDEX 0x0061 199 - #define mmSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX 0 200 - #define mmSDMA1_GFX_RB_CNTL 0x0080 201 - #define mmSDMA1_GFX_RB_CNTL_BASE_IDX 0 202 - #define mmSDMA1_GFX_RB_BASE 0x0081 203 - #define mmSDMA1_GFX_RB_BASE_BASE_IDX 0 204 - #define mmSDMA1_GFX_RB_BASE_HI 0x0082 205 - #define mmSDMA1_GFX_RB_BASE_HI_BASE_IDX 0 206 - #define mmSDMA1_GFX_RB_RPTR 0x0083 207 - #define mmSDMA1_GFX_RB_RPTR_BASE_IDX 0 208 - #define mmSDMA1_GFX_RB_RPTR_HI 0x0084 209 - #define mmSDMA1_GFX_RB_RPTR_HI_BASE_IDX 0 210 - #define mmSDMA1_GFX_RB_WPTR 0x0085 211 - #define mmSDMA1_GFX_RB_WPTR_BASE_IDX 0 212 - #define mmSDMA1_GFX_RB_WPTR_HI 0x0086 213 - #define mmSDMA1_GFX_RB_WPTR_HI_BASE_IDX 0 214 - #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x0087 215 - #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 216 - #define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x0088 217 - #define mmSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 218 - #define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x0089 219 - #define mmSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 220 - #define mmSDMA1_GFX_IB_CNTL 0x008a 221 - #define mmSDMA1_GFX_IB_CNTL_BASE_IDX 0 222 - #define mmSDMA1_GFX_IB_RPTR 0x008b 223 - #define mmSDMA1_GFX_IB_RPTR_BASE_IDX 0 224 - #define mmSDMA1_GFX_IB_OFFSET 0x008c 225 - #define mmSDMA1_GFX_IB_OFFSET_BASE_IDX 0 226 - #define mmSDMA1_GFX_IB_BASE_LO 0x008d 227 - #define mmSDMA1_GFX_IB_BASE_LO_BASE_IDX 0 228 - #define mmSDMA1_GFX_IB_BASE_HI 0x008e 229 - #define mmSDMA1_GFX_IB_BASE_HI_BASE_IDX 0 230 - #define mmSDMA1_GFX_IB_SIZE 0x008f 231 - #define mmSDMA1_GFX_IB_SIZE_BASE_IDX 0 232 - #define mmSDMA1_GFX_SKIP_CNTL 0x0090 233 - #define mmSDMA1_GFX_SKIP_CNTL_BASE_IDX 0 234 - #define mmSDMA1_GFX_CONTEXT_STATUS 0x0091 235 - #define mmSDMA1_GFX_CONTEXT_STATUS_BASE_IDX 0 236 - #define mmSDMA1_GFX_DOORBELL 0x0092 237 - #define mmSDMA1_GFX_DOORBELL_BASE_IDX 0 238 - #define mmSDMA1_GFX_CONTEXT_CNTL 0x0093 239 - #define mmSDMA1_GFX_CONTEXT_CNTL_BASE_IDX 0 240 - #define mmSDMA1_GFX_STATUS 0x00a8 241 - #define mmSDMA1_GFX_STATUS_BASE_IDX 0 242 - #define mmSDMA1_GFX_DOORBELL_LOG 0x00a9 243 - #define mmSDMA1_GFX_DOORBELL_LOG_BASE_IDX 0 244 - #define mmSDMA1_GFX_WATERMARK 0x00aa 245 - #define mmSDMA1_GFX_WATERMARK_BASE_IDX 0 246 - #define mmSDMA1_GFX_DOORBELL_OFFSET 0x00ab 247 - #define mmSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX 0 248 - #define mmSDMA1_GFX_CSA_ADDR_LO 0x00ac 249 - #define mmSDMA1_GFX_CSA_ADDR_LO_BASE_IDX 0 250 - #define mmSDMA1_GFX_CSA_ADDR_HI 0x00ad 251 - #define mmSDMA1_GFX_CSA_ADDR_HI_BASE_IDX 0 252 - #define mmSDMA1_GFX_IB_SUB_REMAIN 0x00af 253 - #define mmSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX 0 254 - #define mmSDMA1_GFX_PREEMPT 0x00b0 255 - #define mmSDMA1_GFX_PREEMPT_BASE_IDX 0 256 - #define mmSDMA1_GFX_DUMMY_REG 0x00b1 257 - #define mmSDMA1_GFX_DUMMY_REG_BASE_IDX 0 258 - #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 259 - #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 260 - #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 261 - #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 262 - #define mmSDMA1_GFX_RB_AQL_CNTL 0x00b4 263 - #define mmSDMA1_GFX_RB_AQL_CNTL_BASE_IDX 0 264 - #define mmSDMA1_GFX_MINOR_PTR_UPDATE 0x00b5 265 - #define mmSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 266 - #define mmSDMA1_GFX_MIDCMD_DATA0 0x00c0 267 - #define mmSDMA1_GFX_MIDCMD_DATA0_BASE_IDX 0 268 - #define mmSDMA1_GFX_MIDCMD_DATA1 0x00c1 269 - #define mmSDMA1_GFX_MIDCMD_DATA1_BASE_IDX 0 270 - #define mmSDMA1_GFX_MIDCMD_DATA2 0x00c2 271 - #define mmSDMA1_GFX_MIDCMD_DATA2_BASE_IDX 0 272 - #define mmSDMA1_GFX_MIDCMD_DATA3 0x00c3 273 - #define mmSDMA1_GFX_MIDCMD_DATA3_BASE_IDX 0 274 - #define mmSDMA1_GFX_MIDCMD_DATA4 0x00c4 275 - #define mmSDMA1_GFX_MIDCMD_DATA4_BASE_IDX 0 276 - #define mmSDMA1_GFX_MIDCMD_DATA5 0x00c5 277 - #define mmSDMA1_GFX_MIDCMD_DATA5_BASE_IDX 0 278 - #define mmSDMA1_GFX_MIDCMD_DATA6 0x00c6 279 - #define mmSDMA1_GFX_MIDCMD_DATA6_BASE_IDX 0 280 - #define mmSDMA1_GFX_MIDCMD_DATA7 0x00c7 281 - #define mmSDMA1_GFX_MIDCMD_DATA7_BASE_IDX 0 282 - #define mmSDMA1_GFX_MIDCMD_DATA8 0x00c8 283 - #define mmSDMA1_GFX_MIDCMD_DATA8_BASE_IDX 0 284 - #define mmSDMA1_GFX_MIDCMD_CNTL 0x00c9 285 - #define mmSDMA1_GFX_MIDCMD_CNTL_BASE_IDX 0 286 - #define mmSDMA1_PAGE_RB_CNTL 0x00e0 287 - #define mmSDMA1_PAGE_RB_CNTL_BASE_IDX 0 288 - #define mmSDMA1_PAGE_RB_BASE 0x00e1 289 - #define mmSDMA1_PAGE_RB_BASE_BASE_IDX 0 290 - #define mmSDMA1_PAGE_RB_BASE_HI 0x00e2 291 - #define mmSDMA1_PAGE_RB_BASE_HI_BASE_IDX 0 292 - #define mmSDMA1_PAGE_RB_RPTR 0x00e3 293 - #define mmSDMA1_PAGE_RB_RPTR_BASE_IDX 0 294 - #define mmSDMA1_PAGE_RB_RPTR_HI 0x00e4 295 - #define mmSDMA1_PAGE_RB_RPTR_HI_BASE_IDX 0 296 - #define mmSDMA1_PAGE_RB_WPTR 0x00e5 297 - #define mmSDMA1_PAGE_RB_WPTR_BASE_IDX 0 298 - #define mmSDMA1_PAGE_RB_WPTR_HI 0x00e6 299 - #define mmSDMA1_PAGE_RB_WPTR_HI_BASE_IDX 0 300 - #define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL 0x00e7 301 - #define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 302 - #define mmSDMA1_PAGE_RB_RPTR_ADDR_HI 0x00e8 303 - #define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 304 - #define mmSDMA1_PAGE_RB_RPTR_ADDR_LO 0x00e9 305 - #define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 306 - #define mmSDMA1_PAGE_IB_CNTL 0x00ea 307 - #define mmSDMA1_PAGE_IB_CNTL_BASE_IDX 0 308 - #define mmSDMA1_PAGE_IB_RPTR 0x00eb 309 - #define mmSDMA1_PAGE_IB_RPTR_BASE_IDX 0 310 - #define mmSDMA1_PAGE_IB_OFFSET 0x00ec 311 - #define mmSDMA1_PAGE_IB_OFFSET_BASE_IDX 0 312 - #define mmSDMA1_PAGE_IB_BASE_LO 0x00ed 313 - #define mmSDMA1_PAGE_IB_BASE_LO_BASE_IDX 0 314 - #define mmSDMA1_PAGE_IB_BASE_HI 0x00ee 315 - #define mmSDMA1_PAGE_IB_BASE_HI_BASE_IDX 0 316 - #define mmSDMA1_PAGE_IB_SIZE 0x00ef 317 - #define mmSDMA1_PAGE_IB_SIZE_BASE_IDX 0 318 - #define mmSDMA1_PAGE_SKIP_CNTL 0x00f0 319 - #define mmSDMA1_PAGE_SKIP_CNTL_BASE_IDX 0 320 - #define mmSDMA1_PAGE_CONTEXT_STATUS 0x00f1 321 - #define mmSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX 0 322 - #define mmSDMA1_PAGE_DOORBELL 0x00f2 323 - #define mmSDMA1_PAGE_DOORBELL_BASE_IDX 0 324 - #define mmSDMA1_PAGE_STATUS 0x0108 325 - #define mmSDMA1_PAGE_STATUS_BASE_IDX 0 326 - #define mmSDMA1_PAGE_DOORBELL_LOG 0x0109 327 - #define mmSDMA1_PAGE_DOORBELL_LOG_BASE_IDX 0 328 - #define mmSDMA1_PAGE_WATERMARK 0x010a 329 - #define mmSDMA1_PAGE_WATERMARK_BASE_IDX 0 330 - #define mmSDMA1_PAGE_DOORBELL_OFFSET 0x010b 331 - #define mmSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX 0 332 - #define mmSDMA1_PAGE_CSA_ADDR_LO 0x010c 333 - #define mmSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX 0 334 - #define mmSDMA1_PAGE_CSA_ADDR_HI 0x010d 335 - #define mmSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX 0 336 - #define mmSDMA1_PAGE_IB_SUB_REMAIN 0x010f 337 - #define mmSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX 0 338 - #define mmSDMA1_PAGE_PREEMPT 0x0110 339 - #define mmSDMA1_PAGE_PREEMPT_BASE_IDX 0 340 - #define mmSDMA1_PAGE_DUMMY_REG 0x0111 341 - #define mmSDMA1_PAGE_DUMMY_REG_BASE_IDX 0 342 - #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI 0x0112 343 - #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 344 - #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO 0x0113 345 - #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 346 - #define mmSDMA1_PAGE_RB_AQL_CNTL 0x0114 347 - #define mmSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX 0 348 - #define mmSDMA1_PAGE_MINOR_PTR_UPDATE 0x0115 349 - #define mmSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 350 - #define mmSDMA1_PAGE_MIDCMD_DATA0 0x0120 351 - #define mmSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX 0 352 - #define mmSDMA1_PAGE_MIDCMD_DATA1 0x0121 353 - #define mmSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX 0 354 - #define mmSDMA1_PAGE_MIDCMD_DATA2 0x0122 355 - #define mmSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX 0 356 - #define mmSDMA1_PAGE_MIDCMD_DATA3 0x0123 357 - #define mmSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX 0 358 - #define mmSDMA1_PAGE_MIDCMD_DATA4 0x0124 359 - #define mmSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX 0 360 - #define mmSDMA1_PAGE_MIDCMD_DATA5 0x0125 361 - #define mmSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX 0 362 - #define mmSDMA1_PAGE_MIDCMD_DATA6 0x0126 363 - #define mmSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX 0 364 - #define mmSDMA1_PAGE_MIDCMD_DATA7 0x0127 365 - #define mmSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX 0 366 - #define mmSDMA1_PAGE_MIDCMD_DATA8 0x0128 367 - #define mmSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX 0 368 - #define mmSDMA1_PAGE_MIDCMD_CNTL 0x0129 369 - #define mmSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX 0 370 - #define mmSDMA1_RLC0_RB_CNTL 0x0140 371 - #define mmSDMA1_RLC0_RB_CNTL_BASE_IDX 0 372 - #define mmSDMA1_RLC0_RB_BASE 0x0141 373 - #define mmSDMA1_RLC0_RB_BASE_BASE_IDX 0 374 - #define mmSDMA1_RLC0_RB_BASE_HI 0x0142 375 - #define mmSDMA1_RLC0_RB_BASE_HI_BASE_IDX 0 376 - #define mmSDMA1_RLC0_RB_RPTR 0x0143 377 - #define mmSDMA1_RLC0_RB_RPTR_BASE_IDX 0 378 - #define mmSDMA1_RLC0_RB_RPTR_HI 0x0144 379 - #define mmSDMA1_RLC0_RB_RPTR_HI_BASE_IDX 0 380 - #define mmSDMA1_RLC0_RB_WPTR 0x0145 381 - #define mmSDMA1_RLC0_RB_WPTR_BASE_IDX 0 382 - #define mmSDMA1_RLC0_RB_WPTR_HI 0x0146 383 - #define mmSDMA1_RLC0_RB_WPTR_HI_BASE_IDX 0 384 - #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x0147 385 - #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 386 - #define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x0148 387 - #define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 388 - #define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x0149 389 - #define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 390 - #define mmSDMA1_RLC0_IB_CNTL 0x014a 391 - #define mmSDMA1_RLC0_IB_CNTL_BASE_IDX 0 392 - #define mmSDMA1_RLC0_IB_RPTR 0x014b 393 - #define mmSDMA1_RLC0_IB_RPTR_BASE_IDX 0 394 - #define mmSDMA1_RLC0_IB_OFFSET 0x014c 395 - #define mmSDMA1_RLC0_IB_OFFSET_BASE_IDX 0 396 - #define mmSDMA1_RLC0_IB_BASE_LO 0x014d 397 - #define mmSDMA1_RLC0_IB_BASE_LO_BASE_IDX 0 398 - #define mmSDMA1_RLC0_IB_BASE_HI 0x014e 399 - #define mmSDMA1_RLC0_IB_BASE_HI_BASE_IDX 0 400 - #define mmSDMA1_RLC0_IB_SIZE 0x014f 401 - #define mmSDMA1_RLC0_IB_SIZE_BASE_IDX 0 402 - #define mmSDMA1_RLC0_SKIP_CNTL 0x0150 403 - #define mmSDMA1_RLC0_SKIP_CNTL_BASE_IDX 0 404 - #define mmSDMA1_RLC0_CONTEXT_STATUS 0x0151 405 - #define mmSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX 0 406 - #define mmSDMA1_RLC0_DOORBELL 0x0152 407 - #define mmSDMA1_RLC0_DOORBELL_BASE_IDX 0 408 - #define mmSDMA1_RLC0_STATUS 0x0168 409 - #define mmSDMA1_RLC0_STATUS_BASE_IDX 0 410 - #define mmSDMA1_RLC0_DOORBELL_LOG 0x0169 411 - #define mmSDMA1_RLC0_DOORBELL_LOG_BASE_IDX 0 412 - #define mmSDMA1_RLC0_WATERMARK 0x016a 413 - #define mmSDMA1_RLC0_WATERMARK_BASE_IDX 0 414 - #define mmSDMA1_RLC0_DOORBELL_OFFSET 0x016b 415 - #define mmSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX 0 416 - #define mmSDMA1_RLC0_CSA_ADDR_LO 0x016c 417 - #define mmSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX 0 418 - #define mmSDMA1_RLC0_CSA_ADDR_HI 0x016d 419 - #define mmSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX 0 420 - #define mmSDMA1_RLC0_IB_SUB_REMAIN 0x016f 421 - #define mmSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX 0 422 - #define mmSDMA1_RLC0_PREEMPT 0x0170 423 - #define mmSDMA1_RLC0_PREEMPT_BASE_IDX 0 424 - #define mmSDMA1_RLC0_DUMMY_REG 0x0171 425 - #define mmSDMA1_RLC0_DUMMY_REG_BASE_IDX 0 426 - #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x0172 427 - #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 428 - #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x0173 429 - #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 430 - #define mmSDMA1_RLC0_RB_AQL_CNTL 0x0174 431 - #define mmSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX 0 432 - #define mmSDMA1_RLC0_MINOR_PTR_UPDATE 0x0175 433 - #define mmSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 434 - #define mmSDMA1_RLC0_MIDCMD_DATA0 0x0180 435 - #define mmSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX 0 436 - #define mmSDMA1_RLC0_MIDCMD_DATA1 0x0181 437 - #define mmSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX 0 438 - #define mmSDMA1_RLC0_MIDCMD_DATA2 0x0182 439 - #define mmSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX 0 440 - #define mmSDMA1_RLC0_MIDCMD_DATA3 0x0183 441 - #define mmSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX 0 442 - #define mmSDMA1_RLC0_MIDCMD_DATA4 0x0184 443 - #define mmSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX 0 444 - #define mmSDMA1_RLC0_MIDCMD_DATA5 0x0185 445 - #define mmSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX 0 446 - #define mmSDMA1_RLC0_MIDCMD_DATA6 0x0186 447 - #define mmSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX 0 448 - #define mmSDMA1_RLC0_MIDCMD_DATA7 0x0187 449 - #define mmSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX 0 450 - #define mmSDMA1_RLC0_MIDCMD_DATA8 0x0188 451 - #define mmSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX 0 452 - #define mmSDMA1_RLC0_MIDCMD_CNTL 0x0189 453 - #define mmSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX 0 454 - #define mmSDMA1_RLC1_RB_CNTL 0x01a0 455 - #define mmSDMA1_RLC1_RB_CNTL_BASE_IDX 0 456 - #define mmSDMA1_RLC1_RB_BASE 0x01a1 457 - #define mmSDMA1_RLC1_RB_BASE_BASE_IDX 0 458 - #define mmSDMA1_RLC1_RB_BASE_HI 0x01a2 459 - #define mmSDMA1_RLC1_RB_BASE_HI_BASE_IDX 0 460 - #define mmSDMA1_RLC1_RB_RPTR 0x01a3 461 - #define mmSDMA1_RLC1_RB_RPTR_BASE_IDX 0 462 - #define mmSDMA1_RLC1_RB_RPTR_HI 0x01a4 463 - #define mmSDMA1_RLC1_RB_RPTR_HI_BASE_IDX 0 464 - #define mmSDMA1_RLC1_RB_WPTR 0x01a5 465 - #define mmSDMA1_RLC1_RB_WPTR_BASE_IDX 0 466 - #define mmSDMA1_RLC1_RB_WPTR_HI 0x01a6 467 - #define mmSDMA1_RLC1_RB_WPTR_HI_BASE_IDX 0 468 - #define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x01a7 469 - #define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 470 - #define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x01a8 471 - #define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 472 - #define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x01a9 473 - #define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 474 - #define mmSDMA1_RLC1_IB_CNTL 0x01aa 475 - #define mmSDMA1_RLC1_IB_CNTL_BASE_IDX 0 476 - #define mmSDMA1_RLC1_IB_RPTR 0x01ab 477 - #define mmSDMA1_RLC1_IB_RPTR_BASE_IDX 0 478 - #define mmSDMA1_RLC1_IB_OFFSET 0x01ac 479 - #define mmSDMA1_RLC1_IB_OFFSET_BASE_IDX 0 480 - #define mmSDMA1_RLC1_IB_BASE_LO 0x01ad 481 - #define mmSDMA1_RLC1_IB_BASE_LO_BASE_IDX 0 482 - #define mmSDMA1_RLC1_IB_BASE_HI 0x01ae 483 - #define mmSDMA1_RLC1_IB_BASE_HI_BASE_IDX 0 484 - #define mmSDMA1_RLC1_IB_SIZE 0x01af 485 - #define mmSDMA1_RLC1_IB_SIZE_BASE_IDX 0 486 - #define mmSDMA1_RLC1_SKIP_CNTL 0x01b0 487 - #define mmSDMA1_RLC1_SKIP_CNTL_BASE_IDX 0 488 - #define mmSDMA1_RLC1_CONTEXT_STATUS 0x01b1 489 - #define mmSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX 0 490 - #define mmSDMA1_RLC1_DOORBELL 0x01b2 491 - #define mmSDMA1_RLC1_DOORBELL_BASE_IDX 0 492 - #define mmSDMA1_RLC1_STATUS 0x01c8 493 - #define mmSDMA1_RLC1_STATUS_BASE_IDX 0 494 - #define mmSDMA1_RLC1_DOORBELL_LOG 0x01c9 495 - #define mmSDMA1_RLC1_DOORBELL_LOG_BASE_IDX 0 496 - #define mmSDMA1_RLC1_WATERMARK 0x01ca 497 - #define mmSDMA1_RLC1_WATERMARK_BASE_IDX 0 498 - #define mmSDMA1_RLC1_DOORBELL_OFFSET 0x01cb 499 - #define mmSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX 0 500 - #define mmSDMA1_RLC1_CSA_ADDR_LO 0x01cc 501 - #define mmSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX 0 502 - #define mmSDMA1_RLC1_CSA_ADDR_HI 0x01cd 503 - #define mmSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX 0 504 - #define mmSDMA1_RLC1_IB_SUB_REMAIN 0x01cf 505 - #define mmSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX 0 506 - #define mmSDMA1_RLC1_PREEMPT 0x01d0 507 - #define mmSDMA1_RLC1_PREEMPT_BASE_IDX 0 508 - #define mmSDMA1_RLC1_DUMMY_REG 0x01d1 509 - #define mmSDMA1_RLC1_DUMMY_REG_BASE_IDX 0 510 - #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x01d2 511 - #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 512 - #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x01d3 513 - #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 514 - #define mmSDMA1_RLC1_RB_AQL_CNTL 0x01d4 515 - #define mmSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX 0 516 - #define mmSDMA1_RLC1_MINOR_PTR_UPDATE 0x01d5 517 - #define mmSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 518 - #define mmSDMA1_RLC1_MIDCMD_DATA0 0x01e0 519 - #define mmSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX 0 520 - #define mmSDMA1_RLC1_MIDCMD_DATA1 0x01e1 521 - #define mmSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX 0 522 - #define mmSDMA1_RLC1_MIDCMD_DATA2 0x01e2 523 - #define mmSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX 0 524 - #define mmSDMA1_RLC1_MIDCMD_DATA3 0x01e3 525 - #define mmSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX 0 526 - #define mmSDMA1_RLC1_MIDCMD_DATA4 0x01e4 527 - #define mmSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX 0 528 - #define mmSDMA1_RLC1_MIDCMD_DATA5 0x01e5 529 - #define mmSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX 0 530 - #define mmSDMA1_RLC1_MIDCMD_DATA6 0x01e6 531 - #define mmSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX 0 532 - #define mmSDMA1_RLC1_MIDCMD_DATA7 0x01e7 533 - #define mmSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX 0 534 - #define mmSDMA1_RLC1_MIDCMD_DATA8 0x01e8 535 - #define mmSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX 0 536 - #define mmSDMA1_RLC1_MIDCMD_CNTL 0x01e9 537 - #define mmSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX 0 538 - 539 - #endif
-1810
drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h
··· 1 - /* 2 - * Copyright (C) 2017 Advanced Micro Devices, Inc. 3 - * 4 - * Permission is hereby granted, free of charge, to any person obtaining a 5 - * copy of this software and associated documentation files (the "Software"), 6 - * to deal in the Software without restriction, including without limitation 7 - * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 - * and/or sell copies of the Software, and to permit persons to whom the 9 - * Software is furnished to do so, subject to the following conditions: 10 - * 11 - * The above copyright notice and this permission notice shall be included 12 - * in all copies or substantial portions of the Software. 13 - * 14 - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 - */ 21 - #ifndef _sdma1_4_0_SH_MASK_HEADER 22 - #define _sdma1_4_0_SH_MASK_HEADER 23 - 24 - 25 - // addressBlock: sdma1_sdma1dec 26 - //SDMA1_UCODE_ADDR 27 - #define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0 28 - #define SDMA1_UCODE_ADDR__VALUE_MASK 0x00001FFFL 29 - //SDMA1_UCODE_DATA 30 - #define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0 31 - #define SDMA1_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 32 - //SDMA1_VM_CNTL 33 - #define SDMA1_VM_CNTL__CMD__SHIFT 0x0 34 - #define SDMA1_VM_CNTL__CMD_MASK 0x0000000FL 35 - //SDMA1_VM_CTX_LO 36 - #define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2 37 - #define SDMA1_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL 38 - //SDMA1_VM_CTX_HI 39 - #define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0 40 - #define SDMA1_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL 41 - //SDMA1_ACTIVE_FCN_ID 42 - #define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 43 - #define SDMA1_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 44 - #define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x1f 45 - #define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 46 - #define SDMA1_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L 47 - #define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000L 48 - //SDMA1_VM_CTX_CNTL 49 - #define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x0 50 - #define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x4 51 - #define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x00000001L 52 - #define SDMA1_VM_CTX_CNTL__VMID_MASK 0x000000F0L 53 - //SDMA1_VIRT_RESET_REQ 54 - #define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x0 55 - #define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x1f 56 - #define SDMA1_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 57 - #define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000L 58 - //SDMA1_VF_ENABLE 59 - #define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0 60 - #define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x00000001L 61 - //SDMA1_CONTEXT_REG_TYPE0 62 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT 0x0 63 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1 64 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2 65 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT 0x3 66 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI__SHIFT 0x4 67 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT 0x5 68 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI__SHIFT 0x6 69 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 70 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 71 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 72 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa 73 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT 0xb 74 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT 0xc 75 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT 0xd 76 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT 0xe 77 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT 0xf 78 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT 0x10 79 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT 0x11 80 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT 0x12 81 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT 0x13 82 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x00000001L 83 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x00000002L 84 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK 0x00000004L 85 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK 0x00000008L 86 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI_MASK 0x00000010L 87 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK 0x00000020L 88 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI_MASK 0x00000040L 89 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L 90 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L 91 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L 92 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK 0x00000400L 93 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK 0x00000800L 94 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK 0x00001000L 95 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK 0x00002000L 96 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK 0x00004000L 97 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK 0x00008000L 98 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK 0x00010000L 99 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK 0x00020000L 100 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK 0x00040000L 101 - #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK 0x00080000L 102 - //SDMA1_CONTEXT_REG_TYPE1 103 - #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS__SHIFT 0x8 104 - #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT 0x9 105 - #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa 106 - #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET__SHIFT 0xb 107 - #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT 0xc 108 - #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT 0xd 109 - #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe 110 - #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT 0xf 111 - #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT 0x10 112 - #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT 0x11 113 - #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 114 - #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 115 - #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL__SHIFT 0x14 116 - #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 117 - #define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 118 - #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS_MASK 0x00000100L 119 - #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK 0x00000200L 120 - #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK 0x00000400L 121 - #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET_MASK 0x00000800L 122 - #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK 0x00001000L 123 - #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK 0x00002000L 124 - #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L 125 - #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK 0x00008000L 126 - #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK 0x00010000L 127 - #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK 0x00020000L 128 - #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L 129 - #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L 130 - #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL_MASK 0x00100000L 131 - #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L 132 - #define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L 133 - //SDMA1_CONTEXT_REG_TYPE2 134 - #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT 0x0 135 - #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1 136 - #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2 137 - #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT 0x3 138 - #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT 0x4 139 - #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT 0x5 140 - #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6__SHIFT 0x6 141 - #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7__SHIFT 0x7 142 - #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8__SHIFT 0x8 143 - #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT 0x9 144 - #define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa 145 - #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x00000001L 146 - #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x00000002L 147 - #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK 0x00000004L 148 - #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK 0x00000008L 149 - #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK 0x00000010L 150 - #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK 0x00000020L 151 - #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6_MASK 0x00000040L 152 - #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7_MASK 0x00000080L 153 - #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8_MASK 0x00000100L 154 - #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK 0x00000200L 155 - #define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L 156 - //SDMA1_CONTEXT_REG_TYPE3 157 - #define SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 158 - #define SDMA1_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL 159 - //SDMA1_PUB_REG_TYPE0 160 - #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x0 161 - #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1 162 - #define SDMA1_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 163 - #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL__SHIFT 0x4 164 - #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO__SHIFT 0x5 165 - #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI__SHIFT 0x6 166 - #define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID__SHIFT 0x7 167 - #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL__SHIFT 0x8 168 - #define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ__SHIFT 0x9 169 - #define SDMA1_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa 170 - #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0__SHIFT 0xb 171 - #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1__SHIFT 0xc 172 - #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2__SHIFT 0xd 173 - #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3__SHIFT 0xe 174 - #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0__SHIFT 0xf 175 - #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1__SHIFT 0x10 176 - #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2__SHIFT 0x11 177 - #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3__SHIFT 0x12 178 - #define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL__SHIFT 0x13 179 - #define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 180 - #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 181 - #define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x1a 182 - #define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT 0x1b 183 - #define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT 0x1c 184 - #define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x1d 185 - #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG__SHIFT 0x1e 186 - #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ__SHIFT 0x1f 187 - #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x00000001L 188 - #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x00000002L 189 - #define SDMA1_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L 190 - #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL_MASK 0x00000010L 191 - #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO_MASK 0x00000020L 192 - #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI_MASK 0x00000040L 193 - #define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID_MASK 0x00000080L 194 - #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL_MASK 0x00000100L 195 - #define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ_MASK 0x00000200L 196 - #define SDMA1_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L 197 - #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0_MASK 0x00000800L 198 - #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1_MASK 0x00001000L 199 - #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2_MASK 0x00002000L 200 - #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3_MASK 0x00004000L 201 - #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0_MASK 0x00008000L 202 - #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1_MASK 0x00010000L 203 - #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2_MASK 0x00020000L 204 - #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3_MASK 0x00040000L 205 - #define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL_MASK 0x00080000L 206 - #define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L 207 - #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L 208 - #define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK 0x04000000L 209 - #define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK 0x08000000L 210 - #define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK 0x10000000L 211 - #define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK 0x20000000L 212 - #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_MASK 0x40000000L 213 - #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ_MASK 0x80000000L 214 - //SDMA1_PUB_REG_TYPE1 215 - #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI__SHIFT 0x0 216 - #define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 217 - #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH__SHIFT 0x2 218 - #define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH__SHIFT 0x3 219 - #define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM__SHIFT 0x4 220 - #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG__SHIFT 0x5 221 - #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG__SHIFT 0x6 222 - #define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL__SHIFT 0x7 223 - #define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG__SHIFT 0x8 224 - #define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM__SHIFT 0x9 225 - #define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL__SHIFT 0xa 226 - #define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE__SHIFT 0xb 227 - #define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM__SHIFT 0xc 228 - #define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM__SHIFT 0xd 229 - #define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe 230 - #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf 231 - #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 232 - #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 233 - #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG__SHIFT 0x12 234 - #define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD__SHIFT 0x13 235 - #define SDMA1_PUB_REG_TYPE1__SDMA1_ID__SHIFT 0x14 236 - #define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION__SHIFT 0x15 237 - #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER__SHIFT 0x16 238 - #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR__SHIFT 0x17 239 - #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT 0x18 240 - #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT 0x19 241 - #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT 0x1a 242 - #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT 0x1b 243 - #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL__SHIFT 0x1c 244 - #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK__SHIFT 0x1d 245 - #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS__SHIFT 0x1e 246 - #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS__SHIFT 0x1f 247 - #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI_MASK 0x00000001L 248 - #define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L 249 - #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_MASK 0x00000004L 250 - #define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH_MASK 0x00000008L 251 - #define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM_MASK 0x00000010L 252 - #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG_MASK 0x00000020L 253 - #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG_MASK 0x00000040L 254 - #define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL_MASK 0x00000080L 255 - #define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG_MASK 0x00000100L 256 - #define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM_MASK 0x00000200L 257 - #define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL_MASK 0x00000400L 258 - #define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE_MASK 0x00000800L 259 - #define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM_MASK 0x00001000L 260 - #define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM_MASK 0x00002000L 261 - #define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L 262 - #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L 263 - #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L 264 - #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L 265 - #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG_MASK 0x00040000L 266 - #define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD_MASK 0x00080000L 267 - #define SDMA1_PUB_REG_TYPE1__SDMA1_ID_MASK 0x00100000L 268 - #define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION_MASK 0x00200000L 269 - #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_MASK 0x00400000L 270 - #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR_MASK 0x00800000L 271 - #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK 0x01000000L 272 - #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK 0x02000000L 273 - #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK 0x04000000L 274 - #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK 0x08000000L 275 - #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL_MASK 0x10000000L 276 - #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK_MASK 0x20000000L 277 - #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS_MASK 0x40000000L 278 - #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS_MASK 0x80000000L 279 - //SDMA1_PUB_REG_TYPE2 280 - #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0__SHIFT 0x0 281 - #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1__SHIFT 0x1 282 - #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2__SHIFT 0x2 283 - #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0__SHIFT 0x3 284 - #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1__SHIFT 0x4 285 - #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0__SHIFT 0x5 286 - #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1__SHIFT 0x6 287 - #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT__SHIFT 0x7 288 - #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE__SHIFT 0x8 289 - #define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE__SHIFT 0x9 290 - #define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT__SHIFT 0xa 291 - #define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2__SHIFT 0xb 292 - #define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG__SHIFT 0xc 293 - #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO__SHIFT 0xd 294 - #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI__SHIFT 0xe 295 - #define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM__SHIFT 0xf 296 - #define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG__SHIFT 0x10 297 - #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0__SHIFT 0x11 298 - #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1__SHIFT 0x12 299 - #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2__SHIFT 0x13 300 - #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3__SHIFT 0x14 301 - #define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER__SHIFT 0x15 302 - #define SDMA1_PUB_REG_TYPE2__SDMA1_UNBREAKABLE__SHIFT 0x16 303 - #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL__SHIFT 0x17 304 - #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT__SHIFT 0x18 305 - #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT__SHIFT 0x19 306 - #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a 307 - #define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL__SHIFT 0x1b 308 - #define SDMA1_PUB_REG_TYPE2__SDMA1_MMHUB_TRUSTLVL__SHIFT 0x1c 309 - #define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d 310 - #define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL__SHIFT 0x1e 311 - #define SDMA1_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f 312 - #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0_MASK 0x00000001L 313 - #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1_MASK 0x00000002L 314 - #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2_MASK 0x00000004L 315 - #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0_MASK 0x00000008L 316 - #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1_MASK 0x00000010L 317 - #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0_MASK 0x00000020L 318 - #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1_MASK 0x00000040L 319 - #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT_MASK 0x00000080L 320 - #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE_MASK 0x00000100L 321 - #define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE_MASK 0x00000200L 322 - #define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT_MASK 0x00000400L 323 - #define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2_MASK 0x00000800L 324 - #define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG_MASK 0x00001000L 325 - #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO_MASK 0x00002000L 326 - #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI_MASK 0x00004000L 327 - #define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM_MASK 0x00008000L 328 - #define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG_MASK 0x00010000L 329 - #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0_MASK 0x00020000L 330 - #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1_MASK 0x00040000L 331 - #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2_MASK 0x00080000L 332 - #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3_MASK 0x00100000L 333 - #define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER_MASK 0x00200000L 334 - #define SDMA1_PUB_REG_TYPE2__SDMA1_UNBREAKABLE_MASK 0x00400000L 335 - #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL_MASK 0x00800000L 336 - #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT_MASK 0x01000000L 337 - #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT_MASK 0x02000000L 338 - #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L 339 - #define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL_MASK 0x08000000L 340 - #define SDMA1_PUB_REG_TYPE2__SDMA1_MMHUB_TRUSTLVL_MASK 0x10000000L 341 - #define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L 342 - #define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL_MASK 0x40000000L 343 - #define SDMA1_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L 344 - //SDMA1_PUB_REG_TYPE3 345 - #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA__SHIFT 0x0 346 - #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX__SHIFT 0x1 347 - #define SDMA1_PUB_REG_TYPE3__RESERVED__SHIFT 0x2 348 - #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA_MASK 0x00000001L 349 - #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX_MASK 0x00000002L 350 - #define SDMA1_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL 351 - //SDMA1_MMHUB_CNTL 352 - #define SDMA1_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 353 - #define SDMA1_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL 354 - //SDMA1_CONTEXT_GROUP_BOUNDARY 355 - #define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 356 - #define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL 357 - //SDMA1_POWER_CNTL 358 - #define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 359 - #define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 360 - #define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 361 - #define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 362 - #define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 363 - #define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L 364 - #define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L 365 - #define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L 366 - #define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L 367 - #define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L 368 - //SDMA1_CLK_CTRL 369 - #define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0 370 - #define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 371 - #define SDMA1_CLK_CTRL__RESERVED__SHIFT 0xc 372 - #define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 373 - #define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 374 - #define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 375 - #define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 376 - #define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 377 - #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 378 - #define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 379 - #define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 380 - #define SDMA1_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 381 - #define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 382 - #define SDMA1_CLK_CTRL__RESERVED_MASK 0x00FFF000L 383 - #define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 384 - #define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 385 - #define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 386 - #define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 387 - #define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 388 - #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 389 - #define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 390 - #define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 391 - //SDMA1_CNTL 392 - #define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0 393 - #define SDMA1_CNTL__UTC_L1_ENABLE__SHIFT 0x1 394 - #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 395 - #define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 396 - #define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 397 - #define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 398 - #define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 399 - #define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 400 - #define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 401 - #define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 402 - #define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 403 - #define SDMA1_CNTL__TRAP_ENABLE_MASK 0x00000001L 404 - #define SDMA1_CNTL__UTC_L1_ENABLE_MASK 0x00000002L 405 - #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L 406 - #define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L 407 - #define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L 408 - #define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L 409 - #define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 410 - #define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L 411 - #define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L 412 - #define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L 413 - #define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L 414 - //SDMA1_CHICKEN_BITS 415 - #define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 416 - #define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 417 - #define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 418 - #define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 419 - #define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 420 - #define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 421 - #define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 422 - #define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 423 - #define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 424 - #define SDMA1_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 425 - #define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a 426 - #define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c 427 - #define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e 428 - #define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L 429 - #define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L 430 - #define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L 431 - #define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L 432 - #define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L 433 - #define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L 434 - #define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L 435 - #define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L 436 - #define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L 437 - #define SDMA1_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L 438 - #define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L 439 - #define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L 440 - #define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L 441 - //SDMA1_GB_ADDR_CONFIG 442 - #define SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 443 - #define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 444 - #define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 445 - #define SDMA1_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 446 - #define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 447 - #define SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 448 - #define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 449 - #define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 450 - #define SDMA1_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 451 - #define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 452 - //SDMA1_GB_ADDR_CONFIG_READ 453 - #define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 454 - #define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 455 - #define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 456 - #define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc 457 - #define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 458 - #define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 459 - #define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 460 - #define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 461 - #define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L 462 - #define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 463 - //SDMA1_RB_RPTR_FETCH_HI 464 - #define SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 465 - #define SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 466 - //SDMA1_SEM_WAIT_FAIL_TIMER_CNTL 467 - #define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 468 - #define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL 469 - //SDMA1_RB_RPTR_FETCH 470 - #define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 471 - #define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 472 - //SDMA1_IB_OFFSET_FETCH 473 - #define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 474 - #define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 475 - //SDMA1_PROGRAM 476 - #define SDMA1_PROGRAM__STREAM__SHIFT 0x0 477 - #define SDMA1_PROGRAM__STREAM_MASK 0xFFFFFFFFL 478 - //SDMA1_STATUS_REG 479 - #define SDMA1_STATUS_REG__IDLE__SHIFT 0x0 480 - #define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1 481 - #define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2 482 - #define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3 483 - #define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 484 - #define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 485 - #define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 486 - #define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 487 - #define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 488 - #define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9 489 - #define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa 490 - #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 491 - #define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc 492 - #define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 493 - #define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe 494 - #define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 495 - #define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 496 - #define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 497 - #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 498 - #define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 499 - #define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 500 - #define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 501 - #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 502 - #define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 503 - #define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a 504 - #define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 505 - #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 506 - #define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e 507 - #define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 508 - #define SDMA1_STATUS_REG__IDLE_MASK 0x00000001L 509 - #define SDMA1_STATUS_REG__REG_IDLE_MASK 0x00000002L 510 - #define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x00000004L 511 - #define SDMA1_STATUS_REG__RB_FULL_MASK 0x00000008L 512 - #define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L 513 - #define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L 514 - #define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L 515 - #define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L 516 - #define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L 517 - #define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x00000200L 518 - #define SDMA1_STATUS_REG__EX_IDLE_MASK 0x00000400L 519 - #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L 520 - #define SDMA1_STATUS_REG__PACKET_READY_MASK 0x00001000L 521 - #define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L 522 - #define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x00004000L 523 - #define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L 524 - #define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L 525 - #define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L 526 - #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L 527 - #define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L 528 - #define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L 529 - #define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L 530 - #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L 531 - #define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L 532 - #define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x04000000L 533 - #define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L 534 - #define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L 535 - #define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000L 536 - #define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L 537 - //SDMA1_STATUS1_REG 538 - #define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 539 - #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 540 - #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 541 - #define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 542 - #define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 543 - #define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 544 - #define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 545 - #define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 546 - #define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 547 - #define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 548 - #define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 549 - #define SDMA1_STATUS1_REG__EX_START__SHIFT 0xf 550 - #define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 551 - #define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 552 - #define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L 553 - #define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L 554 - #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L 555 - #define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L 556 - #define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L 557 - #define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L 558 - #define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L 559 - #define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L 560 - #define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L 561 - #define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L 562 - #define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L 563 - #define SDMA1_STATUS1_REG__EX_START_MASK 0x00008000L 564 - #define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L 565 - #define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L 566 - //SDMA1_RD_BURST_CNTL 567 - #define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 568 - #define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L 569 - //SDMA1_HBM_PAGE_CONFIG 570 - #define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 571 - #define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L 572 - //SDMA1_UCODE_CHECKSUM 573 - #define SDMA1_UCODE_CHECKSUM__DATA__SHIFT 0x0 574 - #define SDMA1_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 575 - //SDMA1_F32_CNTL 576 - #define SDMA1_F32_CNTL__HALT__SHIFT 0x0 577 - #define SDMA1_F32_CNTL__STEP__SHIFT 0x1 578 - #define SDMA1_F32_CNTL__HALT_MASK 0x00000001L 579 - #define SDMA1_F32_CNTL__STEP_MASK 0x00000002L 580 - //SDMA1_FREEZE 581 - #define SDMA1_FREEZE__PREEMPT__SHIFT 0x0 582 - #define SDMA1_FREEZE__FREEZE__SHIFT 0x4 583 - #define SDMA1_FREEZE__FROZEN__SHIFT 0x5 584 - #define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6 585 - #define SDMA1_FREEZE__PREEMPT_MASK 0x00000001L 586 - #define SDMA1_FREEZE__FREEZE_MASK 0x00000010L 587 - #define SDMA1_FREEZE__FROZEN_MASK 0x00000020L 588 - #define SDMA1_FREEZE__F32_FREEZE_MASK 0x00000040L 589 - //SDMA1_PHASE0_QUANTUM 590 - #define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0 591 - #define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 592 - #define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 593 - #define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL 594 - #define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L 595 - #define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000L 596 - //SDMA1_PHASE1_QUANTUM 597 - #define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0 598 - #define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8 599 - #define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 600 - #define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL 601 - #define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L 602 - #define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000L 603 - //SDMA1_EDC_CONFIG 604 - #define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1 605 - #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 606 - #define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 607 - #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L 608 - //SDMA1_BA_THRESHOLD 609 - #define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0 610 - #define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 611 - #define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL 612 - #define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L 613 - //SDMA1_ID 614 - #define SDMA1_ID__DEVICE_ID__SHIFT 0x0 615 - #define SDMA1_ID__DEVICE_ID_MASK 0x000000FFL 616 - //SDMA1_VERSION 617 - #define SDMA1_VERSION__MINVER__SHIFT 0x0 618 - #define SDMA1_VERSION__MAJVER__SHIFT 0x8 619 - #define SDMA1_VERSION__REV__SHIFT 0x10 620 - #define SDMA1_VERSION__MINVER_MASK 0x0000007FL 621 - #define SDMA1_VERSION__MAJVER_MASK 0x00007F00L 622 - #define SDMA1_VERSION__REV_MASK 0x003F0000L 623 - //SDMA1_EDC_COUNTER 624 - #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 625 - #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 626 - #define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 627 - #define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 628 - #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 629 - #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 630 - #define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 631 - #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 632 - #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 633 - #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 634 - #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa 635 - #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb 636 - #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc 637 - #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd 638 - #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe 639 - #define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf 640 - #define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 641 - #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L 642 - #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L 643 - #define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L 644 - #define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L 645 - #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L 646 - #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L 647 - #define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L 648 - #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L 649 - #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L 650 - #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L 651 - #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L 652 - #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L 653 - #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L 654 - #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L 655 - #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L 656 - #define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L 657 - #define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L 658 - //SDMA1_EDC_COUNTER_CLEAR 659 - #define SDMA1_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 660 - #define SDMA1_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L 661 - //SDMA1_STATUS2_REG 662 - #define SDMA1_STATUS2_REG__ID__SHIFT 0x0 663 - #define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 664 - #define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10 665 - #define SDMA1_STATUS2_REG__ID_MASK 0x00000003L 666 - #define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL 667 - #define SDMA1_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L 668 - //SDMA1_ATOMIC_CNTL 669 - #define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 670 - #define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 671 - #define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 672 - #define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L 673 - //SDMA1_ATOMIC_PREOP_LO 674 - #define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 675 - #define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 676 - //SDMA1_ATOMIC_PREOP_HI 677 - #define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 678 - #define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 679 - //SDMA1_UTCL1_CNTL 680 - #define SDMA1_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 681 - #define SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 682 - #define SDMA1_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb 683 - #define SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe 684 - #define SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 685 - #define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d 686 - #define SDMA1_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L 687 - #define SDMA1_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL 688 - #define SDMA1_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L 689 - #define SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L 690 - #define SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L 691 - #define SDMA1_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L 692 - //SDMA1_UTCL1_WATERMK 693 - #define SDMA1_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 694 - #define SDMA1_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa 695 - #define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 696 - #define SDMA1_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a 697 - #define SDMA1_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL 698 - #define SDMA1_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L 699 - #define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L 700 - #define SDMA1_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L 701 - //SDMA1_UTCL1_RD_STATUS 702 - #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 703 - #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 704 - #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 705 - #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 706 - #define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 707 - #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 708 - #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 709 - #define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 710 - #define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 711 - #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 712 - #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 713 - #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 714 - #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 715 - #define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 716 - #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 717 - #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 718 - #define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 719 - #define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 720 - #define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 721 - #define SDMA1_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 722 - #define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 723 - #define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 724 - #define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 725 - #define SDMA1_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 726 - #define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d 727 - #define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e 728 - #define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f 729 - #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 730 - #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 731 - #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 732 - #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 733 - #define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 734 - #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 735 - #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 736 - #define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 737 - #define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 738 - #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 739 - #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 740 - #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 741 - #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 742 - #define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 743 - #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 744 - #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 745 - #define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 746 - #define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 747 - #define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L 748 - #define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L 749 - #define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L 750 - #define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L 751 - #define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L 752 - #define SDMA1_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L 753 - #define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L 754 - #define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L 755 - #define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L 756 - //SDMA1_UTCL1_WR_STATUS 757 - #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 758 - #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 759 - #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 760 - #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 761 - #define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 762 - #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 763 - #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 764 - #define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 765 - #define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 766 - #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 767 - #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 768 - #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 769 - #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 770 - #define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 771 - #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 772 - #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 773 - #define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 774 - #define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 775 - #define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 776 - #define SDMA1_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 777 - #define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 778 - #define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 779 - #define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 780 - #define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 781 - #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c 782 - #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d 783 - #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e 784 - #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f 785 - #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 786 - #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 787 - #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 788 - #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 789 - #define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 790 - #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 791 - #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 792 - #define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 793 - #define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 794 - #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 795 - #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 796 - #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 797 - #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 798 - #define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 799 - #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 800 - #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 801 - #define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 802 - #define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 803 - #define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L 804 - #define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L 805 - #define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L 806 - #define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L 807 - #define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L 808 - #define SDMA1_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L 809 - #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L 810 - #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L 811 - #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L 812 - #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L 813 - //SDMA1_UTCL1_INV0 814 - #define SDMA1_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 815 - #define SDMA1_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 816 - #define SDMA1_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 817 - #define SDMA1_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 818 - #define SDMA1_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 819 - #define SDMA1_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 820 - #define SDMA1_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 821 - #define SDMA1_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 822 - #define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 823 - #define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 824 - #define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa 825 - #define SDMA1_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 826 - #define SDMA1_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc 827 - #define SDMA1_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 828 - #define SDMA1_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L 829 - #define SDMA1_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L 830 - #define SDMA1_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L 831 - #define SDMA1_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L 832 - #define SDMA1_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L 833 - #define SDMA1_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L 834 - #define SDMA1_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L 835 - #define SDMA1_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L 836 - #define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L 837 - #define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L 838 - #define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L 839 - #define SDMA1_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L 840 - #define SDMA1_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L 841 - #define SDMA1_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L 842 - //SDMA1_UTCL1_INV1 843 - #define SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 844 - #define SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL 845 - //SDMA1_UTCL1_INV2 846 - #define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 847 - #define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL 848 - //SDMA1_UTCL1_RD_XNACK0 849 - #define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 850 - #define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 851 - //SDMA1_UTCL1_RD_XNACK1 852 - #define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 853 - #define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 854 - #define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 855 - #define SDMA1_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a 856 - #define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 857 - #define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L 858 - #define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 859 - #define SDMA1_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L 860 - //SDMA1_UTCL1_WR_XNACK0 861 - #define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 862 - #define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 863 - //SDMA1_UTCL1_WR_XNACK1 864 - #define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 865 - #define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 866 - #define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 867 - #define SDMA1_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a 868 - #define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 869 - #define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L 870 - #define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 871 - #define SDMA1_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L 872 - //SDMA1_UTCL1_TIMEOUT 873 - #define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 874 - #define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 875 - #define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL 876 - #define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L 877 - //SDMA1_UTCL1_PAGE 878 - #define SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 879 - #define SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 880 - #define SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 881 - #define SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 882 - #define SDMA1_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L 883 - #define SDMA1_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL 884 - #define SDMA1_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L 885 - #define SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L 886 - //SDMA1_POWER_CNTL_IDLE 887 - #define SDMA1_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 888 - #define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 889 - #define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 890 - #define SDMA1_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL 891 - #define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L 892 - #define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L 893 - //SDMA1_RELAX_ORDERING_LUT 894 - #define SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 895 - #define SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 896 - #define SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 897 - #define SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 898 - #define SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 899 - #define SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 900 - #define SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 901 - #define SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 902 - #define SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 903 - #define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 904 - #define SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb 905 - #define SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc 906 - #define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 907 - #define SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 908 - #define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 909 - #define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 910 - #define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d 911 - #define SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 912 - #define SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 913 - #define SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 914 - #define SDMA1_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L 915 - #define SDMA1_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L 916 - #define SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 917 - #define SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 918 - #define SDMA1_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 919 - #define SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 920 - #define SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 921 - #define SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 922 - #define SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 923 - #define SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L 924 - #define SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L 925 - #define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 926 - #define SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 927 - #define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 928 - #define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 929 - #define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L 930 - #define SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 931 - #define SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 932 - //SDMA1_CHICKEN_BITS_2 933 - #define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 934 - #define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 935 - //SDMA1_STATUS3_REG 936 - #define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 937 - #define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 938 - #define SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 939 - #define SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL 940 - #define SDMA1_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L 941 - #define SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L 942 - //SDMA1_PHYSICAL_ADDR_LO 943 - #define SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 944 - #define SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 945 - #define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 946 - #define SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc 947 - #define SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L 948 - #define SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L 949 - #define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L 950 - #define SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L 951 - //SDMA1_PHYSICAL_ADDR_HI 952 - #define SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 953 - #define SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL 954 - //SDMA1_PHASE2_QUANTUM 955 - #define SDMA1_PHASE2_QUANTUM__UNIT__SHIFT 0x0 956 - #define SDMA1_PHASE2_QUANTUM__VALUE__SHIFT 0x8 957 - #define SDMA1_PHASE2_QUANTUM__PREFER__SHIFT 0x1e 958 - #define SDMA1_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL 959 - #define SDMA1_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L 960 - #define SDMA1_PHASE2_QUANTUM__PREFER_MASK 0x40000000L 961 - //SDMA1_ERROR_LOG 962 - #define SDMA1_ERROR_LOG__OVERRIDE__SHIFT 0x0 963 - #define SDMA1_ERROR_LOG__STATUS__SHIFT 0x10 964 - #define SDMA1_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 965 - #define SDMA1_ERROR_LOG__STATUS_MASK 0xFFFF0000L 966 - //SDMA1_PUB_DUMMY_REG0 967 - #define SDMA1_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 968 - #define SDMA1_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL 969 - //SDMA1_PUB_DUMMY_REG1 970 - #define SDMA1_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 971 - #define SDMA1_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL 972 - //SDMA1_PUB_DUMMY_REG2 973 - #define SDMA1_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 974 - #define SDMA1_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL 975 - //SDMA1_PUB_DUMMY_REG3 976 - #define SDMA1_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 977 - #define SDMA1_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL 978 - //SDMA1_F32_COUNTER 979 - #define SDMA1_F32_COUNTER__VALUE__SHIFT 0x0 980 - #define SDMA1_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 981 - //SDMA1_UNBREAKABLE 982 - #define SDMA1_UNBREAKABLE__VALUE__SHIFT 0x0 983 - #define SDMA1_UNBREAKABLE__VALUE_MASK 0x00000001L 984 - //SDMA1_PERFMON_CNTL 985 - #define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 986 - #define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 987 - #define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 988 - #define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa 989 - #define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb 990 - #define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc 991 - #define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L 992 - #define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L 993 - #define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL 994 - #define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L 995 - #define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L 996 - #define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L 997 - //SDMA1_PERFCOUNTER0_RESULT 998 - #define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 999 - #define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1000 - //SDMA1_PERFCOUNTER1_RESULT 1001 - #define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 1002 - #define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1003 - //SDMA1_PERFCOUNTER_TAG_DELAY_RANGE 1004 - #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 1005 - #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe 1006 - #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c 1007 - #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL 1008 - #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L 1009 - #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L 1010 - //SDMA1_CRD_CNTL 1011 - #define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 1012 - #define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 1013 - #define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 1014 - #define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 1015 - //SDMA1_MMHUB_TRUSTLVL 1016 - #define SDMA1_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0 1017 - #define SDMA1_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x3 1018 - #define SDMA1_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x6 1019 - #define SDMA1_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x9 1020 - #define SDMA1_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0xc 1021 - #define SDMA1_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0xf 1022 - #define SDMA1_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x12 1023 - #define SDMA1_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x15 1024 - #define SDMA1_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L 1025 - #define SDMA1_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L 1026 - #define SDMA1_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001C0L 1027 - #define SDMA1_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000E00L 1028 - #define SDMA1_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L 1029 - #define SDMA1_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L 1030 - #define SDMA1_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001C0000L 1031 - #define SDMA1_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00E00000L 1032 - //SDMA1_GPU_IOV_VIOLATION_LOG 1033 - #define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 1034 - #define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 1035 - #define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 1036 - #define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12 1037 - #define SDMA1_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 1038 - #define SDMA1_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 1039 - #define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 1040 - #define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 1041 - #define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 1042 - #define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL 1043 - #define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L 1044 - #define SDMA1_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L 1045 - #define SDMA1_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L 1046 - #define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L 1047 - //SDMA1_ULV_CNTL 1048 - #define SDMA1_ULV_CNTL__HYSTERESIS__SHIFT 0x0 1049 - #define SDMA1_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d 1050 - #define SDMA1_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e 1051 - #define SDMA1_ULV_CNTL__ULV_STATUS__SHIFT 0x1f 1052 - #define SDMA1_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL 1053 - #define SDMA1_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L 1054 - #define SDMA1_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L 1055 - #define SDMA1_ULV_CNTL__ULV_STATUS_MASK 0x80000000L 1056 - //SDMA1_EA_DBIT_ADDR_DATA 1057 - #define SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 1058 - #define SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL 1059 - //SDMA1_EA_DBIT_ADDR_INDEX 1060 - #define SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 1061 - #define SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L 1062 - //SDMA1_GFX_RB_CNTL 1063 - #define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 1064 - #define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 1065 - #define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1066 - #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1067 - #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1068 - #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1069 - #define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 1070 - #define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 1071 - #define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1072 - #define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1073 - #define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1074 - #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1075 - #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1076 - #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1077 - #define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L 1078 - #define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L 1079 - //SDMA1_GFX_RB_BASE 1080 - #define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0 1081 - #define SDMA1_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1082 - //SDMA1_GFX_RB_BASE_HI 1083 - #define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 1084 - #define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1085 - //SDMA1_GFX_RB_RPTR 1086 - #define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x0 1087 - #define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1088 - //SDMA1_GFX_RB_RPTR_HI 1089 - #define SDMA1_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 1090 - #define SDMA1_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1091 - //SDMA1_GFX_RB_WPTR 1092 - #define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x0 1093 - #define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1094 - //SDMA1_GFX_RB_WPTR_HI 1095 - #define SDMA1_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 1096 - #define SDMA1_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1097 - //SDMA1_GFX_RB_WPTR_POLL_CNTL 1098 - #define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1099 - #define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1100 - #define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1101 - #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1102 - #define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1103 - #define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1104 - #define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1105 - #define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1106 - #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1107 - #define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1108 - //SDMA1_GFX_RB_RPTR_ADDR_HI 1109 - #define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1110 - #define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1111 - //SDMA1_GFX_RB_RPTR_ADDR_LO 1112 - #define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1113 - #define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1114 - //SDMA1_GFX_IB_CNTL 1115 - #define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 1116 - #define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1117 - #define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1118 - #define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 1119 - #define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1120 - #define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1121 - #define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1122 - #define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1123 - //SDMA1_GFX_IB_RPTR 1124 - #define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2 1125 - #define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1126 - //SDMA1_GFX_IB_OFFSET 1127 - #define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 1128 - #define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1129 - //SDMA1_GFX_IB_BASE_LO 1130 - #define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 1131 - #define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1132 - //SDMA1_GFX_IB_BASE_HI 1133 - #define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 1134 - #define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1135 - //SDMA1_GFX_IB_SIZE 1136 - #define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0 1137 - #define SDMA1_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL 1138 - //SDMA1_GFX_SKIP_CNTL 1139 - #define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1140 - #define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1141 - //SDMA1_GFX_CONTEXT_STATUS 1142 - #define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1143 - #define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 1144 - #define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1145 - #define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1146 - #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1147 - #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1148 - #define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1149 - #define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1150 - #define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1151 - #define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1152 - #define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1153 - #define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1154 - #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1155 - #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1156 - #define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1157 - #define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1158 - //SDMA1_GFX_DOORBELL 1159 - #define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c 1160 - #define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 1161 - #define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000L 1162 - #define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000L 1163 - //SDMA1_GFX_CONTEXT_CNTL 1164 - #define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 1165 - #define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L 1166 - //SDMA1_GFX_STATUS 1167 - #define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1168 - #define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1169 - #define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1170 - #define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1171 - //SDMA1_GFX_DOORBELL_LOG 1172 - #define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1173 - #define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 1174 - #define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1175 - #define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1176 - //SDMA1_GFX_WATERMARK 1177 - #define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1178 - #define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1179 - #define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1180 - #define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1181 - //SDMA1_GFX_DOORBELL_OFFSET 1182 - #define SDMA1_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1183 - #define SDMA1_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1184 - //SDMA1_GFX_CSA_ADDR_LO 1185 - #define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 1186 - #define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1187 - //SDMA1_GFX_CSA_ADDR_HI 1188 - #define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 1189 - #define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1190 - //SDMA1_GFX_IB_SUB_REMAIN 1191 - #define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1192 - #define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1193 - //SDMA1_GFX_PREEMPT 1194 - #define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 1195 - #define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1196 - //SDMA1_GFX_DUMMY_REG 1197 - #define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 1198 - #define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1199 - //SDMA1_GFX_RB_WPTR_POLL_ADDR_HI 1200 - #define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1201 - #define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1202 - //SDMA1_GFX_RB_WPTR_POLL_ADDR_LO 1203 - #define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1204 - #define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1205 - //SDMA1_GFX_RB_AQL_CNTL 1206 - #define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1207 - #define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1208 - #define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1209 - #define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1210 - #define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1211 - #define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1212 - //SDMA1_GFX_MINOR_PTR_UPDATE 1213 - #define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1214 - #define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1215 - //SDMA1_GFX_MIDCMD_DATA0 1216 - #define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 1217 - #define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1218 - //SDMA1_GFX_MIDCMD_DATA1 1219 - #define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 1220 - #define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1221 - //SDMA1_GFX_MIDCMD_DATA2 1222 - #define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 1223 - #define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1224 - //SDMA1_GFX_MIDCMD_DATA3 1225 - #define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 1226 - #define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1227 - //SDMA1_GFX_MIDCMD_DATA4 1228 - #define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 1229 - #define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1230 - //SDMA1_GFX_MIDCMD_DATA5 1231 - #define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 1232 - #define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1233 - //SDMA1_GFX_MIDCMD_DATA6 1234 - #define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 1235 - #define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1236 - //SDMA1_GFX_MIDCMD_DATA7 1237 - #define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 1238 - #define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1239 - //SDMA1_GFX_MIDCMD_DATA8 1240 - #define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 1241 - #define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1242 - //SDMA1_GFX_MIDCMD_CNTL 1243 - #define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1244 - #define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1245 - #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1246 - #define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1247 - #define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1248 - #define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1249 - #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1250 - #define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1251 - //SDMA1_PAGE_RB_CNTL 1252 - #define SDMA1_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 1253 - #define SDMA1_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 1254 - #define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1255 - #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1256 - #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1257 - #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1258 - #define SDMA1_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 1259 - #define SDMA1_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 1260 - #define SDMA1_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1261 - #define SDMA1_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1262 - #define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1263 - #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1264 - #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1265 - #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1266 - #define SDMA1_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L 1267 - #define SDMA1_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L 1268 - //SDMA1_PAGE_RB_BASE 1269 - #define SDMA1_PAGE_RB_BASE__ADDR__SHIFT 0x0 1270 - #define SDMA1_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1271 - //SDMA1_PAGE_RB_BASE_HI 1272 - #define SDMA1_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 1273 - #define SDMA1_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1274 - //SDMA1_PAGE_RB_RPTR 1275 - #define SDMA1_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 1276 - #define SDMA1_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1277 - //SDMA1_PAGE_RB_RPTR_HI 1278 - #define SDMA1_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 1279 - #define SDMA1_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1280 - //SDMA1_PAGE_RB_WPTR 1281 - #define SDMA1_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 1282 - #define SDMA1_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1283 - //SDMA1_PAGE_RB_WPTR_HI 1284 - #define SDMA1_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 1285 - #define SDMA1_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1286 - //SDMA1_PAGE_RB_WPTR_POLL_CNTL 1287 - #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1288 - #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1289 - #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1290 - #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1291 - #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1292 - #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1293 - #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1294 - #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1295 - #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1296 - #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1297 - //SDMA1_PAGE_RB_RPTR_ADDR_HI 1298 - #define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1299 - #define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1300 - //SDMA1_PAGE_RB_RPTR_ADDR_LO 1301 - #define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1302 - #define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1303 - //SDMA1_PAGE_IB_CNTL 1304 - #define SDMA1_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 1305 - #define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1306 - #define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1307 - #define SDMA1_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 1308 - #define SDMA1_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1309 - #define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1310 - #define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1311 - #define SDMA1_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1312 - //SDMA1_PAGE_IB_RPTR 1313 - #define SDMA1_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 1314 - #define SDMA1_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1315 - //SDMA1_PAGE_IB_OFFSET 1316 - #define SDMA1_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 1317 - #define SDMA1_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1318 - //SDMA1_PAGE_IB_BASE_LO 1319 - #define SDMA1_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 1320 - #define SDMA1_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1321 - //SDMA1_PAGE_IB_BASE_HI 1322 - #define SDMA1_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 1323 - #define SDMA1_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1324 - //SDMA1_PAGE_IB_SIZE 1325 - #define SDMA1_PAGE_IB_SIZE__SIZE__SHIFT 0x0 1326 - #define SDMA1_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL 1327 - //SDMA1_PAGE_SKIP_CNTL 1328 - #define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1329 - #define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1330 - //SDMA1_PAGE_CONTEXT_STATUS 1331 - #define SDMA1_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1332 - #define SDMA1_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 1333 - #define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1334 - #define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1335 - #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1336 - #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1337 - #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1338 - #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1339 - #define SDMA1_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1340 - #define SDMA1_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1341 - #define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1342 - #define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1343 - #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1344 - #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1345 - #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1346 - #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1347 - //SDMA1_PAGE_DOORBELL 1348 - #define SDMA1_PAGE_DOORBELL__ENABLE__SHIFT 0x1c 1349 - #define SDMA1_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e 1350 - #define SDMA1_PAGE_DOORBELL__ENABLE_MASK 0x10000000L 1351 - #define SDMA1_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L 1352 - //SDMA1_PAGE_STATUS 1353 - #define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1354 - #define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1355 - #define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1356 - #define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1357 - //SDMA1_PAGE_DOORBELL_LOG 1358 - #define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1359 - #define SDMA1_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 1360 - #define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1361 - #define SDMA1_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1362 - //SDMA1_PAGE_WATERMARK 1363 - #define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1364 - #define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1365 - #define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1366 - #define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1367 - //SDMA1_PAGE_DOORBELL_OFFSET 1368 - #define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1369 - #define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1370 - //SDMA1_PAGE_CSA_ADDR_LO 1371 - #define SDMA1_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 1372 - #define SDMA1_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1373 - //SDMA1_PAGE_CSA_ADDR_HI 1374 - #define SDMA1_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 1375 - #define SDMA1_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1376 - //SDMA1_PAGE_IB_SUB_REMAIN 1377 - #define SDMA1_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1378 - #define SDMA1_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1379 - //SDMA1_PAGE_PREEMPT 1380 - #define SDMA1_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 1381 - #define SDMA1_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1382 - //SDMA1_PAGE_DUMMY_REG 1383 - #define SDMA1_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 1384 - #define SDMA1_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1385 - //SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI 1386 - #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1387 - #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1388 - //SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO 1389 - #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1390 - #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1391 - //SDMA1_PAGE_RB_AQL_CNTL 1392 - #define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1393 - #define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1394 - #define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1395 - #define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1396 - #define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1397 - #define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1398 - //SDMA1_PAGE_MINOR_PTR_UPDATE 1399 - #define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1400 - #define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1401 - //SDMA1_PAGE_MIDCMD_DATA0 1402 - #define SDMA1_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 1403 - #define SDMA1_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1404 - //SDMA1_PAGE_MIDCMD_DATA1 1405 - #define SDMA1_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 1406 - #define SDMA1_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1407 - //SDMA1_PAGE_MIDCMD_DATA2 1408 - #define SDMA1_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 1409 - #define SDMA1_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1410 - //SDMA1_PAGE_MIDCMD_DATA3 1411 - #define SDMA1_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 1412 - #define SDMA1_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1413 - //SDMA1_PAGE_MIDCMD_DATA4 1414 - #define SDMA1_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 1415 - #define SDMA1_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1416 - //SDMA1_PAGE_MIDCMD_DATA5 1417 - #define SDMA1_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 1418 - #define SDMA1_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1419 - //SDMA1_PAGE_MIDCMD_DATA6 1420 - #define SDMA1_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 1421 - #define SDMA1_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1422 - //SDMA1_PAGE_MIDCMD_DATA7 1423 - #define SDMA1_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 1424 - #define SDMA1_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1425 - //SDMA1_PAGE_MIDCMD_DATA8 1426 - #define SDMA1_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 1427 - #define SDMA1_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1428 - //SDMA1_PAGE_MIDCMD_CNTL 1429 - #define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1430 - #define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1431 - #define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1432 - #define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1433 - #define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1434 - #define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1435 - #define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1436 - #define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1437 - //SDMA1_RLC0_RB_CNTL 1438 - #define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 1439 - #define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 1440 - #define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1441 - #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1442 - #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1443 - #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1444 - #define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 1445 - #define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 1446 - #define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1447 - #define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1448 - #define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1449 - #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1450 - #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1451 - #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1452 - #define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L 1453 - #define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L 1454 - //SDMA1_RLC0_RB_BASE 1455 - #define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 1456 - #define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1457 - //SDMA1_RLC0_RB_BASE_HI 1458 - #define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 1459 - #define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1460 - //SDMA1_RLC0_RB_RPTR 1461 - #define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 1462 - #define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1463 - //SDMA1_RLC0_RB_RPTR_HI 1464 - #define SDMA1_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 1465 - #define SDMA1_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1466 - //SDMA1_RLC0_RB_WPTR 1467 - #define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 1468 - #define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1469 - //SDMA1_RLC0_RB_WPTR_HI 1470 - #define SDMA1_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 1471 - #define SDMA1_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1472 - //SDMA1_RLC0_RB_WPTR_POLL_CNTL 1473 - #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1474 - #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1475 - #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1476 - #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1477 - #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1478 - #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1479 - #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1480 - #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1481 - #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1482 - #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1483 - //SDMA1_RLC0_RB_RPTR_ADDR_HI 1484 - #define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1485 - #define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1486 - //SDMA1_RLC0_RB_RPTR_ADDR_LO 1487 - #define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1488 - #define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1489 - //SDMA1_RLC0_IB_CNTL 1490 - #define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 1491 - #define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1492 - #define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1493 - #define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 1494 - #define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1495 - #define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1496 - #define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1497 - #define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1498 - //SDMA1_RLC0_IB_RPTR 1499 - #define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 1500 - #define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1501 - //SDMA1_RLC0_IB_OFFSET 1502 - #define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 1503 - #define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1504 - //SDMA1_RLC0_IB_BASE_LO 1505 - #define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 1506 - #define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1507 - //SDMA1_RLC0_IB_BASE_HI 1508 - #define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 1509 - #define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1510 - //SDMA1_RLC0_IB_SIZE 1511 - #define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0 1512 - #define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL 1513 - //SDMA1_RLC0_SKIP_CNTL 1514 - #define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1515 - #define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1516 - //SDMA1_RLC0_CONTEXT_STATUS 1517 - #define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1518 - #define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 1519 - #define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1520 - #define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1521 - #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1522 - #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1523 - #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1524 - #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1525 - #define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1526 - #define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1527 - #define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1528 - #define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1529 - #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1530 - #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1531 - #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1532 - #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1533 - //SDMA1_RLC0_DOORBELL 1534 - #define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 1535 - #define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 1536 - #define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000L 1537 - #define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L 1538 - //SDMA1_RLC0_STATUS 1539 - #define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1540 - #define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1541 - #define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1542 - #define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1543 - //SDMA1_RLC0_DOORBELL_LOG 1544 - #define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1545 - #define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 1546 - #define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1547 - #define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1548 - //SDMA1_RLC0_WATERMARK 1549 - #define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1550 - #define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1551 - #define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1552 - #define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1553 - //SDMA1_RLC0_DOORBELL_OFFSET 1554 - #define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1555 - #define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1556 - //SDMA1_RLC0_CSA_ADDR_LO 1557 - #define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 1558 - #define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1559 - //SDMA1_RLC0_CSA_ADDR_HI 1560 - #define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 1561 - #define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1562 - //SDMA1_RLC0_IB_SUB_REMAIN 1563 - #define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1564 - #define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1565 - //SDMA1_RLC0_PREEMPT 1566 - #define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 1567 - #define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1568 - //SDMA1_RLC0_DUMMY_REG 1569 - #define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 1570 - #define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1571 - //SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 1572 - #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1573 - #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1574 - //SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 1575 - #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1576 - #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1577 - //SDMA1_RLC0_RB_AQL_CNTL 1578 - #define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1579 - #define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1580 - #define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1581 - #define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1582 - #define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1583 - #define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1584 - //SDMA1_RLC0_MINOR_PTR_UPDATE 1585 - #define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1586 - #define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1587 - //SDMA1_RLC0_MIDCMD_DATA0 1588 - #define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 1589 - #define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1590 - //SDMA1_RLC0_MIDCMD_DATA1 1591 - #define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 1592 - #define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1593 - //SDMA1_RLC0_MIDCMD_DATA2 1594 - #define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 1595 - #define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1596 - //SDMA1_RLC0_MIDCMD_DATA3 1597 - #define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 1598 - #define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1599 - //SDMA1_RLC0_MIDCMD_DATA4 1600 - #define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 1601 - #define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1602 - //SDMA1_RLC0_MIDCMD_DATA5 1603 - #define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 1604 - #define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1605 - //SDMA1_RLC0_MIDCMD_DATA6 1606 - #define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 1607 - #define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1608 - //SDMA1_RLC0_MIDCMD_DATA7 1609 - #define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 1610 - #define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1611 - //SDMA1_RLC0_MIDCMD_DATA8 1612 - #define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 1613 - #define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1614 - //SDMA1_RLC0_MIDCMD_CNTL 1615 - #define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1616 - #define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1617 - #define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1618 - #define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1619 - #define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1620 - #define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1621 - #define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1622 - #define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1623 - //SDMA1_RLC1_RB_CNTL 1624 - #define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 1625 - #define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 1626 - #define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1627 - #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1628 - #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1629 - #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1630 - #define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 1631 - #define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 1632 - #define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1633 - #define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1634 - #define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1635 - #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1636 - #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1637 - #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1638 - #define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L 1639 - #define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L 1640 - //SDMA1_RLC1_RB_BASE 1641 - #define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0 1642 - #define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1643 - //SDMA1_RLC1_RB_BASE_HI 1644 - #define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 1645 - #define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1646 - //SDMA1_RLC1_RB_RPTR 1647 - #define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 1648 - #define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1649 - //SDMA1_RLC1_RB_RPTR_HI 1650 - #define SDMA1_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 1651 - #define SDMA1_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1652 - //SDMA1_RLC1_RB_WPTR 1653 - #define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 1654 - #define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1655 - //SDMA1_RLC1_RB_WPTR_HI 1656 - #define SDMA1_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 1657 - #define SDMA1_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1658 - //SDMA1_RLC1_RB_WPTR_POLL_CNTL 1659 - #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1660 - #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1661 - #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1662 - #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1663 - #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1664 - #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1665 - #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1666 - #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1667 - #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1668 - #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1669 - //SDMA1_RLC1_RB_RPTR_ADDR_HI 1670 - #define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1671 - #define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1672 - //SDMA1_RLC1_RB_RPTR_ADDR_LO 1673 - #define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1674 - #define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1675 - //SDMA1_RLC1_IB_CNTL 1676 - #define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 1677 - #define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1678 - #define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1679 - #define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 1680 - #define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1681 - #define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1682 - #define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1683 - #define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1684 - //SDMA1_RLC1_IB_RPTR 1685 - #define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 1686 - #define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1687 - //SDMA1_RLC1_IB_OFFSET 1688 - #define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 1689 - #define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1690 - //SDMA1_RLC1_IB_BASE_LO 1691 - #define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 1692 - #define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1693 - //SDMA1_RLC1_IB_BASE_HI 1694 - #define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 1695 - #define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1696 - //SDMA1_RLC1_IB_SIZE 1697 - #define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0 1698 - #define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL 1699 - //SDMA1_RLC1_SKIP_CNTL 1700 - #define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1701 - #define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1702 - //SDMA1_RLC1_CONTEXT_STATUS 1703 - #define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1704 - #define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 1705 - #define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1706 - #define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1707 - #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1708 - #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1709 - #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1710 - #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1711 - #define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1712 - #define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1713 - #define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1714 - #define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1715 - #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1716 - #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1717 - #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1718 - #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1719 - //SDMA1_RLC1_DOORBELL 1720 - #define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 1721 - #define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 1722 - #define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000L 1723 - #define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L 1724 - //SDMA1_RLC1_STATUS 1725 - #define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1726 - #define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1727 - #define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1728 - #define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1729 - //SDMA1_RLC1_DOORBELL_LOG 1730 - #define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1731 - #define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 1732 - #define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1733 - #define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1734 - //SDMA1_RLC1_WATERMARK 1735 - #define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1736 - #define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1737 - #define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1738 - #define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1739 - //SDMA1_RLC1_DOORBELL_OFFSET 1740 - #define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1741 - #define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1742 - //SDMA1_RLC1_CSA_ADDR_LO 1743 - #define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 1744 - #define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1745 - //SDMA1_RLC1_CSA_ADDR_HI 1746 - #define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 1747 - #define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1748 - //SDMA1_RLC1_IB_SUB_REMAIN 1749 - #define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1750 - #define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1751 - //SDMA1_RLC1_PREEMPT 1752 - #define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 1753 - #define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1754 - //SDMA1_RLC1_DUMMY_REG 1755 - #define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 1756 - #define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1757 - //SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 1758 - #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1759 - #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1760 - //SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 1761 - #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1762 - #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1763 - //SDMA1_RLC1_RB_AQL_CNTL 1764 - #define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1765 - #define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1766 - #define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1767 - #define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1768 - #define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1769 - #define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1770 - //SDMA1_RLC1_MINOR_PTR_UPDATE 1771 - #define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1772 - #define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1773 - //SDMA1_RLC1_MIDCMD_DATA0 1774 - #define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 1775 - #define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1776 - //SDMA1_RLC1_MIDCMD_DATA1 1777 - #define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 1778 - #define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1779 - //SDMA1_RLC1_MIDCMD_DATA2 1780 - #define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 1781 - #define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1782 - //SDMA1_RLC1_MIDCMD_DATA3 1783 - #define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 1784 - #define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1785 - //SDMA1_RLC1_MIDCMD_DATA4 1786 - #define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 1787 - #define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1788 - //SDMA1_RLC1_MIDCMD_DATA5 1789 - #define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 1790 - #define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1791 - //SDMA1_RLC1_MIDCMD_DATA6 1792 - #define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 1793 - #define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1794 - //SDMA1_RLC1_MIDCMD_DATA7 1795 - #define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 1796 - #define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1797 - //SDMA1_RLC1_MIDCMD_DATA8 1798 - #define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 1799 - #define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1800 - //SDMA1_RLC1_MIDCMD_CNTL 1801 - #define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1802 - #define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1803 - #define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1804 - #define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1805 - #define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1806 - #define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1807 - #define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1808 - #define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1809 - 1810 - #endif