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Merge tag 'riscv/for-v5.4-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V fixes from Paul Walmsley:

- Ensure that exclusive-load reservations are terminated after system
call or exception handling. This primarily affects QEMU, which does
not expire load reservations.

- Fix an issue primarily affecting RV32 platforms that can cause the DT
header to be corrupted, causing boot failures.

* tag 'riscv/for-v5.4-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: Fix memblock reservation for device tree blob
RISC-V: Clear load reservations while restoring hart contexts

+32 -2
+1
arch/riscv/include/asm/asm.h
··· 22 22 23 23 #define REG_L __REG_SEL(ld, lw) 24 24 #define REG_S __REG_SEL(sd, sw) 25 + #define REG_SC __REG_SEL(sc.d, sc.w) 25 26 #define SZREG __REG_SEL(8, 4) 26 27 #define LGREG __REG_SEL(3, 2) 27 28
+20 -1
arch/riscv/kernel/entry.S
··· 98 98 */ 99 99 .macro RESTORE_ALL 100 100 REG_L a0, PT_SSTATUS(sp) 101 - REG_L a2, PT_SEPC(sp) 101 + /* 102 + * The current load reservation is effectively part of the processor's 103 + * state, in the sense that load reservations cannot be shared between 104 + * different hart contexts. We can't actually save and restore a load 105 + * reservation, so instead here we clear any existing reservation -- 106 + * it's always legal for implementations to clear load reservations at 107 + * any point (as long as the forward progress guarantee is kept, but 108 + * we'll ignore that here). 109 + * 110 + * Dangling load reservations can be the result of taking a trap in the 111 + * middle of an LR/SC sequence, but can also be the result of a taken 112 + * forward branch around an SC -- which is how we implement CAS. As a 113 + * result we need to clear reservations between the last CAS and the 114 + * jump back to the new context. While it is unlikely the store 115 + * completes, implementations are allowed to expand reservations to be 116 + * arbitrarily large. 117 + */ 118 + REG_L a2, PT_SEPC(sp) 119 + REG_SC x0, a2, PT_SEPC(sp) 120 + 102 121 csrw CSR_SSTATUS, a0 103 122 csrw CSR_SEPC, a2 104 123
+11 -1
arch/riscv/mm/init.c
··· 11 11 #include <linux/swap.h> 12 12 #include <linux/sizes.h> 13 13 #include <linux/of_fdt.h> 14 + #include <linux/libfdt.h> 14 15 15 16 #include <asm/fixmap.h> 16 17 #include <asm/tlbflush.h> ··· 83 82 } 84 83 #endif /* CONFIG_BLK_DEV_INITRD */ 85 84 85 + static phys_addr_t dtb_early_pa __initdata; 86 + 86 87 void __init setup_bootmem(void) 87 88 { 88 89 struct memblock_region *reg; ··· 120 117 setup_initrd(); 121 118 #endif /* CONFIG_BLK_DEV_INITRD */ 122 119 123 - early_init_fdt_reserve_self(); 120 + /* 121 + * Avoid using early_init_fdt_reserve_self() since __pa() does 122 + * not work for DTB pointers that are fixmap addresses 123 + */ 124 + memblock_reserve(dtb_early_pa, fdt_totalsize(dtb_early_va)); 125 + 124 126 early_init_fdt_scan_reserved_mem(); 125 127 memblock_allow_resize(); 126 128 memblock_dump_all(); ··· 401 393 402 394 /* Save pointer to DTB for early FDT parsing */ 403 395 dtb_early_va = (void *)fix_to_virt(FIX_FDT) + (dtb_pa & ~PAGE_MASK); 396 + /* Save physical address for memblock reservation */ 397 + dtb_early_pa = dtb_pa; 404 398 } 405 399 406 400 static void __init setup_vm_final(void)