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Merge tag 'imx-bindings-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX DT bindings update for 5.20:

- Compatibles for new boards: i.MX7 based Toradex Colibri, DH electronics
i.MX8M Plus DHCOM and PDK2, TQMa8MPxL, Carrier for Toradex i.MX6 Apalis,
i.MX93 EVK, PHYTEC i.MX8MM based board.
- A series from Abel Vesa (and Viorel Suman) to split fsl,scu.txt bindings
into multiple subsystem bindings in yaml format.
- Fix 'line too long' warning caused by Toradex Colibri boards.

* tag 'imx-bindings-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
dt-bindings: arm: add TQMa8MPxL board
dt-bindings: firmware: Add fsl,scu yaml file
dt-bindings: watchdog: Add fsl,scu-wdt yaml file
dt-bindings: thermal: Add fsl,scu-thermal yaml file
dt-bindings: rtc: Add fsl,scu-rtc yaml file
dt-bindings: power: Add fsl,scu-pd yaml file
dt-bindings: nvmem: Add fsl,scu-ocotp yaml file
dt-bindings: input: Add fsl,scu-key yaml file
dt-bindings: pinctrl: imx: Add fsl,scu-iomux yaml file
dt-bindings: clk: imx: Add fsl,scu-clk yaml file
bindings: arm: fsl: Add PHYTEC i.MX8MM devicetree bindings
dt-bindings: arm: fsl: Add carrier for toradex,apalis-imx6q
dt-bindings: arm: fsl: Decrease the line length
dt-bindings: arm: Add DH electronics i.MX8M Plus DHCOM and PDK2
dt-bindings: arm: fsl: add toradex,colibri-imx7s/d/d-emmc-iris/-v2
dt-bindings: arm: fsl: add imx93 11x11 evk board
dt-bindings: arm: fsl: correct 1g vs. 1gb in toradex,colibri-imx6ull-*

Link: https://lore.kernel.org/r/20220709082951.15123-3-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Arnd Bergmann 8128bfe3 bfcfa1bd

+614 -285
-271
Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
··· 1 - NXP i.MX System Controller Firmware (SCFW) 2 - -------------------------------------------------------------------- 3 - 4 - The System Controller Firmware (SCFW) is a low-level system function 5 - which runs on a dedicated Cortex-M core to provide power, clock, and 6 - resource management. It exists on some i.MX8 processors. e.g. i.MX8QM 7 - (QM, QP), and i.MX8QX (QXP, DX). 8 - 9 - The AP communicates with the SC using a multi-ported MU module found 10 - in the LSIO subsystem. The current definition of this MU module provides 11 - 5 remote AP connections to the SC to support up to 5 execution environments 12 - (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces 13 - with the LSIO DSC IP bus. The SC firmware will communicate with this MU 14 - using the MSI bus. 15 - 16 - System Controller Device Node: 17 - ============================================================ 18 - 19 - The scu node with the following properties shall be under the /firmware/ node. 20 - 21 - Required properties: 22 - ------------------- 23 - - compatible: should be "fsl,imx-scu". 24 - - mbox-names: should include "tx0", "tx1", "tx2", "tx3", 25 - "rx0", "rx1", "rx2", "rx3"; 26 - include "gip3" if want to support general MU interrupt. 27 - - mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for 28 - rx, and 1 optional MU channel for general interrupt. 29 - All MU channels must be in the same MU instance. 30 - Cross instances are not allowed. The MU instance can only 31 - be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need 32 - to make sure use the one which is not conflict with other 33 - execution environments. e.g. ATF. 34 - Note: 35 - Channel 0 must be "tx0" or "rx0". 36 - Channel 1 must be "tx1" or "rx1". 37 - Channel 2 must be "tx2" or "rx2". 38 - Channel 3 must be "tx3" or "rx3". 39 - General interrupt rx channel must be "gip3". 40 - e.g. 41 - mboxes = <&lsio_mu1 0 0 42 - &lsio_mu1 0 1 43 - &lsio_mu1 0 2 44 - &lsio_mu1 0 3 45 - &lsio_mu1 1 0 46 - &lsio_mu1 1 1 47 - &lsio_mu1 1 2 48 - &lsio_mu1 1 3 49 - &lsio_mu1 3 3>; 50 - See Documentation/devicetree/bindings/mailbox/fsl,mu.yaml 51 - for detailed mailbox binding. 52 - 53 - Note: Each mu which supports general interrupt should have an alias correctly 54 - numbered in "aliases" node. 55 - e.g. 56 - aliases { 57 - mu1 = &lsio_mu1; 58 - }; 59 - 60 - i.MX SCU Client Device Node: 61 - ============================================================ 62 - 63 - Client nodes are maintained as children of the relevant IMX-SCU device node. 64 - 65 - Power domain bindings based on SCU Message Protocol 66 - ------------------------------------------------------------ 67 - 68 - This binding for the SCU power domain providers uses the generic power 69 - domain binding[2]. 70 - 71 - Required properties: 72 - - compatible: Should be one of: 73 - "fsl,imx8qm-scu-pd", 74 - "fsl,imx8qxp-scu-pd" 75 - followed by "fsl,scu-pd" 76 - 77 - - #power-domain-cells: Must be 1. Contains the Resource ID used by 78 - SCU commands. 79 - See detailed Resource ID list from: 80 - include/dt-bindings/firmware/imx/rsrc.h 81 - 82 - Clock bindings based on SCU Message Protocol 83 - ------------------------------------------------------------ 84 - 85 - This binding uses the common clock binding[1]. 86 - 87 - Required properties: 88 - - compatible: Should be one of: 89 - "fsl,imx8dxl-clk" 90 - "fsl,imx8qm-clk" 91 - "fsl,imx8qxp-clk" 92 - followed by "fsl,scu-clk" 93 - - #clock-cells: Should be 2. 94 - Contains the Resource and Clock ID value. 95 - - clocks: List of clock specifiers, must contain an entry for 96 - each required entry in clock-names 97 - - clock-names: Should include entries "xtal_32KHz", "xtal_24MHz" 98 - 99 - The clock consumer should specify the desired clock by having the clock 100 - ID in its "clocks" phandle cell. 101 - 102 - See the full list of clock IDs from: 103 - include/dt-bindings/clock/imx8qxp-clock.h 104 - 105 - Pinctrl bindings based on SCU Message Protocol 106 - ------------------------------------------------------------ 107 - 108 - This binding uses the i.MX common pinctrl binding[3]. 109 - 110 - Required properties: 111 - - compatible: Should be one of: 112 - "fsl,imx8qm-iomuxc", 113 - "fsl,imx8qxp-iomuxc", 114 - "fsl,imx8dxl-iomuxc". 115 - 116 - Required properties for Pinctrl sub nodes: 117 - - fsl,pins: Each entry consists of 3 integers which represents 118 - the mux and config setting for one pin. The first 2 119 - integers <pin_id mux_mode> are specified using a 120 - PIN_FUNC_ID macro, which can be found in 121 - <dt-bindings/pinctrl/pads-imx8qm.h>, 122 - <dt-bindings/pinctrl/pads-imx8qxp.h>, 123 - <dt-bindings/pinctrl/pads-imx8dxl.h>. 124 - The last integer CONFIG is the pad setting value like 125 - pull-up on this pin. 126 - 127 - Please refer to i.MX8QXP Reference Manual for detailed 128 - CONFIG settings. 129 - 130 - [1] Documentation/devicetree/bindings/clock/clock-bindings.txt 131 - [2] Documentation/devicetree/bindings/power/power-domain.yaml 132 - [3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt 133 - 134 - RTC bindings based on SCU Message Protocol 135 - ------------------------------------------------------------ 136 - 137 - Required properties: 138 - - compatible: should be "fsl,imx8qxp-sc-rtc"; 139 - 140 - OCOTP bindings based on SCU Message Protocol 141 - ------------------------------------------------------------ 142 - Required properties: 143 - - compatible: Should be one of: 144 - "fsl,imx8qm-scu-ocotp", 145 - "fsl,imx8qxp-scu-ocotp". 146 - - #address-cells: Must be 1. Contains byte index 147 - - #size-cells: Must be 1. Contains byte length 148 - 149 - Optional Child nodes: 150 - 151 - - Data cells of ocotp: 152 - Detailed bindings are described in bindings/nvmem/nvmem.txt 153 - 154 - Watchdog bindings based on SCU Message Protocol 155 - ------------------------------------------------------------ 156 - 157 - Required properties: 158 - - compatible: should be: 159 - "fsl,imx8qxp-sc-wdt" 160 - followed by "fsl,imx-sc-wdt"; 161 - Optional properties: 162 - - timeout-sec: contains the watchdog timeout in seconds. 163 - 164 - SCU key bindings based on SCU Message Protocol 165 - ------------------------------------------------------------ 166 - 167 - Required properties: 168 - - compatible: should be: 169 - "fsl,imx8qxp-sc-key" 170 - followed by "fsl,imx-sc-key"; 171 - - linux,keycodes: See Documentation/devicetree/bindings/input/input.yaml 172 - 173 - Thermal bindings based on SCU Message Protocol 174 - ------------------------------------------------------------ 175 - 176 - Required properties: 177 - - compatible: Should be : 178 - "fsl,imx8qxp-sc-thermal" 179 - followed by "fsl,imx-sc-thermal"; 180 - 181 - - #thermal-sensor-cells: See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml 182 - for a description. 183 - 184 - Example (imx8qxp): 185 - ------------- 186 - aliases { 187 - mu1 = &lsio_mu1; 188 - }; 189 - 190 - lsio_mu1: mailbox@5d1c0000 { 191 - ... 192 - #mbox-cells = <2>; 193 - }; 194 - 195 - firmware { 196 - scu { 197 - compatible = "fsl,imx-scu"; 198 - mbox-names = "tx0", "tx1", "tx2", "tx3", 199 - "rx0", "rx1", "rx2", "rx3", 200 - "gip3"; 201 - mboxes = <&lsio_mu1 0 0 202 - &lsio_mu1 0 1 203 - &lsio_mu1 0 2 204 - &lsio_mu1 0 3 205 - &lsio_mu1 1 0 206 - &lsio_mu1 1 1 207 - &lsio_mu1 1 2 208 - &lsio_mu1 1 3 209 - &lsio_mu1 3 3>; 210 - 211 - clk: clk { 212 - compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; 213 - #clock-cells = <2>; 214 - }; 215 - 216 - iomuxc { 217 - compatible = "fsl,imx8qxp-iomuxc"; 218 - 219 - pinctrl_lpuart0: lpuart0grp { 220 - fsl,pins = < 221 - SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 222 - SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 223 - >; 224 - }; 225 - ... 226 - }; 227 - 228 - ocotp: imx8qx-ocotp { 229 - compatible = "fsl,imx8qxp-scu-ocotp"; 230 - #address-cells = <1>; 231 - #size-cells = <1>; 232 - 233 - fec_mac0: mac@2c4 { 234 - reg = <0x2c4 8>; 235 - }; 236 - }; 237 - 238 - pd: imx8qx-pd { 239 - compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; 240 - #power-domain-cells = <1>; 241 - }; 242 - 243 - rtc: rtc { 244 - compatible = "fsl,imx8qxp-sc-rtc"; 245 - }; 246 - 247 - scu_key: scu-key { 248 - compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; 249 - linux,keycodes = <KEY_POWER>; 250 - }; 251 - 252 - watchdog { 253 - compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; 254 - timeout-sec = <60>; 255 - }; 256 - 257 - tsens: thermal-sensor { 258 - compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; 259 - #thermal-sensor-cells = <1>; 260 - }; 261 - }; 262 - }; 263 - 264 - serial@5a060000 { 265 - ... 266 - pinctrl-names = "default"; 267 - pinctrl-0 = <&pinctrl_lpuart0>; 268 - clocks = <&uart0_clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>; 269 - clock-names = "ipg"; 270 - power-domains = <&pd IMX_SC_R_UART_0>; 271 - };
+47 -14
Documentation/devicetree/bindings/arm/fsl.yaml
··· 321 321 - enum: 322 322 - toradex,apalis_imx6q-ixora # Apalis iMX6Q/D Module on Ixora Carrier Board 323 323 - toradex,apalis_imx6q-ixora-v1.1 # Apalis iMX6Q/D Module on Ixora V1.1 Carrier Board 324 + - toradex,apalis_imx6q-ixora-v1.2 # Apalis iMX6Q/D Module on Ixora V1.2 Carrier Board 324 325 - toradex,apalis_imx6q-eval # Apalis iMX6Q/D Module on Apalis Evaluation Board 325 326 - const: toradex,apalis_imx6q 326 327 - const: fsl,imx6q ··· 671 670 - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Modules 672 671 items: 673 672 - enum: 674 - - toradex,colibri-imx6ull-aster # Colibri iMX6ULL Module on Aster Carrier Board 675 - - toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Evaluation Board V3 676 - - toradex,colibri-imx6ull-iris # Colibri iMX6ULL Module on Iris Carrier Board 677 - - toradex,colibri-imx6ull-iris-v2 # Colibri iMX6ULL Module on Iris V2 Carrier Board 673 + - toradex,colibri-imx6ull-aster # Aster Carrier Board 674 + - toradex,colibri-imx6ull-eval # Colibri Evaluation Board V3 675 + - toradex,colibri-imx6ull-iris # Iris Carrier Board 676 + - toradex,colibri-imx6ull-iris-v2 # Iris V2 Carrier Board 678 677 - const: toradex,colibri-imx6ull # Colibri iMX6ULL Module 679 678 - const: fsl,imx6ull 680 679 681 680 - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL 1GB (eMMC) Module 682 681 items: 683 682 - enum: 684 - - toradex,colibri-imx6ull-emmc-aster # Colibri iMX6ULL 1G (eMMC) on Aster Carrier Board 685 - - toradex,colibri-imx6ull-emmc-eval # Colibri iMX6ULL 1G (eMMC) on Colibri Evaluation B. V3 686 - - toradex,colibri-imx6ull-emmc-iris # Colibri iMX6ULL 1G (eMMC) on Iris Carrier Board 687 - - toradex,colibri-imx6ull-emmc-iris-v2 # Colibri iMX6ULL 1G (eMMC) on Iris V2 Carrier Board 683 + - toradex,colibri-imx6ull-emmc-aster # Aster Carrier Board 684 + - toradex,colibri-imx6ull-emmc-eval # Colibri Evaluation B. V3 685 + - toradex,colibri-imx6ull-emmc-iris # Iris Carrier Board 686 + - toradex,colibri-imx6ull-emmc-iris-v2 # Iris V2 Carrier Board 688 687 - const: toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module 689 688 - const: fsl,imx6ull 690 689 691 690 - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Wi-Fi / BT Modules 692 691 items: 693 692 - enum: 694 - - toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT M. on Colibri Eval. B. V3 695 - - toradex,colibri-imx6ull-wifi-aster # Colibri iMX6ULL Wi-Fi / BT M. on Aster Carrier Board 696 - - toradex,colibri-imx6ull-wifi-iris # Colibri iMX6ULL Wi-Fi / BT M. on Iris Carrier Board 697 - - toradex,colibri-imx6ull-wifi-iris-v2 # Colibri iMX6ULL Wi-Fi / BT M. on Iris V2 Carrier Board 693 + - toradex,colibri-imx6ull-wifi-eval # Colibri Eval. B. V3 694 + - toradex,colibri-imx6ull-wifi-aster # Aster Carrier Board 695 + - toradex,colibri-imx6ull-wifi-iris # Iris Carrier Board 696 + - toradex,colibri-imx6ull-wifi-iris-v2 # Iris V2 Carrier Board 698 697 - const: toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Module 699 698 - const: fsl,imx6ull 700 699 ··· 739 738 - enum: 740 739 - toradex,colibri-imx7s-aster # Module on Aster Carrier Board 741 740 - toradex,colibri-imx7s-eval-v3 # Module on Colibri Evaluation Board V3 741 + - toradex,colibri-imx7s-iris # Module on Iris Carrier Board 742 + - toradex,colibri-imx7s-iris-v2 # Module on Iris Carrier Board V2 742 743 - const: toradex,colibri-imx7s 743 744 - const: fsl,imx7s 744 745 ··· 792 789 - description: i.MX7D Boards with Toradex Colibri i.MX7D Module 793 790 items: 794 791 - enum: 795 - - toradex,colibri-imx7d-aster # Colibri iMX7D Module on Aster Carrier Board 796 - - toradex,colibri-imx7d-eval-v3 # Colibri iMX7D Module on Colibri Evaluation Board V3 792 + - toradex,colibri-imx7d-aster # Aster Carrier Board 793 + - toradex,colibri-imx7d-eval-v3 # Colibri Evaluation Board V3 794 + - toradex,colibri-imx7d-iris # Iris Carrier Board 795 + - toradex,colibri-imx7d-iris-v2 # Iris Carrier Board V2 797 796 - const: toradex,colibri-imx7d 798 797 - const: fsl,imx7d 799 798 ··· 804 799 - enum: 805 800 - toradex,colibri-imx7d-emmc-aster # Module on Aster Carrier Board 806 801 - toradex,colibri-imx7d-emmc-eval-v3 # Module on Colibri Evaluation Board V3 802 + - toradex,colibri-imx7d-emmc-iris # Module on Iris Carrier Board 803 + - toradex,colibri-imx7d-emmc-iris-v2 # Module on Iris Carrier Board V2 807 804 - const: toradex,colibri-imx7d-emmc 808 805 - const: fsl,imx7d 809 806 ··· 872 865 - const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module 873 866 - const: fsl,imx8mm 874 867 868 + - description: PHYTEC phyCORE-i.MX8MM SoM based boards 869 + items: 870 + - const: phytec,imx8mm-phyboard-polis-rdk # phyBOARD-Polis RDK 871 + - const: phytec,imx8mm-phycore-som # phyCORE-i.MX8MM SoM 872 + - const: fsl,imx8mm 873 + 875 874 - description: Variscite VAR-SOM-MX8MM based boards 876 875 items: 877 876 - const: variscite,var-som-mx8mm-symphony ··· 927 914 - description: i.MX8MP based Boards 928 915 items: 929 916 - enum: 917 + - dh,imx8mp-dhcom-som # i.MX8MP DHCOM SoM 918 + - dh,imx8mp-dhcom-pdk2 # i.MX8MP DHCOM SoM on PDK2 board 930 919 - fsl,imx8mp-evk # i.MX8MP EVK Board 931 920 - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board 932 921 - toradex,verdin-imx8mp # Verdin iMX8M Plus Modules ··· 965 950 - toradex,verdin-imx8mp-wifi-dev # Verdin iMX8M Plus Wi-Fi / BT M. on Verdin Development B. 966 951 - const: toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Module 967 952 - const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module 953 + - const: fsl,imx8mp 954 + 955 + - description: 956 + TQMa8MPxL is a series of LGA SOM featuring NXP i.MX8MP system-on-chip 957 + variants. It is designed to be soldered on different carrier boards. 958 + All CPU variants use the same device tree hence only one compatible 959 + is needed. MBa8MPxL mainboard can be used as starterkit or in a boxed 960 + version as an industrial computing device. 961 + items: 962 + - enum: 963 + - tq,imx8mp-tqma8mpql-mba8mpxl # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM on MBa8MPxL 964 + - const: tq,imx8mp-tqma8mpql # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM 968 965 - const: fsl,imx8mp 969 966 970 967 - description: i.MX8MQ based Boards ··· 1046 1019 - enum: 1047 1020 - fsl,imx8ulp-evk # i.MX8ULP EVK Board 1048 1021 - const: fsl,imx8ulp 1022 + 1023 + - description: i.MX93 based Boards 1024 + items: 1025 + - enum: 1026 + - fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board 1027 + - const: fsl,imx93 1049 1028 1050 1029 - description: 1051 1030 Freescale Vybrid Platform Device Tree Bindings
+43
Documentation/devicetree/bindings/clock/fsl,scu-clk.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/fsl,scu-clk.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: i.MX SCU Client Device Node - Clock bindings based on SCU Message Protocol 8 + 9 + maintainers: 10 + - Abel Vesa <abel.vesa@nxp.com> 11 + 12 + description: i.MX SCU Client Device Node 13 + Client nodes are maintained as children of the relevant IMX-SCU device node. 14 + This binding uses the common clock binding. 15 + (Documentation/devicetree/bindings/clock/clock-bindings.txt) 16 + The clock consumer should specify the desired clock by having the clock 17 + ID in its "clocks" phandle cell. See the full list of clock IDs from 18 + include/dt-bindings/clock/imx8qxp-clock.h 19 + 20 + properties: 21 + compatible: 22 + items: 23 + - enum: 24 + - fsl,imx8dxl-clk 25 + - fsl,imx8qm-clk 26 + - fsl,imx8qxp-clk 27 + - const: fsl,scu-clk 28 + 29 + '#clock-cells': 30 + const: 2 31 + 32 + required: 33 + - compatible 34 + - '#clock-cells' 35 + 36 + additionalProperties: false 37 + 38 + examples: 39 + - | 40 + clock-controller { 41 + compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; 42 + #clock-cells = <2>; 43 + };
+210
Documentation/devicetree/bindings/firmware/fsl,scu.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/firmware/fsl,scu.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: NXP i.MX System Controller Firmware (SCFW) 8 + 9 + maintainers: 10 + - Dong Aisheng <aisheng.dong@nxp.com> 11 + 12 + description: 13 + The System Controller Firmware (SCFW) is a low-level system function 14 + which runs on a dedicated Cortex-M core to provide power, clock, and 15 + resource management. It exists on some i.MX8 processors. e.g. i.MX8QM 16 + (QM, QP), and i.MX8QX (QXP, DX). 17 + The AP communicates with the SC using a multi-ported MU module found 18 + in the LSIO subsystem. The current definition of this MU module provides 19 + 5 remote AP connections to the SC to support up to 5 execution environments 20 + (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces 21 + with the LSIO DSC IP bus. The SC firmware will communicate with this MU 22 + using the MSI bus. 23 + 24 + properties: 25 + compatible: 26 + const: fsl,imx-scu 27 + 28 + clock-controller: 29 + description: 30 + Clock controller node that provides the clocks controlled by the SCU 31 + $ref: /schemas/clock/fsl,scu-clk.yaml 32 + 33 + ocotp: 34 + description: 35 + OCOTP controller node provided by the SCU 36 + $ref: /schemas/nvmem/fsl,scu-ocotp.yaml 37 + 38 + keys: 39 + description: 40 + Keys provided by the SCU 41 + $ref: /schemas/input/fsl,scu-key.yaml 42 + 43 + mboxes: 44 + description: 45 + A list of phandles of TX MU channels followed by a list of phandles of 46 + RX MU channels. The list may include at the end one more optional MU 47 + channel for general interrupt. The number of expected tx and rx 48 + channels is 1 TX and 1 RX channels if MU instance is "fsl,imx8-mu-scu" 49 + compatible, 4 TX and 4 RX channels otherwise. All MU channels must be 50 + within the same MU instance. Cross instances are not allowed. The MU 51 + instance can only be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users 52 + need to ensure that one is used that does not conflict with other 53 + execution environments such as ATF. 54 + oneOf: 55 + - items: 56 + - description: TX0 MU channel 57 + - description: RX0 MU channel 58 + - items: 59 + - description: TX0 MU channel 60 + - description: RX0 MU channel 61 + - description: optional MU channel for general interrupt 62 + - items: 63 + - description: TX0 MU channel 64 + - description: TX1 MU channel 65 + - description: TX2 MU channel 66 + - description: TX3 MU channel 67 + - description: RX0 MU channel 68 + - description: RX1 MU channel 69 + - description: RX2 MU channel 70 + - description: RX3 MU channel 71 + - items: 72 + - description: TX0 MU channel 73 + - description: TX1 MU channel 74 + - description: TX2 MU channel 75 + - description: TX3 MU channel 76 + - description: RX0 MU channel 77 + - description: RX1 MU channel 78 + - description: RX2 MU channel 79 + - description: RX3 MU channel 80 + - description: optional MU channel for general interrupt 81 + 82 + mbox-names: 83 + oneOf: 84 + - items: 85 + - const: tx0 86 + - const: rx0 87 + - items: 88 + - const: tx0 89 + - const: rx0 90 + - const: gip3 91 + - items: 92 + - const: tx0 93 + - const: tx1 94 + - const: tx2 95 + - const: tx3 96 + - const: rx0 97 + - const: rx1 98 + - const: rx2 99 + - const: rx3 100 + - items: 101 + - const: tx0 102 + - const: tx1 103 + - const: tx2 104 + - const: tx3 105 + - const: rx0 106 + - const: rx1 107 + - const: rx2 108 + - const: rx3 109 + - const: gip3 110 + 111 + pinctrl: 112 + description: 113 + Pin controller provided by the SCU 114 + $ref: /schemas/pinctrl/fsl,scu-pinctrl.yaml 115 + 116 + power-controller: 117 + description: 118 + Power domains controller node that provides the power domains 119 + controlled by the SCU 120 + $ref: /schemas/power/fsl,scu-pd.yaml 121 + 122 + rtc: 123 + description: 124 + RTC controller provided by the SCU 125 + $ref: /schemas/rtc/fsl,scu-rtc.yaml 126 + 127 + thermal-sensor: 128 + description: 129 + Thermal sensor provided by the SCU 130 + $ref: /schemas/thermal/fsl,scu-thermal.yaml 131 + 132 + watchdog: 133 + description: 134 + Watchdog controller provided by the SCU 135 + $ref: /schemas/watchdog/fsl,scu-wdt.yaml 136 + 137 + required: 138 + - compatible 139 + - mbox-names 140 + - mboxes 141 + 142 + additionalProperties: false 143 + 144 + examples: 145 + - | 146 + #include <dt-bindings/firmware/imx/rsrc.h> 147 + #include <dt-bindings/input/input.h> 148 + #include <dt-bindings/pinctrl/pads-imx8qxp.h> 149 + 150 + firmware { 151 + system-controller { 152 + compatible = "fsl,imx-scu"; 153 + mbox-names = "tx0", "tx1", "tx2", "tx3", 154 + "rx0", "rx1", "rx2", "rx3", 155 + "gip3"; 156 + mboxes = <&lsio_mu1 0 0 &lsio_mu1 0 1 &lsio_mu1 0 2 &lsio_mu1 0 3 157 + &lsio_mu1 1 0 &lsio_mu1 1 1 &lsio_mu1 1 2 &lsio_mu1 1 3 158 + &lsio_mu1 3 3>; 159 + 160 + clock-controller { 161 + compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; 162 + #clock-cells = <2>; 163 + }; 164 + 165 + pinctrl { 166 + compatible = "fsl,imx8qxp-iomuxc"; 167 + 168 + pinctrl_lpuart0: lpuart0grp { 169 + fsl,pins = < 170 + IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 171 + IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 172 + >; 173 + }; 174 + }; 175 + 176 + ocotp { 177 + compatible = "fsl,imx8qxp-scu-ocotp"; 178 + #address-cells = <1>; 179 + #size-cells = <1>; 180 + 181 + fec_mac0: mac@2c4 { 182 + reg = <0x2c4 6>; 183 + }; 184 + }; 185 + 186 + power-controller { 187 + compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; 188 + #power-domain-cells = <1>; 189 + }; 190 + 191 + rtc { 192 + compatible = "fsl,imx8qxp-sc-rtc"; 193 + }; 194 + 195 + keys { 196 + compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; 197 + linux,keycodes = <KEY_POWER>; 198 + }; 199 + 200 + watchdog { 201 + compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; 202 + timeout-sec = <60>; 203 + }; 204 + 205 + thermal-sensor { 206 + compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; 207 + #thermal-sensor-cells = <1>; 208 + }; 209 + }; 210 + };
+40
Documentation/devicetree/bindings/input/fsl,scu-key.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/input/fsl,scu-key.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: i.MX SCU Client Device Node - SCU key bindings based on SCU Message Protocol 8 + 9 + maintainers: 10 + - Dong Aisheng <aisheng.dong@nxp.com> 11 + 12 + description: i.MX SCU Client Device Node 13 + Client nodes are maintained as children of the relevant IMX-SCU device node. 14 + 15 + allOf: 16 + - $ref: input.yaml# 17 + 18 + properties: 19 + compatible: 20 + items: 21 + - const: fsl,imx8qxp-sc-key 22 + - const: fsl,imx-sc-key 23 + 24 + linux,keycodes: 25 + maxItems: 1 26 + 27 + required: 28 + - compatible 29 + - linux,keycodes 30 + 31 + additionalProperties: false 32 + 33 + examples: 34 + - | 35 + #include <dt-bindings/input/input.h> 36 + 37 + keys { 38 + compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; 39 + linux,keycodes = <KEY_POWER>; 40 + };
+56
Documentation/devicetree/bindings/nvmem/fsl,scu-ocotp.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/nvmem/fsl,scu-ocotp.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: i.MX SCU Client Device Node - OCOTP bindings based on SCU Message Protocol 8 + 9 + maintainers: 10 + - Dong Aisheng <aisheng.dong@nxp.com> 11 + 12 + description: i.MX SCU Client Device Node 13 + Client nodes are maintained as children of the relevant IMX-SCU device node. 14 + 15 + allOf: 16 + - $ref: nvmem.yaml# 17 + 18 + properties: 19 + compatible: 20 + enum: 21 + - fsl,imx8qm-scu-ocotp 22 + - fsl,imx8qxp-scu-ocotp 23 + 24 + patternProperties: 25 + '^mac@[0-9a-f]*$': 26 + type: object 27 + description: 28 + MAC address. 29 + 30 + properties: 31 + reg: 32 + description: 33 + Byte offset within OCOTP where the MAC address is stored 34 + maxItems: 1 35 + 36 + required: 37 + - reg 38 + 39 + additionalProperties: false 40 + 41 + required: 42 + - compatible 43 + 44 + unevaluatedProperties: false 45 + 46 + examples: 47 + - | 48 + ocotp { 49 + compatible = "fsl,imx8qxp-scu-ocotp"; 50 + #address-cells = <1>; 51 + #size-cells = <1>; 52 + 53 + fec_mac0: mac@2c4 { 54 + reg = <0x2c4 6>; 55 + }; 56 + };
+74
Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/pinctrl/fsl,scu-pinctrl.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: i.MX SCU Client Device Node - Pinctrl bindings based on SCU Message Protocol 8 + 9 + maintainers: 10 + - Dong Aisheng <aisheng.dong@nxp.com> 11 + 12 + description: i.MX SCU Client Device Node 13 + Client nodes are maintained as children of the relevant IMX-SCU device node. 14 + This binding uses the i.MX common pinctrl binding. 15 + (Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt) 16 + 17 + allOf: 18 + - $ref: pinctrl.yaml# 19 + 20 + properties: 21 + compatible: 22 + enum: 23 + - fsl,imx8qm-iomuxc 24 + - fsl,imx8qxp-iomuxc 25 + - fsl,imx8dxl-iomuxc 26 + 27 + patternProperties: 28 + 'grp$': 29 + type: object 30 + description: 31 + Pinctrl node's client devices use subnodes for desired pin configuration. 32 + Client device subnodes use below standard properties. 33 + 34 + properties: 35 + fsl,pins: 36 + description: 37 + each entry consists of 3 integers and represents the pin ID, the mux value 38 + and pad setting for the pin. The first 2 integers - pin_id and mux_val - are 39 + specified using a PIN_FUNC_ID macro, which can be found in 40 + <include/dt-bindings/pinctrl/pads-imx8qxp.h>. The last integer is 41 + the pad setting value like pull-up on this pin. Please refer to the 42 + appropriate i.MX8 Reference Manual for detailed pad CONFIG settings. 43 + $ref: /schemas/types.yaml#/definitions/uint32-matrix 44 + items: 45 + items: 46 + - description: | 47 + "pin_id" indicates the pin ID 48 + - description: | 49 + "mux_val" indicates the mux value to be applied. 50 + - description: | 51 + "pad_setting" indicates the pad configuration value to be applied. 52 + 53 + required: 54 + - fsl,pins 55 + 56 + additionalProperties: false 57 + 58 + required: 59 + - compatible 60 + 61 + additionalProperties: false 62 + 63 + examples: 64 + - | 65 + pinctrl { 66 + compatible = "fsl,imx8qxp-iomuxc"; 67 + 68 + pinctrl_lpuart0: lpuart0grp { 69 + fsl,pins = < 70 + 111 0 0x06000020 71 + 112 0 0x06000020 72 + >; 73 + }; 74 + };
+41
Documentation/devicetree/bindings/power/fsl,scu-pd.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/power/fsl,scu-pd.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: i.MX SCU Client Device Node - Power domain bindings based on SCU Message Protocol 8 + 9 + maintainers: 10 + - Dong Aisheng <aisheng.dong@nxp.com> 11 + 12 + description: i.MX SCU Client Device Node 13 + Client nodes are maintained as children of the relevant IMX-SCU device node. 14 + Power domain bindings based on SCU Message Protocol 15 + 16 + allOf: 17 + - $ref: power-domain.yaml# 18 + 19 + properties: 20 + compatible: 21 + items: 22 + - enum: 23 + - fsl,imx8qm-scu-pd 24 + - fsl,imx8qxp-scu-pd 25 + - const: fsl,scu-pd 26 + 27 + '#power-domain-cells': 28 + const: 1 29 + 30 + required: 31 + - compatible 32 + - '#power-domain-cells' 33 + 34 + additionalProperties: false 35 + 36 + examples: 37 + - | 38 + power-controller { 39 + compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; 40 + #power-domain-cells = <1>; 41 + };
+31
Documentation/devicetree/bindings/rtc/fsl,scu-rtc.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/rtc/fsl,scu-rtc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: i.MX SCU Client Device Node - RTC bindings based on SCU Message Protocol 8 + 9 + maintainers: 10 + - Dong Aisheng <aisheng.dong@nxp.com> 11 + 12 + description: i.MX SCU Client Device Node 13 + Client nodes are maintained as children of the relevant IMX-SCU device node. 14 + 15 + allOf: 16 + - $ref: rtc.yaml# 17 + 18 + properties: 19 + compatible: 20 + const: fsl,imx8qxp-sc-rtc 21 + 22 + required: 23 + - compatible 24 + 25 + additionalProperties: false 26 + 27 + examples: 28 + - | 29 + rtc { 30 + compatible = "fsl,imx8qxp-sc-rtc"; 31 + };
+38
Documentation/devicetree/bindings/thermal/fsl,scu-thermal.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/thermal/fsl,scu-thermal.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: i.MX SCU Client Device Node - Thermal bindings based on SCU Message Protocol 8 + 9 + maintainers: 10 + - Dong Aisheng <aisheng.dong@nxp.com> 11 + 12 + description: i.MX SCU Client Device Node 13 + Client nodes are maintained as children of the relevant IMX-SCU device node. 14 + 15 + allOf: 16 + - $ref: thermal-sensor.yaml# 17 + 18 + properties: 19 + compatible: 20 + items: 21 + - const: fsl,imx8qxp-sc-thermal 22 + - const: fsl,imx-sc-thermal 23 + 24 + '#thermal-sensor-cells': 25 + const: 1 26 + 27 + required: 28 + - compatible 29 + - '#thermal-sensor-cells' 30 + 31 + additionalProperties: false 32 + 33 + examples: 34 + - | 35 + thermal-sensor { 36 + compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; 37 + #thermal-sensor-cells = <1>; 38 + };
+34
Documentation/devicetree/bindings/watchdog/fsl,scu-wdt.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/watchdog/fsl,scu-wdt.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: i.MX SCU Client Device Node - Watchdog bindings based on SCU Message Protocol 8 + 9 + maintainers: 10 + - Dong Aisheng <aisheng.dong@nxp.com> 11 + 12 + description: i.MX SCU Client Device Node 13 + Client nodes are maintained as children of the relevant IMX-SCU device node. 14 + 15 + allOf: 16 + - $ref: watchdog.yaml# 17 + 18 + properties: 19 + compatible: 20 + items: 21 + - const: fsl,imx8qxp-sc-wdt 22 + - const: fsl,imx-sc-wdt 23 + 24 + required: 25 + - compatible 26 + 27 + unevaluatedProperties: false 28 + 29 + examples: 30 + - | 31 + watchdog { 32 + compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; 33 + timeout-sec = <60>; 34 + };