Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/amd/pm: export a function amdgpu_smu_ras_send_msg to allow send msg directly

provide a interface that allows ras client send msg to smu/pmfw directly.

Signed-off-by: Yang Wang <kevinyang.wang@amd.com>
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

YiPeng Chai and committed by
Alex Deucher
80e462c5 2b5b3f9b

+41
+11
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
··· 612 612 return true; 613 613 } 614 614 615 + int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type msg, 616 + uint32_t param, uint32_t *read_arg) 617 + { 618 + struct smu_context *smu = adev->powerplay.pp_handle; 619 + int ret = -EOPNOTSUPP; 620 + 621 + if (smu->ppt_funcs && smu->ppt_funcs->ras_send_msg) 622 + ret = smu->ppt_funcs->ras_send_msg(smu, msg, param, read_arg); 623 + 624 + return ret; 625 + } 615 626 616 627 static int smu_sys_get_pp_table(void *handle, 617 628 char **table)
+11
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
··· 1522 1522 */ 1523 1523 ssize_t (*get_xcp_metrics)(struct smu_context *smu, int xcp_id, 1524 1524 void *table); 1525 + /** 1526 + * @ras_send_msg: Send a message with a parameter from Ras 1527 + * &msg: Type of message. 1528 + * &param: Message parameter. 1529 + * &read_arg: SMU response (optional). 1530 + */ 1531 + int (*ras_send_msg)(struct smu_context *smu, 1532 + enum smu_message_type msg, uint32_t param, uint32_t *read_arg); 1533 + 1525 1534 }; 1526 1535 1527 1536 typedef enum { ··· 1796 1787 ssize_t smu_get_pm_policy_info(struct smu_context *smu, 1797 1788 enum pp_pm_policy p_type, char *sysbuf); 1798 1789 1790 + int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type msg, 1791 + uint32_t param, uint32_t *readarg); 1799 1792 #endif 1800 1793 1801 1794 void smu_feature_cap_set(struct smu_context *smu, enum smu_feature_cap_id fea_id);
+19
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
··· 3226 3226 return ret; 3227 3227 } 3228 3228 3229 + static int smu_v13_0_6_ras_send_msg(struct smu_context *smu, enum smu_message_type msg, uint32_t param, uint32_t *read_arg) 3230 + { 3231 + int ret; 3232 + 3233 + switch (msg) { 3234 + case SMU_MSG_QueryValidMcaCount: 3235 + case SMU_MSG_QueryValidMcaCeCount: 3236 + case SMU_MSG_McaBankDumpDW: 3237 + case SMU_MSG_McaBankCeDumpDW: 3238 + case SMU_MSG_ClearMcaOnRead: 3239 + ret = smu_cmn_send_smc_msg_with_param(smu, msg, param, read_arg); 3240 + break; 3241 + default: 3242 + ret = -EPERM; 3243 + } 3244 + 3245 + return ret; 3246 + } 3229 3247 3230 3248 static int smu_v13_0_6_post_init(struct smu_context *smu) 3231 3249 { ··· 3939 3921 .reset_sdma = smu_v13_0_6_reset_sdma, 3940 3922 .dpm_reset_vcn = smu_v13_0_6_reset_vcn, 3941 3923 .post_init = smu_v13_0_6_post_init, 3924 + .ras_send_msg = smu_v13_0_6_ras_send_msg, 3942 3925 }; 3943 3926 3944 3927 void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu)