Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

remoteproc: mediatek: Support mt8186 scp

Add SCP support for mt8186

Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220225132747.31808-3-allen-kh.cheng@mediatek.com

authored by

Allen-KH Cheng and committed by
Bjorn Andersson
80d69185 22335385

+38
+3
drivers/remoteproc/mtk_common.h
··· 32 32 #define MT8183_SCP_CACHESIZE_8KB BIT(8) 33 33 #define MT8183_SCP_CACHE_CON_WAYEN BIT(10) 34 34 35 + #define MT8186_SCP_L1_SRAM_PD_P1 0x40B0 36 + #define MT8186_SCP_L1_SRAM_PD_p2 0x40B4 37 + 35 38 #define MT8192_L2TCM_SRAM_PD_0 0x10C0 36 39 #define MT8192_L2TCM_SRAM_PD_1 0x10C4 37 40 #define MT8192_L2TCM_SRAM_PD_2 0x10C8
+35
drivers/remoteproc/mtk_scp.c
··· 383 383 writel(GENMASK(i, 0), addr); 384 384 } 385 385 386 + static int mt8186_scp_before_load(struct mtk_scp *scp) 387 + { 388 + /* Clear SCP to host interrupt */ 389 + writel(MT8183_SCP_IPC_INT_BIT, scp->reg_base + MT8183_SCP_TO_HOST); 390 + 391 + /* Reset clocks before loading FW */ 392 + writel(0x0, scp->reg_base + MT8183_SCP_CLK_SW_SEL); 393 + writel(0x0, scp->reg_base + MT8183_SCP_CLK_DIV_SEL); 394 + 395 + /* Turn on the power of SCP's SRAM before using it. Enable 1 block per time*/ 396 + mt8192_power_on_sram(scp->reg_base + MT8183_SCP_SRAM_PDN); 397 + 398 + /* Initialize TCM before loading FW. */ 399 + writel(0x0, scp->reg_base + MT8183_SCP_L1_SRAM_PD); 400 + writel(0x0, scp->reg_base + MT8183_SCP_TCM_TAIL_SRAM_PD); 401 + writel(0x0, scp->reg_base + MT8186_SCP_L1_SRAM_PD_P1); 402 + writel(0x0, scp->reg_base + MT8186_SCP_L1_SRAM_PD_p2); 403 + 404 + return 0; 405 + } 406 + 386 407 static int mt8192_scp_before_load(struct mtk_scp *scp) 387 408 { 388 409 /* clear SPM interrupt, SCP2SPM_IPC_CLR */ ··· 895 874 .ipi_buf_offset = 0x7bdb0, 896 875 }; 897 876 877 + static const struct mtk_scp_of_data mt8186_of_data = { 878 + .scp_clk_get = mt8195_scp_clk_get, 879 + .scp_before_load = mt8186_scp_before_load, 880 + .scp_irq_handler = mt8183_scp_irq_handler, 881 + .scp_reset_assert = mt8183_scp_reset_assert, 882 + .scp_reset_deassert = mt8183_scp_reset_deassert, 883 + .scp_stop = mt8183_scp_stop, 884 + .scp_da_to_va = mt8183_scp_da_to_va, 885 + .host_to_scp_reg = MT8183_HOST_TO_SCP, 886 + .host_to_scp_int_bit = MT8183_HOST_IPC_INT_BIT, 887 + .ipi_buf_offset = 0x7bdb0, 888 + }; 889 + 898 890 static const struct mtk_scp_of_data mt8192_of_data = { 899 891 .scp_clk_get = mt8192_scp_clk_get, 900 892 .scp_before_load = mt8192_scp_before_load, ··· 934 900 935 901 static const struct of_device_id mtk_scp_of_match[] = { 936 902 { .compatible = "mediatek,mt8183-scp", .data = &mt8183_of_data }, 903 + { .compatible = "mediatek,mt8186-scp", .data = &mt8186_of_data }, 937 904 { .compatible = "mediatek,mt8192-scp", .data = &mt8192_of_data }, 938 905 { .compatible = "mediatek,mt8195-scp", .data = &mt8195_of_data }, 939 906 {},