tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'bnxt_en-fix-queue-reset-when-queue-active'

David Wei says:

====================
fix bnxt_en queue reset when queue is active

The current bnxt_en queue API implementation is buggy when resetting a
queue that has active traffic. The problem is that there is no FW
involved to stop the flow of packets and relying on napi_disable() isn't
enough.

To fix this, call bnxt_hwrm_vnic_update() with MRU set to 0 for both the
default and the ntuple vnic to stop the flow of packets. This works for
any Rx queue and not only those that have ntuple rules since every Rx
queue is either in the default or the ntuple vnic.

For bnxt_hwrm_vnic_update() to work, proper flushing must be done by the
FW. A FW flag is there to indicate support and queue_mgmt_ops is keyed
behind this.

The first three patches are from Michael Chan and adds the prerequisite
vnic functions and FW flags indicating that it will properly flush
during vnic update.

Tested on BCM957504 while iperf3 is active:

1. Reset a queue that has an ntuple rule steering flow into it
2. Reset all queues in order, one at a time

In both cases the flow is not interrupted.

Sending this to net-next as there is no in-tree kernel consumer of queue
API just yet, and there is a patch that changes when the queue_mgmt_ops
is registered.

Reviewed-by: Wojciech Drewek <wojciech.drewek@intel.com>
---
v3:
- include patches from Michael Chan that adds a FW flag for vnic flush
capability
- key support for queue_mgmt_ops behind this new flag

v2:
- split setting vnic->mru into a separate patch (Wojciech)
- clarify why napi_enable()/disable() is removed
====================

Signed-off-by: David S. Miller <davem@davemloft.net>

David S. Miller 80d021bc 969afb43

+300 -146
+44 -6
drivers/net/ethernet/broadcom/bnxt/bnxt.c
··· 6579 6579 req->dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id); 6580 6580 req->lb_rule = cpu_to_le16(0xffff); 6581 6581 vnic_mru: 6582 - req->mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + VLAN_HLEN); 6582 + vnic->mru = bp->dev->mtu + ETH_HLEN + VLAN_HLEN; 6583 + req->mru = cpu_to_le16(vnic->mru); 6583 6584 6584 6585 req->vnic_id = cpu_to_le16(vnic->fw_vnic_id); 6585 6586 #ifdef CONFIG_BNXT_SRIOV ··· 6716 6715 bp->rss_cap |= BNXT_RSS_CAP_ESP_V4_RSS_CAP; 6717 6716 if (flags & VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV6_CAP) 6718 6717 bp->rss_cap |= BNXT_RSS_CAP_ESP_V6_RSS_CAP; 6718 + if (flags & VNIC_QCAPS_RESP_FLAGS_RE_FLUSH_CAP) 6719 + bp->fw_cap |= BNXT_FW_CAP_VNIC_RE_FLUSH; 6719 6720 } 6720 6721 hwrm_req_drop(bp, req); 6721 6722 return rc; ··· 10090 10087 10091 10088 vnic_setup_err: 10092 10089 return rc; 10090 + } 10091 + 10092 + int bnxt_hwrm_vnic_update(struct bnxt *bp, struct bnxt_vnic_info *vnic, 10093 + u8 valid) 10094 + { 10095 + struct hwrm_vnic_update_input *req; 10096 + int rc; 10097 + 10098 + rc = hwrm_req_init(bp, req, HWRM_VNIC_UPDATE); 10099 + if (rc) 10100 + return rc; 10101 + 10102 + req->vnic_id = cpu_to_le32(vnic->fw_vnic_id); 10103 + 10104 + if (valid & VNIC_UPDATE_REQ_ENABLES_MRU_VALID) 10105 + req->mru = cpu_to_le16(vnic->mru); 10106 + 10107 + req->enables = cpu_to_le32(valid); 10108 + 10109 + return hwrm_req_send(bp, req); 10093 10110 } 10094 10111 10095 10112 int bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic) ··· 15177 15154 struct bnxt *bp = netdev_priv(dev); 15178 15155 struct bnxt_rx_ring_info *rxr, *clone; 15179 15156 struct bnxt_cp_ring_info *cpr; 15180 - int rc; 15157 + struct bnxt_vnic_info *vnic; 15158 + int i, rc; 15181 15159 15182 15160 rxr = &bp->rx_ring[idx]; 15183 15161 clone = qmem; ··· 15203 15179 if (bp->flags & BNXT_FLAG_AGG_RINGS) 15204 15180 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod); 15205 15181 15206 - napi_enable(&rxr->bnapi->napi); 15207 - 15208 15182 cpr = &rxr->bnapi->cp_ring; 15209 15183 cpr->sw_stats->rx.rx_resets++; 15184 + 15185 + for (i = 0; i <= BNXT_VNIC_NTUPLE; i++) { 15186 + vnic = &bp->vnic_info[i]; 15187 + vnic->mru = bp->dev->mtu + ETH_HLEN + VLAN_HLEN; 15188 + bnxt_hwrm_vnic_update(bp, vnic, 15189 + VNIC_UPDATE_REQ_ENABLES_MRU_VALID); 15190 + } 15210 15191 15211 15192 return 0; 15212 15193 ··· 15224 15195 { 15225 15196 struct bnxt *bp = netdev_priv(dev); 15226 15197 struct bnxt_rx_ring_info *rxr; 15198 + struct bnxt_vnic_info *vnic; 15199 + int i; 15200 + 15201 + for (i = 0; i <= BNXT_VNIC_NTUPLE; i++) { 15202 + vnic = &bp->vnic_info[i]; 15203 + vnic->mru = 0; 15204 + bnxt_hwrm_vnic_update(bp, vnic, 15205 + VNIC_UPDATE_REQ_ENABLES_MRU_VALID); 15206 + } 15227 15207 15228 15208 rxr = &bp->rx_ring[idx]; 15229 - napi_disable(&rxr->bnapi->napi); 15230 15209 bnxt_hwrm_rx_ring_free(bp, rxr, false); 15231 15210 bnxt_hwrm_rx_agg_ring_free(bp, rxr, false); 15232 15211 rxr->rx_next_cons = 0; ··· 15718 15681 dev->stat_ops = &bnxt_stat_ops; 15719 15682 dev->watchdog_timeo = BNXT_TX_TIMEOUT; 15720 15683 dev->ethtool_ops = &bnxt_ethtool_ops; 15721 - dev->queue_mgmt_ops = &bnxt_queue_mgmt_ops; 15722 15684 pci_set_drvdata(pdev, dev); 15723 15685 15724 15686 rc = bnxt_alloc_hwrm_resources(bp); ··· 15898 15862 15899 15863 if (BNXT_SUPPORTS_NTUPLE_VNIC(bp)) 15900 15864 bp->rss_cap |= BNXT_RSS_CAP_MULTI_RSS_CTX; 15865 + if (BNXT_SUPPORTS_QUEUE_API(bp)) 15866 + dev->queue_mgmt_ops = &bnxt_queue_mgmt_ops; 15901 15867 15902 15868 rc = register_netdev(dev); 15903 15869 if (rc)
+7
drivers/net/ethernet/broadcom/bnxt/bnxt.h
··· 1250 1250 #define BNXT_MAX_CTX_PER_VNIC 8 1251 1251 u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC]; 1252 1252 u16 fw_l2_ctx_id; 1253 + u16 mru; 1253 1254 #define BNXT_MAX_UC_ADDRS 4 1254 1255 struct bnxt_l2_filter *l2_filters[BNXT_MAX_UC_ADDRS]; 1255 1256 /* index 0 always dev_addr */ ··· 2438 2437 #define BNXT_FW_CAP_VNIC_TUNNEL_TPA BIT_ULL(37) 2439 2438 #define BNXT_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO BIT_ULL(38) 2440 2439 #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V3 BIT_ULL(39) 2440 + #define BNXT_FW_CAP_VNIC_RE_FLUSH BIT_ULL(40) 2441 2441 2442 2442 u32 fw_dbg_cap; 2443 2443 ··· 2451 2449 #define BNXT_SUPPORTS_MULTI_RSS_CTX(bp) \ 2452 2450 (BNXT_PF(bp) && BNXT_SUPPORTS_NTUPLE_VNIC(bp) && \ 2453 2451 ((bp)->rss_cap & BNXT_RSS_CAP_MULTI_RSS_CTX)) 2452 + #define BNXT_SUPPORTS_QUEUE_API(bp) \ 2453 + (BNXT_PF(bp) && BNXT_SUPPORTS_NTUPLE_VNIC(bp) && \ 2454 + ((bp)->fw_cap & BNXT_FW_CAP_VNIC_RE_FLUSH)) 2454 2455 2455 2456 u32 hwrm_spec_code; 2456 2457 u16 hwrm_cmd_seq; ··· 2843 2838 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all); 2844 2839 int bnxt_hwrm_func_qcaps(struct bnxt *bp); 2845 2840 int bnxt_hwrm_fw_set_time(struct bnxt *); 2841 + int bnxt_hwrm_vnic_update(struct bnxt *bp, struct bnxt_vnic_info *vnic, 2842 + u8 valid); 2846 2843 int bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic); 2847 2844 int __bnxt_setup_vnic_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic); 2848 2845 void bnxt_del_one_rss_ctx(struct bnxt *bp, struct bnxt_rss_ctx *rss_ctx,
+249 -140
drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h
··· 403 403 #define HWRM_FUNC_LAG_UPDATE 0x1b1UL 404 404 #define HWRM_FUNC_LAG_FREE 0x1b2UL 405 405 #define HWRM_FUNC_LAG_QCFG 0x1b3UL 406 + #define HWRM_FUNC_TIMEDTX_PACING_RATE_ADD 0x1c2UL 407 + #define HWRM_FUNC_TIMEDTX_PACING_RATE_DELETE 0x1c3UL 408 + #define HWRM_FUNC_TIMEDTX_PACING_RATE_QUERY 0x1c4UL 406 409 #define HWRM_SELFTEST_QLIST 0x200UL 407 410 #define HWRM_SELFTEST_EXEC 0x201UL 408 411 #define HWRM_SELFTEST_IRQ 0x202UL ··· 433 430 #define HWRM_STAT_GENERIC_QSTATS 0x218UL 434 431 #define HWRM_MFG_PRVSN_EXPORT_CERT 0x219UL 435 432 #define HWRM_STAT_DB_ERROR_QSTATS 0x21aUL 433 + #define HWRM_MFG_TESTS 0x21bUL 434 + #define HWRM_PORT_POE_CFG 0x230UL 435 + #define HWRM_PORT_POE_QCFG 0x231UL 436 436 #define HWRM_UDCC_QCAPS 0x258UL 437 437 #define HWRM_UDCC_CFG 0x259UL 438 438 #define HWRM_UDCC_QCFG 0x25aUL ··· 445 439 #define HWRM_UDCC_COMP_CFG 0x25eUL 446 440 #define HWRM_UDCC_COMP_QCFG 0x25fUL 447 441 #define HWRM_UDCC_COMP_QUERY 0x260UL 442 + #define HWRM_QUEUE_PFCWD_TIMEOUT_QCAPS 0x261UL 443 + #define HWRM_QUEUE_PFCWD_TIMEOUT_CFG 0x262UL 444 + #define HWRM_QUEUE_PFCWD_TIMEOUT_QCFG 0x263UL 448 445 #define HWRM_TF 0x2bcUL 449 446 #define HWRM_TF_VERSION_GET 0x2bdUL 450 447 #define HWRM_TF_SESSION_OPEN 0x2c6UL ··· 509 500 #define HWRM_TFC_IF_TBL_GET 0x399UL 510 501 #define HWRM_TFC_TBL_SCOPE_CONFIG_GET 0x39aUL 511 502 #define HWRM_TFC_RESC_USAGE_QUERY 0x39bUL 512 - #define HWRM_QUEUE_PFCWD_TIMEOUT_QCAPS 0x39cUL 513 - #define HWRM_QUEUE_PFCWD_TIMEOUT_CFG 0x39dUL 514 - #define HWRM_QUEUE_PFCWD_TIMEOUT_QCFG 0x39eUL 515 503 #define HWRM_SV 0x400UL 504 + #define HWRM_DBG_SERDES_TEST 0xff0eUL 516 505 #define HWRM_DBG_LOG_BUFFER_FLUSH 0xff0fUL 517 506 #define HWRM_DBG_READ_DIRECT 0xff10UL 518 507 #define HWRM_DBG_READ_INDIRECT 0xff11UL ··· 540 533 #define HWRM_DBG_USEQ_RUN 0xff29UL 541 534 #define HWRM_DBG_USEQ_DELIVERY_REQ 0xff2aUL 542 535 #define HWRM_DBG_USEQ_RESP_HDR 0xff2bUL 536 + #define HWRM_DBG_COREDUMP_CAPTURE 0xff2cUL 537 + #define HWRM_DBG_PTRACE 0xff2dUL 538 + #define HWRM_DBG_SIM_CABLE_STATE 0xff2eUL 543 539 #define HWRM_NVM_GET_VPD_FIELD_INFO 0xffeaUL 544 540 #define HWRM_NVM_SET_VPD_FIELD_INFO 0xffebUL 545 541 #define HWRM_NVM_DEFRAG 0xffecUL ··· 592 582 #define HWRM_ERR_CODE_RESOURCE_LOCKED 0x11UL 593 583 #define HWRM_ERR_CODE_PF_UNAVAILABLE 0x12UL 594 584 #define HWRM_ERR_CODE_ENTITY_NOT_PRESENT 0x13UL 585 + #define HWRM_ERR_CODE_SECURE_SOC_ERROR 0x14UL 595 586 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL 596 587 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL 597 588 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL ··· 624 613 #define HWRM_VERSION_MAJOR 1 625 614 #define HWRM_VERSION_MINOR 10 626 615 #define HWRM_VERSION_UPDATE 3 627 - #define HWRM_VERSION_RSVD 44 628 - #define HWRM_VERSION_STR "1.10.3.44" 616 + #define HWRM_VERSION_RSVD 68 617 + #define HWRM_VERSION_STR "1.10.3.68" 629 618 630 619 /* hwrm_ver_get_input (size:192b/24B) */ 631 620 struct hwrm_ver_get_input { ··· 861 850 #define ASYNC_EVENT_CMPL_EVENT_ID_UDCC_SESSION_CHANGE 0x4bUL 862 851 #define ASYNC_EVENT_CMPL_EVENT_ID_DBG_BUF_PRODUCER 0x4cUL 863 852 #define ASYNC_EVENT_CMPL_EVENT_ID_PEER_MMAP_CHANGE 0x4dUL 864 - #define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID 0x4eUL 853 + #define ASYNC_EVENT_CMPL_EVENT_ID_REPRESENTOR_PAIR_CHANGE 0x4eUL 854 + #define ASYNC_EVENT_CMPL_EVENT_ID_VF_STAT_CHANGE 0x4fUL 855 + #define ASYNC_EVENT_CMPL_EVENT_ID_HOST_COREDUMP 0x50UL 856 + #define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID 0x51UL 865 857 #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL 866 858 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 867 859 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR ··· 1705 1691 u8 unused_0[6]; 1706 1692 }; 1707 1693 1708 - /* hwrm_func_qcaps_output (size:1088b/136B) */ 1694 + /* hwrm_func_qcaps_output (size:1152b/144B) */ 1709 1695 struct hwrm_func_qcaps_output { 1710 1696 __le16 error_code; 1711 1697 __le16 req_type; ··· 1838 1824 #define FUNC_QCAPS_RESP_FLAGS_EXT2_TF_EGRESS_NIC_FLOW_SUPPORTED 0x4000000UL 1839 1825 #define FUNC_QCAPS_RESP_FLAGS_EXT2_MULTI_LOSSLESS_QUEUES_SUPPORTED 0x8000000UL 1840 1826 #define FUNC_QCAPS_RESP_FLAGS_EXT2_PEER_MMAP_SUPPORTED 0x10000000UL 1827 + #define FUNC_QCAPS_RESP_FLAGS_EXT2_TIMED_TX_PACING_SUPPORTED 0x20000000UL 1828 + #define FUNC_QCAPS_RESP_FLAGS_EXT2_VF_STAT_EJECTION_SUPPORTED 0x40000000UL 1829 + #define FUNC_QCAPS_RESP_FLAGS_EXT2_HOST_COREDUMP_SUPPORTED 0x80000000UL 1841 1830 __le16 tunnel_disable_flag; 1842 1831 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN 0x1UL 1843 1832 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NGE 0x2UL ··· 1862 1845 __le32 roce_vf_max_qp; 1863 1846 __le32 roce_vf_max_srq; 1864 1847 __le32 roce_vf_max_gid; 1865 - u8 unused_3[3]; 1848 + __le32 flags_ext3; 1849 + #define FUNC_QCAPS_RESP_FLAGS_EXT3_RM_RSV_WHILE_ALLOC_CAP 0x1UL 1850 + u8 unused_3[7]; 1866 1851 u8 valid; 1867 1852 }; 1868 1853 ··· 2040 2021 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2041 2022 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 2042 2023 __le16 host_mtu; 2043 - u8 unused_3[2]; 2024 + __le16 flags2; 2025 + #define FUNC_QCFG_RESP_FLAGS2_SRIOV_DSCP_INSERT_ENABLED 0x1UL 2044 2026 u8 unused_4[2]; 2045 2027 u8 port_kdnet_mode; 2046 2028 #define FUNC_QCFG_RESP_PORT_KDNET_MODE_DISABLED 0x0UL ··· 3691 3671 __le16 target_id; 3692 3672 __le64 resp_addr; 3693 3673 __le16 type; 3694 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QP 0x0UL 3695 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ 0x1UL 3696 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ 0x2UL 3697 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_VNIC 0x3UL 3698 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_STAT 0x4UL 3699 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SP_TQM_RING 0x5UL 3700 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_FP_TQM_RING 0x6UL 3701 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MRAV 0xeUL 3702 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TIM 0xfUL 3703 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TX_CK 0x13UL 3704 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RX_CK 0x14UL 3705 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3706 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL 3707 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL 3708 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL 3709 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL 3710 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TBL_SCOPE 0x1cUL 3711 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_XID_PARTITION 0x1dUL 3712 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRT_TRACE 0x1eUL 3713 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRT2_TRACE 0x1fUL 3714 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CRT_TRACE 0x20UL 3715 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CRT2_TRACE 0x21UL 3716 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RIGP0_TRACE 0x22UL 3717 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_L2_HWRM_TRACE 0x23UL 3718 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_ROCE_HWRM_TRACE 0x24UL 3719 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 0xffffUL 3720 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 3674 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QP 0x0UL 3675 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ 0x1UL 3676 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ 0x2UL 3677 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_VNIC 0x3UL 3678 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_STAT 0x4UL 3679 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SP_TQM_RING 0x5UL 3680 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_FP_TQM_RING 0x6UL 3681 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MRAV 0xeUL 3682 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TIM 0xfUL 3683 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TX_CK 0x13UL 3684 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RX_CK 0x14UL 3685 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3686 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL 3687 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL 3688 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL 3689 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL 3690 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TBL_SCOPE 0x1cUL 3691 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_XID_PARTITION 0x1dUL 3692 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRT_TRACE 0x1eUL 3693 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRT2_TRACE 0x1fUL 3694 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CRT_TRACE 0x20UL 3695 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CRT2_TRACE 0x21UL 3696 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RIGP0_TRACE 0x22UL 3697 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_L2_HWRM_TRACE 0x23UL 3698 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_ROCE_HWRM_TRACE 0x24UL 3699 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TTX_PACING_TQM_RING 0x25UL 3700 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CA0_TRACE 0x26UL 3701 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CA1_TRACE 0x27UL 3702 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CA2_TRACE 0x28UL 3703 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RIGP1_TRACE 0x29UL 3704 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 0xffffUL 3705 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 3721 3706 __le16 instance; 3722 3707 __le32 flags; 3723 3708 #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_PREBOOT_MODE 0x1UL ··· 3797 3772 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RIGP0_TRACE 0x22UL 3798 3773 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_L2_HWRM_TRACE 0x23UL 3799 3774 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_ROCE_HWRM_TRACE 0x24UL 3775 + #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TTX_PACING_TQM_RING 0x25UL 3776 + #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CA0_TRACE 0x26UL 3777 + #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CA1_TRACE 0x27UL 3778 + #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CA2_TRACE 0x28UL 3779 + #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RIGP1_TRACE 0x29UL 3800 3780 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID 0xffffUL 3801 3781 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID 3802 3782 __le16 instance; ··· 3815 3785 __le16 seq_id; 3816 3786 __le16 resp_len; 3817 3787 __le16 type; 3818 - #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QP 0x0UL 3819 - #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRQ 0x1UL 3820 - #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CQ 0x2UL 3821 - #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_VNIC 0x3UL 3822 - #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_STAT 0x4UL 3823 - #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SP_TQM_RING 0x5UL 3824 - #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_FP_TQM_RING 0x6UL 3825 - #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MRAV 0xeUL 3826 - #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TIM 0xfUL 3827 - #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TX_CK 0x13UL 3828 - #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RX_CK 0x14UL 3829 - #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MP_TQM_RING 0x15UL 3830 - #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TBL_SCOPE 0x1cUL 3831 - #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_XID_PARTITION 0x1dUL 3832 - #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRT_TRACE 0x1eUL 3833 - #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRT2_TRACE 0x1fUL 3834 - #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CRT_TRACE 0x20UL 3835 - #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CRT2_TRACE 0x21UL 3836 - #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RIGP0_TRACE 0x22UL 3837 - #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_L2_HWRM_TRACE 0x23UL 3838 - #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_ROCE_HWRM_TRACE 0x24UL 3839 - #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 0xffffUL 3840 - #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 3788 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QP 0x0UL 3789 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRQ 0x1UL 3790 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CQ 0x2UL 3791 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_VNIC 0x3UL 3792 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_STAT 0x4UL 3793 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SP_TQM_RING 0x5UL 3794 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_FP_TQM_RING 0x6UL 3795 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MRAV 0xeUL 3796 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TIM 0xfUL 3797 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TX_CK 0x13UL 3798 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RX_CK 0x14UL 3799 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MP_TQM_RING 0x15UL 3800 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TBL_SCOPE 0x1cUL 3801 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_XID_PARTITION 0x1dUL 3802 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRT_TRACE 0x1eUL 3803 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRT2_TRACE 0x1fUL 3804 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CRT_TRACE 0x20UL 3805 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CRT2_TRACE 0x21UL 3806 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RIGP0_TRACE 0x22UL 3807 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_L2_HWRM_TRACE 0x23UL 3808 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_ROCE_HWRM_TRACE 0x24UL 3809 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TTX_PACING_TQM_RING 0x25UL 3810 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CA0_TRACE 0x26UL 3811 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CA1_TRACE 0x27UL 3812 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CA2_TRACE 0x28UL 3813 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RIGP1_TRACE 0x29UL 3814 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 0xffffUL 3815 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 3841 3816 __le16 instance; 3842 3817 __le32 flags; 3843 3818 __le64 page_dir; ··· 3918 3883 __le32 rsvd2[2]; 3919 3884 }; 3920 3885 3886 + /* ck_split_entries (size:128b/16B) */ 3887 + struct ck_split_entries { 3888 + __le32 num_quic_entries; 3889 + __le32 rsvd; 3890 + __le32 rsvd2[2]; 3891 + }; 3892 + 3921 3893 /* hwrm_func_backing_store_qcaps_v2_input (size:192b/24B) */ 3922 3894 struct hwrm_func_backing_store_qcaps_v2_input { 3923 3895 __le16 req_type; ··· 3933 3891 __le16 target_id; 3934 3892 __le64 resp_addr; 3935 3893 __le16 type; 3936 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QP 0x0UL 3937 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ 0x1UL 3938 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ 0x2UL 3939 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_VNIC 0x3UL 3940 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_STAT 0x4UL 3941 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SP_TQM_RING 0x5UL 3942 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING 0x6UL 3943 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV 0xeUL 3944 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM 0xfUL 3945 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TX_CK 0x13UL 3946 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RX_CK 0x14UL 3947 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3948 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL 3949 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL 3950 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL 3951 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL 3952 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TBL_SCOPE 0x1cUL 3953 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_XID_PARTITION 0x1dUL 3954 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT_TRACE 0x1eUL 3955 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT2_TRACE 0x1fUL 3956 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT_TRACE 0x20UL 3957 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT2_TRACE 0x21UL 3958 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP0_TRACE 0x22UL 3959 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_L2_HWRM_TRACE 0x23UL 3960 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_ROCE_HWRM_TRACE 0x24UL 3961 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 0xffffUL 3962 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 3894 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QP 0x0UL 3895 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ 0x1UL 3896 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ 0x2UL 3897 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_VNIC 0x3UL 3898 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_STAT 0x4UL 3899 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SP_TQM_RING 0x5UL 3900 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING 0x6UL 3901 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV 0xeUL 3902 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM 0xfUL 3903 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TX_CK 0x13UL 3904 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RX_CK 0x14UL 3905 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3906 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL 3907 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL 3908 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL 3909 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL 3910 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TBL_SCOPE 0x1cUL 3911 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_XID_PARTITION 0x1dUL 3912 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT_TRACE 0x1eUL 3913 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT2_TRACE 0x1fUL 3914 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT_TRACE 0x20UL 3915 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT2_TRACE 0x21UL 3916 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP0_TRACE 0x22UL 3917 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_L2_HWRM_TRACE 0x23UL 3918 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_ROCE_HWRM_TRACE 0x24UL 3919 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TTX_PACING_TQM_RING 0x25UL 3920 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA0_TRACE 0x26UL 3921 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA1_TRACE 0x27UL 3922 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA2_TRACE 0x28UL 3923 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP1_TRACE 0x29UL 3924 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 0xffffUL 3925 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 3963 3926 u8 rsvd[6]; 3964 3927 }; 3965 3928 ··· 3975 3928 __le16 seq_id; 3976 3929 __le16 resp_len; 3977 3930 __le16 type; 3978 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QP 0x0UL 3979 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ 0x1UL 3980 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ 0x2UL 3981 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_VNIC 0x3UL 3982 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_STAT 0x4UL 3983 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SP_TQM_RING 0x5UL 3984 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_FP_TQM_RING 0x6UL 3985 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MRAV 0xeUL 3986 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TIM 0xfUL 3987 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TX_CK 0x13UL 3988 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RX_CK 0x14UL 3989 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MP_TQM_RING 0x15UL 3990 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SQ_DB_SHADOW 0x16UL 3991 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RQ_DB_SHADOW 0x17UL 3992 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ_DB_SHADOW 0x18UL 3993 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ_DB_SHADOW 0x19UL 3994 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TBL_SCOPE 0x1cUL 3995 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_XID_PARTITION 0x1dUL 3996 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRT_TRACE 0x1eUL 3997 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRT2_TRACE 0x1fUL 3998 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CRT_TRACE 0x20UL 3999 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CRT2_TRACE 0x21UL 4000 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RIGP0_TRACE 0x22UL 4001 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_L2_HWRM_TRACE 0x23UL 4002 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_ROCE_HWRM_TRACE 0x24UL 4003 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 0xffffUL 4004 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 3931 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QP 0x0UL 3932 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ 0x1UL 3933 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ 0x2UL 3934 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_VNIC 0x3UL 3935 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_STAT 0x4UL 3936 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SP_TQM_RING 0x5UL 3937 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_FP_TQM_RING 0x6UL 3938 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MRAV 0xeUL 3939 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TIM 0xfUL 3940 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TX_CK 0x13UL 3941 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RX_CK 0x14UL 3942 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MP_TQM_RING 0x15UL 3943 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SQ_DB_SHADOW 0x16UL 3944 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RQ_DB_SHADOW 0x17UL 3945 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ_DB_SHADOW 0x18UL 3946 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ_DB_SHADOW 0x19UL 3947 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TBL_SCOPE 0x1cUL 3948 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_XID_PARTITION 0x1dUL 3949 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRT_TRACE 0x1eUL 3950 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRT2_TRACE 0x1fUL 3951 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CRT_TRACE 0x20UL 3952 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CRT2_TRACE 0x21UL 3953 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RIGP0_TRACE 0x22UL 3954 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_L2_HWRM_TRACE 0x23UL 3955 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_ROCE_HWRM_TRACE 0x24UL 3956 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TTX_PACING_TQM_RING 0x25UL 3957 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CA0_TRACE 0x26UL 3958 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CA1_TRACE 0x27UL 3959 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CA2_TRACE 0x28UL 3960 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RIGP1_TRACE 0x29UL 3961 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 0xffffUL 3962 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 4005 3963 __le16 entry_size; 4006 3964 __le32 flags; 4007 3965 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ENABLE_CTX_KIND_INIT 0x1UL 4008 3966 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID 0x2UL 4009 3967 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_DRIVER_MANAGED_MEMORY 0x4UL 4010 3968 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ROCE_QP_PSEUDO_STATIC_ALLOC 0x8UL 3969 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_FW_DBG_TRACE 0x10UL 4011 3970 __le32 instance_bit_map; 4012 3971 u8 ctx_init_value; 4013 3972 u8 ctx_init_offset; ··· 4463 4410 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 4464 4411 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 4465 4412 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT 0x5UL 4413 + #define PORT_PHY_QCFG_RESP_MODULE_STATUS_OVERHEATED 0x6UL 4466 4414 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 4467 4415 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 4468 4416 __le32 preemphasis; ··· 4995 4941 __le16 resp_len; 4996 4942 __le16 tx_stat_size; 4997 4943 __le16 rx_stat_size; 4998 - u8 unused_0[3]; 4944 + u8 flags; 4945 + #define PORT_QSTATS_RESP_FLAGS_CLEARED 0x1UL 4946 + u8 unused_0[2]; 4999 4947 u8 valid; 5000 4948 }; 5001 4949 ··· 5130 5074 __le16 total_active_cos_queues; 5131 5075 u8 flags; 5132 5076 #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL 5077 + #define PORT_QSTATS_EXT_RESP_FLAGS_CLEARED 0x2UL 5133 5078 u8 valid; 5134 5079 }; 5135 5080 ··· 6567 6510 u8 valid; 6568 6511 }; 6569 6512 6513 + /* hwrm_vnic_update_input (size:256b/32B) */ 6514 + struct hwrm_vnic_update_input { 6515 + __le16 req_type; 6516 + __le16 cmpl_ring; 6517 + __le16 seq_id; 6518 + __le16 target_id; 6519 + __le64 resp_addr; 6520 + __le32 vnic_id; 6521 + __le32 enables; 6522 + #define VNIC_UPDATE_REQ_ENABLES_VNIC_STATE_VALID 0x1UL 6523 + #define VNIC_UPDATE_REQ_ENABLES_MRU_VALID 0x2UL 6524 + #define VNIC_UPDATE_REQ_ENABLES_METADATA_FORMAT_TYPE_VALID 0x4UL 6525 + u8 vnic_state; 6526 + #define VNIC_UPDATE_REQ_VNIC_STATE_NORMAL 0x0UL 6527 + #define VNIC_UPDATE_REQ_VNIC_STATE_DROP 0x1UL 6528 + #define VNIC_UPDATE_REQ_VNIC_STATE_LAST VNIC_UPDATE_REQ_VNIC_STATE_DROP 6529 + u8 metadata_format_type; 6530 + #define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_0 0x0UL 6531 + #define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_1 0x1UL 6532 + #define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_2 0x2UL 6533 + #define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_3 0x3UL 6534 + #define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_4 0x4UL 6535 + #define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_LAST VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_4 6536 + __le16 mru; 6537 + u8 unused_1[4]; 6538 + }; 6539 + 6540 + /* hwrm_vnic_update_output (size:128b/16B) */ 6541 + struct hwrm_vnic_update_output { 6542 + __le16 error_code; 6543 + __le16 req_type; 6544 + __le16 seq_id; 6545 + __le16 resp_len; 6546 + u8 unused_0[7]; 6547 + u8 valid; 6548 + }; 6549 + 6570 6550 /* hwrm_vnic_free_input (size:192b/24B) */ 6571 6551 struct hwrm_vnic_free_input { 6572 6552 __le16 req_type; ··· 6734 6640 #define VNIC_QCAPS_RESP_FLAGS_RSS_PROF_TCAM_MODE_ENABLED 0x8000000UL 6735 6641 #define VNIC_QCAPS_RESP_FLAGS_VNIC_RSS_HASH_MODE_CAP 0x10000000UL 6736 6642 #define VNIC_QCAPS_RESP_FLAGS_HW_TUNNEL_TPA_CAP 0x20000000UL 6643 + #define VNIC_QCAPS_RESP_FLAGS_RE_FLUSH_CAP 0x40000000UL 6737 6644 __le16 max_aggs_supported; 6738 6645 u8 unused_1[5]; 6739 6646 u8 valid; ··· 7579 7484 __le16 target_id; 7580 7485 __le64 resp_addr; 7581 7486 __le32 flags; 7582 - #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 7583 - #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL 7584 - #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL 7585 - #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 7586 - #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 7587 - #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL 7588 - #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2 7589 - #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2) 7590 - #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2) 7591 - #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2) 7592 - #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE 7593 - #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_MASK 0x30UL 7594 - #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_SFT 4 7595 - #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_NO_UPDATE (0x0UL << 4) 7596 - #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_BYPASS_LKUP (0x1UL << 4) 7597 - #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_ENABLE_LKUP (0x2UL << 4) 7598 - #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_ENABLE_LKUP 7487 + #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 7488 + #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL 7489 + #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL 7490 + #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 7491 + #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 7492 + #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL 7493 + #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2 7494 + #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2) 7495 + #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2) 7496 + #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2) 7497 + #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE 7498 + #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_MASK 0x30UL 7499 + #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_SFT 4 7500 + #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_NO_UPDATE (0x0UL << 4) 7501 + #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_BYPASS_LKUP (0x1UL << 4) 7502 + #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_ENABLE_LKUP (0x2UL << 4) 7503 + #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_RESTORE_FW_OP (0x3UL << 4) 7504 + #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_RESTORE_FW_OP 7599 7505 __le32 enables; 7600 7506 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 7601 7507 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL ··· 8862 8766 __le64 rx_tpa_events; 8863 8767 }; 8864 8768 8865 - /* hwrm_stat_ctx_alloc_input (size:320b/40B) */ 8769 + /* hwrm_stat_ctx_alloc_input (size:384b/48B) */ 8866 8770 struct hwrm_stat_ctx_alloc_input { 8867 8771 __le16 req_type; 8868 8772 __le16 cmpl_ring; ··· 8872 8776 __le64 stats_dma_addr; 8873 8777 __le32 update_period_ms; 8874 8778 u8 stat_ctx_flags; 8875 - #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 8779 + #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 8780 + #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_DUP_HOST_BUF 0x2UL 8876 8781 u8 unused_0; 8877 8782 __le16 stats_dma_length; 8878 8783 __le16 flags; 8879 8784 #define STAT_CTX_ALLOC_REQ_FLAGS_STEERING_TAG_VALID 0x1UL 8880 8785 __le16 steering_tag; 8881 - __le32 unused_1; 8786 + __le32 stat_ctx_id; 8787 + __le16 alloc_seq_id; 8788 + u8 unused_1[6]; 8882 8789 }; 8883 8790 8884 8791 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */ ··· 9749 9650 __le32 coredump_component_disable_caps; 9750 9651 #define DBG_QCAPS_RESP_COREDUMP_COMPONENT_DISABLE_CAPS_NVRAM 0x1UL 9751 9652 __le32 flags; 9752 - #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_NVM 0x1UL 9753 - #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR 0x2UL 9754 - #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR 0x4UL 9755 - #define DBG_QCAPS_RESP_FLAGS_USEQ 0x8UL 9653 + #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_NVM 0x1UL 9654 + #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR 0x2UL 9655 + #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR 0x4UL 9656 + #define DBG_QCAPS_RESP_FLAGS_USEQ 0x8UL 9657 + #define DBG_QCAPS_RESP_FLAGS_COREDUMP_HOST_DDR 0x10UL 9658 + #define DBG_QCAPS_RESP_FLAGS_COREDUMP_HOST_CAPTURE 0x20UL 9659 + #define DBG_QCAPS_RESP_FLAGS_PTRACE 0x40UL 9756 9660 u8 unused_1[3]; 9757 9661 u8 valid; 9758 9662 }; ··· 10194 10092 u8 valid; 10195 10093 }; 10196 10094 10197 - /* hwrm_nvm_get_dev_info_input (size:128b/16B) */ 10095 + /* hwrm_nvm_get_dev_info_input (size:192b/24B) */ 10198 10096 struct hwrm_nvm_get_dev_info_input { 10199 10097 __le16 req_type; 10200 10098 __le16 cmpl_ring; 10201 10099 __le16 seq_id; 10202 10100 __le16 target_id; 10203 10101 __le64 resp_addr; 10102 + u8 flags; 10103 + #define NVM_GET_DEV_INFO_REQ_FLAGS_SECURITY_SOC_NVM 0x1UL 10104 + u8 unused_0[7]; 10204 10105 }; 10205 10106 10206 - /* hwrm_nvm_get_dev_info_output (size:704b/88B) */ 10107 + /* hwrm_nvm_get_dev_info_output (size:768b/96B) */ 10207 10108 struct hwrm_nvm_get_dev_info_output { 10208 10109 __le16 error_code; 10209 10110 __le16 req_type; ··· 10240 10135 __le16 netctrl_fw_minor; 10241 10136 __le16 netctrl_fw_build; 10242 10137 __le16 netctrl_fw_patch; 10138 + __le16 srt2_fw_major; 10139 + __le16 srt2_fw_minor; 10140 + __le16 srt2_fw_build; 10141 + __le16 srt2_fw_patch; 10243 10142 u8 unused_0[7]; 10244 10143 u8 valid; 10245 10144 };