···1212extern int pcmcia_gcplus_init(struct device *);1313extern int pcmcia_graphicsmaster_init(struct device *);1414extern int pcmcia_h3600_init(struct device *);1515-extern int pcmcia_nanoengine_init(struct device *);1615extern int pcmcia_pangolin_init(struct device *);1716extern int pcmcia_pfs168_init(struct device *);1817extern int pcmcia_shannon_init(struct device *);
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drivers/pcmcia/sa1100_nanoengine.c
···11-/*22- * drivers/pcmcia/sa1100_nanoengine.c33- *44- * PCMCIA implementation routines for BSI nanoEngine.55- *66- * In order to have a fully functional pcmcia subsystem in a BSE nanoEngine77- * board you should carefully read this:88- * http://cambuca.ldhs.cetuc.puc-rio.br/nanoengine/99- *1010- * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>1111- *1212- * Based on original work for kernel 2.4 by1313- * Miguel Freitas <miguel@cpti.cetuc.puc-rio.br>1414- *1515- * This program is free software; you can redistribute it and/or modify1616- * it under the terms of the GNU General Public License version 2 as1717- * published by the Free Software Foundation.1818- *1919- */2020-#include <linux/device.h>2121-#include <linux/errno.h>2222-#include <linux/gpio.h>2323-#include <linux/interrupt.h>2424-#include <linux/irq.h>2525-#include <linux/init.h>2626-#include <linux/kernel.h>2727-#include <linux/module.h>2828-#include <linux/signal.h>2929-3030-#include <asm/mach-types.h>3131-#include <asm/irq.h>3232-3333-#include <mach/hardware.h>3434-#include <mach/nanoengine.h>3535-3636-#include "sa1100_generic.h"3737-3838-struct nanoengine_pins {3939- unsigned output_pins;4040- unsigned clear_outputs;4141- int gpio_rst;4242- int gpio_cd;4343- int gpio_rdy;4444-};4545-4646-static struct nanoengine_pins nano_skts[] = {4747- {4848- .gpio_rst = GPIO_PC_RESET0,4949- .gpio_cd = GPIO_PC_CD0,5050- .gpio_rdy = GPIO_PC_READY0,5151- }, {5252- .gpio_rst = GPIO_PC_RESET1,5353- .gpio_cd = GPIO_PC_CD1,5454- .gpio_rdy = GPIO_PC_READY1,5555- }5656-};5757-5858-unsigned num_nano_pcmcia_sockets = ARRAY_SIZE(nano_skts);5959-6060-static int nanoengine_pcmcia_hw_init(struct soc_pcmcia_socket *skt)6161-{6262- unsigned i = skt->nr;6363- int ret;6464-6565- if (i >= num_nano_pcmcia_sockets)6666- return -ENXIO;6767-6868- ret = gpio_request_one(nano_skts[i].gpio_rst, GPIOF_OUT_INIT_LOW,6969- i ? "PC RST1" : "PC RST0");7070- if (ret)7171- return ret;7272-7373- skt->stat[SOC_STAT_CD].gpio = nano_skts[i].gpio_cd;7474- skt->stat[SOC_STAT_CD].name = i ? "PC CD1" : "PC CD0";7575- skt->stat[SOC_STAT_RDY].gpio = nano_skts[i].gpio_rdy;7676- skt->stat[SOC_STAT_RDY].name = i ? "PC RDY1" : "PC RDY0";7777-7878- return 0;7979-}8080-8181-static void nanoengine_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt)8282-{8383- gpio_free(nano_skts[skt->nr].gpio_rst);8484-}8585-8686-static int nanoengine_pcmcia_configure_socket(8787- struct soc_pcmcia_socket *skt, const socket_state_t *state)8888-{8989- unsigned i = skt->nr;9090-9191- if (i >= num_nano_pcmcia_sockets)9292- return -ENXIO;9393-9494- gpio_set_value(nano_skts[skt->nr].gpio_rst, !!(state->flags & SS_RESET));9595-9696- return 0;9797-}9898-9999-static void nanoengine_pcmcia_socket_state(100100- struct soc_pcmcia_socket *skt, struct pcmcia_state *state)101101-{102102- unsigned i = skt->nr;103103-104104- if (i >= num_nano_pcmcia_sockets)105105- return;106106-107107- state->bvd1 = 1;108108- state->bvd2 = 1;109109- state->vs_3v = 1; /* Can only apply 3.3V */110110- state->vs_Xv = 0;111111-}112112-113113-static struct pcmcia_low_level nanoengine_pcmcia_ops = {114114- .owner = THIS_MODULE,115115-116116- .hw_init = nanoengine_pcmcia_hw_init,117117- .hw_shutdown = nanoengine_pcmcia_hw_shutdown,118118-119119- .configure_socket = nanoengine_pcmcia_configure_socket,120120- .socket_state = nanoengine_pcmcia_socket_state,121121-};122122-123123-int pcmcia_nanoengine_init(struct device *dev)124124-{125125- int ret = -ENODEV;126126-127127- if (machine_is_nanoengine())128128- ret = sa11xx_drv_pcmcia_probe(129129- dev, &nanoengine_pcmcia_ops, 0, 2);130130-131131- return ret;132132-}133133-