tjh.dev
+5
-3
tools/arch/arm64/include/asm/cputype.h
+5
-3
tools/arch/arm64/include/asm/cputype.h
···
81
81
#define ARM_CPU_PART_CORTEX_A78AE 0xD42
82
82
#define ARM_CPU_PART_CORTEX_X1 0xD44
83
83
#define ARM_CPU_PART_CORTEX_A510 0xD46
84
-
#define ARM_CPU_PART_CORTEX_X1C 0xD4C
85
84
#define ARM_CPU_PART_CORTEX_A520 0xD80
86
85
#define ARM_CPU_PART_CORTEX_A710 0xD47
87
86
#define ARM_CPU_PART_CORTEX_A715 0xD4D
···
92
93
#define ARM_CPU_PART_NEOVERSE_V2 0xD4F
93
94
#define ARM_CPU_PART_CORTEX_A720 0xD81
94
95
#define ARM_CPU_PART_CORTEX_X4 0xD82
96
+
#define ARM_CPU_PART_NEOVERSE_V3AE 0xD83
95
97
#define ARM_CPU_PART_NEOVERSE_V3 0xD84
96
98
#define ARM_CPU_PART_CORTEX_X925 0xD85
97
99
#define ARM_CPU_PART_CORTEX_A725 0xD87
···
130
130
131
131
#define NVIDIA_CPU_PART_DENVER 0x003
132
132
#define NVIDIA_CPU_PART_CARMEL 0x004
133
+
#define NVIDIA_CPU_PART_OLYMPUS 0x010
133
134
134
135
#define FUJITSU_CPU_PART_A64FX 0x001
135
136
···
172
171
#define MIDR_CORTEX_A78AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78AE)
173
172
#define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1)
174
173
#define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510)
175
-
#define MIDR_CORTEX_X1C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1C)
176
174
#define MIDR_CORTEX_A520 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520)
177
175
#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)
178
176
#define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A715)
···
183
183
#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)
184
184
#define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720)
185
185
#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)
186
+
#define MIDR_NEOVERSE_V3AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3AE)
186
187
#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
187
188
#define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
188
189
#define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
···
223
222
224
223
#define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)
225
224
#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
225
+
#define MIDR_NVIDIA_OLYMPUS MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_OLYMPUS)
226
226
#define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
227
227
#define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
228
228
#define MIDR_HISI_HIP09 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP09)
···
247
245
/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
248
246
#define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
249
247
#define MIDR_FUJITSU_ERRATUM_010001_MASK (~MIDR_CPU_VAR_REV(1, 0))
250
-
#define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_NFD1 | TCR_NFD0)
248
+
#define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_EL1_NFD1 | TCR_EL1_NFD0)
251
249
252
250
#ifndef __ASSEMBLER__
253
251
+11
tools/arch/x86/include/asm/cpufeatures.h
+11
tools/arch/x86/include/asm/cpufeatures.h
···
314
314
#define X86_FEATURE_SM4 (12*32+ 2) /* SM4 instructions */
315
315
#define X86_FEATURE_AVX_VNNI (12*32+ 4) /* "avx_vnni" AVX VNNI instructions */
316
316
#define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* "avx512_bf16" AVX512 BFLOAT16 instructions */
317
+
#define X86_FEATURE_LASS (12*32+ 6) /* "lass" Linear Address Space Separation */
317
318
#define X86_FEATURE_CMPCCXADD (12*32+ 7) /* CMPccXADD instructions */
318
319
#define X86_FEATURE_ARCH_PERFMON_EXT (12*32+ 8) /* Intel Architectural PerfMon Extension */
319
320
#define X86_FEATURE_FZRM (12*32+10) /* Fast zero-length REP MOVSB */
···
339
338
#define X86_FEATURE_AMD_STIBP (13*32+15) /* Single Thread Indirect Branch Predictors */
340
339
#define X86_FEATURE_AMD_STIBP_ALWAYS_ON (13*32+17) /* Single Thread Indirect Branch Predictors always-on preferred */
341
340
#define X86_FEATURE_AMD_IBRS_SAME_MODE (13*32+19) /* Indirect Branch Restricted Speculation same mode protection*/
341
+
#define X86_FEATURE_EFER_LMSLE_MBZ (13*32+20) /* EFER.LMSLE must be zero */
342
342
#define X86_FEATURE_AMD_PPIN (13*32+23) /* "amd_ppin" Protected Processor Inventory Number */
343
343
#define X86_FEATURE_AMD_SSBD (13*32+24) /* Speculative Store Bypass Disable */
344
344
#define X86_FEATURE_VIRT_SSBD (13*32+25) /* "virt_ssbd" Virtualized Speculative Store Bypass Disable */
···
504
502
#define X86_FEATURE_IBPB_EXIT_TO_USER (21*32+14) /* Use IBPB on exit-to-userspace, see VMSCAPE bug */
505
503
#define X86_FEATURE_ABMC (21*32+15) /* Assignable Bandwidth Monitoring Counters */
506
504
#define X86_FEATURE_MSR_IMM (21*32+16) /* MSR immediate form instructions */
505
+
#define X86_FEATURE_SGX_EUPDATESVN (21*32+17) /* Support for ENCLS[EUPDATESVN] instruction */
506
+
507
+
#define X86_FEATURE_SDCIAE (21*32+18) /* L3 Smart Data Cache Injection Allocation Enforcement */
508
+
#define X86_FEATURE_CLEAR_CPU_BUF_VM_MMIO (21*32+19) /*
509
+
* Clear CPU buffers before VM-Enter if the vCPU
510
+
* can access host MMIO (ignored for all intents
511
+
* and purposes if CLEAR_CPU_BUF_VM is set).
512
+
*/
513
+
#define X86_FEATURE_X2AVIC_EXT (21*32+20) /* AMD SVM x2AVIC support for 4k vCPUs */
507
514
508
515
/*
509
516
* BUG word(s)
+30
tools/arch/x86/include/asm/msr-index.h
+30
tools/arch/x86/include/asm/msr-index.h
···
166
166
* Processor MMIO stale data
167
167
* vulnerabilities.
168
168
*/
169
+
#define ARCH_CAP_MCU_ENUM BIT(16) /*
170
+
* Indicates the presence of microcode update
171
+
* feature enumeration and status information.
172
+
*/
169
173
#define ARCH_CAP_FB_CLEAR BIT(17) /*
170
174
* VERW clears CPU fill buffer
171
175
* even on MDS_NO CPUs.
···
330
326
#define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \
331
327
PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE | \
332
328
PERF_CAP_PEBS_TIMING_INFO)
329
+
330
+
/* Arch PEBS */
331
+
#define MSR_IA32_PEBS_BASE 0x000003f4
332
+
#define MSR_IA32_PEBS_INDEX 0x000003f5
333
+
#define ARCH_PEBS_OFFSET_MASK 0x7fffff
334
+
#define ARCH_PEBS_INDEX_WR_SHIFT 4
335
+
336
+
#define ARCH_PEBS_RELOAD 0xffffffff
337
+
#define ARCH_PEBS_CNTR_ALLOW BIT_ULL(35)
338
+
#define ARCH_PEBS_CNTR_GP BIT_ULL(36)
339
+
#define ARCH_PEBS_CNTR_FIXED BIT_ULL(37)
340
+
#define ARCH_PEBS_CNTR_METRICS BIT_ULL(38)
341
+
#define ARCH_PEBS_LBR_SHIFT 40
342
+
#define ARCH_PEBS_LBR (0x3ull << ARCH_PEBS_LBR_SHIFT)
343
+
#define ARCH_PEBS_VECR_XMM BIT_ULL(49)
344
+
#define ARCH_PEBS_GPR BIT_ULL(61)
345
+
#define ARCH_PEBS_AUX BIT_ULL(62)
346
+
#define ARCH_PEBS_EN BIT_ULL(63)
347
+
#define ARCH_PEBS_CNTR_MASK (ARCH_PEBS_CNTR_GP | ARCH_PEBS_CNTR_FIXED | \
348
+
ARCH_PEBS_CNTR_METRICS)
333
349
334
350
#define MSR_IA32_RTIT_CTL 0x00000570
335
351
#define RTIT_CTL_TRACEEN BIT(0)
···
953
929
#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
954
930
955
931
#define MSR_IA32_UCODE_WRITE 0x00000079
932
+
933
+
#define MSR_IA32_MCU_ENUMERATION 0x0000007b
934
+
#define MCU_STAGING BIT(4)
935
+
956
936
#define MSR_IA32_UCODE_REV 0x0000008b
957
937
958
938
/* Intel SGX Launch Enclave Public Key Hash MSRs */
···
1253
1225
#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
1254
1226
#define MSR_IA32_VMX_VMFUNC 0x00000491
1255
1227
#define MSR_IA32_VMX_PROCBASED_CTLS3 0x00000492
1228
+
1229
+
#define MSR_IA32_MCU_STAGING_MBOX_ADDR 0x000007a5
1256
1230
1257
1231
/* Resctrl MSRs: */
1258
1232
/* - Intel: */
+1
tools/arch/x86/include/uapi/asm/kvm.h
+1
tools/arch/x86/include/uapi/asm/kvm.h
+4
-2
tools/build/Makefile.feature
+4
-2
tools/build/Makefile.feature
···
99
99
libzstd \
100
100
disassembler-four-args \
101
101
disassembler-init-styled \
102
-
file-handle
102
+
file-handle \
103
+
libopenssl
103
104
104
105
# FEATURE_TESTS_BASIC + FEATURE_TESTS_EXTRA is the complete list
105
106
# of all feature tests
···
148
147
lzma \
149
148
bpf \
150
149
libaio \
151
-
libzstd
150
+
libzstd \
151
+
libopenssl
152
152
153
153
#
154
154
# Declare group members of a feature to display the logical OR of the detection
+7
-3
tools/build/feature/Makefile
+7
-3
tools/build/feature/Makefile
···
67
67
test-libopencsd.bin \
68
68
test-clang.bin \
69
69
test-llvm.bin \
70
-
test-llvm-perf.bin \
70
+
test-llvm-perf.bin \
71
71
test-libaio.bin \
72
72
test-libzstd.bin \
73
73
test-clang-bpf-co-re.bin \
74
74
test-file-handle.bin \
75
-
test-libpfm4.bin
75
+
test-libpfm4.bin \
76
+
test-libopenssl.bin
76
77
77
78
FILES := $(addprefix $(OUTPUT),$(FILES))
78
79
···
107
106
__BUILD = $(CC) $(CFLAGS) -MD -Wall -Werror -o $@ $(patsubst %.bin,%.c,$(@F)) $(LDFLAGS)
108
107
BUILD = $(__BUILD) > $(@:.bin=.make.output) 2>&1
109
108
BUILD_BFD = $(BUILD) -DPACKAGE='"perf"' -lbfd -ldl
110
-
BUILD_ALL = $(BUILD) -fstack-protector-all -O2 -D_FORTIFY_SOURCE=2 -ldw -lelf -lnuma -lelf -lslang $(FLAGS_PERL_EMBED) $(FLAGS_PYTHON_EMBED) -ldl -lz -llzma -lzstd
109
+
BUILD_ALL = $(BUILD) -fstack-protector-all -O2 -D_FORTIFY_SOURCE=2 -ldw -lelf -lnuma -lelf -lslang $(FLAGS_PERL_EMBED) $(FLAGS_PYTHON_EMBED) -ldl -lz -llzma -lzstd -lssl
111
110
112
111
__BUILDXX = $(CXX) $(CXXFLAGS) -MD -Wall -Werror -o $@ $(patsubst %.bin,%.cpp,$(@F)) $(LDFLAGS)
113
112
BUILDXX = $(__BUILDXX) > $(@:.bin=.make.output) 2>&1
···
381
380
382
381
$(OUTPUT)test-libpfm4.bin:
383
382
$(BUILD) -lpfm
383
+
384
+
$(OUTPUT)test-libopenssl.bin:
385
+
$(BUILD) -lssl
384
386
385
387
$(OUTPUT)test-bpftool-skeletons.bin:
386
388
$(SYSTEM_BPFTOOL) version | grep '^features:.*skeletons' \
+5
tools/build/feature/test-all.c
+5
tools/build/feature/test-all.c
···
142
142
# include "test-libtraceevent.c"
143
143
#undef main
144
144
145
+
#define main main_test_libopenssl
146
+
# include "test-libopenssl.c"
147
+
#undef main
148
+
145
149
int main(int argc, char *argv[])
146
150
{
147
151
main_test_libpython();
···
177
173
main_test_reallocarray();
178
174
main_test_libzstd();
179
175
main_test_libtraceevent();
176
+
main_test_libopenssl();
180
177
181
178
return 0;
182
179
}
+7
tools/build/feature/test-libopenssl.c
+7
tools/build/feature/test-libopenssl.c
-6
tools/include/linux/gfp_types.h
-6
tools/include/linux/gfp_types.h
···
55
55
#ifdef CONFIG_LOCKDEP
56
56
___GFP_NOLOCKDEP_BIT,
57
57
#endif
58
-
#ifdef CONFIG_SLAB_OBJ_EXT
59
58
___GFP_NO_OBJ_EXT_BIT,
60
-
#endif
61
59
___GFP_LAST_BIT
62
60
};
63
61
···
96
98
#else
97
99
#define ___GFP_NOLOCKDEP 0
98
100
#endif
99
-
#ifdef CONFIG_SLAB_OBJ_EXT
100
101
#define ___GFP_NO_OBJ_EXT BIT(___GFP_NO_OBJ_EXT_BIT)
101
-
#else
102
-
#define ___GFP_NO_OBJ_EXT 0
103
-
#endif
104
102
105
103
/*
106
104
* Physical address zone modifiers (see linux/mmzone.h - low four bits)
+3
-1
tools/include/uapi/asm-generic/unistd.h
+3
-1
tools/include/uapi/asm-generic/unistd.h
···
857
857
__SYSCALL(__NR_file_getattr, sys_file_getattr)
858
858
#define __NR_file_setattr 469
859
859
__SYSCALL(__NR_file_setattr, sys_file_setattr)
860
+
#define __NR_listns 470
861
+
__SYSCALL(__NR_listns, sys_listns)
860
862
861
863
#undef __NR_syscalls
862
-
#define __NR_syscalls 470
864
+
#define __NR_syscalls 471
863
865
864
866
/*
865
867
* 32 bit systems traditionally used different
+15
tools/include/uapi/drm/drm.h
+15
tools/include/uapi/drm/drm.h
···
906
906
*/
907
907
#define DRM_CLIENT_CAP_CURSOR_PLANE_HOTSPOT 6
908
908
909
+
/**
910
+
* DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE
911
+
*
912
+
* If set to 1 the DRM core will allow setting the COLOR_PIPELINE
913
+
* property on a &drm_plane, as well as drm_colorop properties.
914
+
*
915
+
* Setting of these plane properties will be rejected when this client
916
+
* cap is set:
917
+
* - COLOR_ENCODING
918
+
* - COLOR_RANGE
919
+
*
920
+
* The client must enable &DRM_CLIENT_CAP_ATOMIC first.
921
+
*/
922
+
#define DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE 7
923
+
909
924
/* DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
910
925
struct drm_set_client_cap {
911
926
__u64 capability;
+11
tools/include/uapi/linux/kvm.h
+11
tools/include/uapi/linux/kvm.h
···
179
179
#define KVM_EXIT_LOONGARCH_IOCSR 38
180
180
#define KVM_EXIT_MEMORY_FAULT 39
181
181
#define KVM_EXIT_TDX 40
182
+
#define KVM_EXIT_ARM_SEA 41
182
183
183
184
/* For KVM_EXIT_INTERNAL_ERROR */
184
185
/* Emulate instruction failed. */
···
474
473
} setup_event_notify;
475
474
};
476
475
} tdx;
476
+
/* KVM_EXIT_ARM_SEA */
477
+
struct {
478
+
#define KVM_EXIT_ARM_SEA_FLAG_GPA_VALID (1ULL << 0)
479
+
__u64 flags;
480
+
__u64 esr;
481
+
__u64 gva;
482
+
__u64 gpa;
483
+
} arm_sea;
477
484
/* Fix the size of the union. */
478
485
char padding[256];
479
486
};
···
972
963
#define KVM_CAP_RISCV_MP_STATE_RESET 242
973
964
#define KVM_CAP_ARM_CACHEABLE_PFNMAP_SUPPORTED 243
974
965
#define KVM_CAP_GUEST_MEMFD_FLAGS 244
966
+
#define KVM_CAP_ARM_SEA_TO_USER 245
967
+
#define KVM_CAP_S390_USER_OPEREXEC 246
975
968
976
969
struct kvm_irq_routing_irqchip {
977
970
__u32 irqchip;
+8
tools/perf/Makefile.config
+8
tools/perf/Makefile.config
···
701
701
endif
702
702
endif
703
703
704
+
ifeq ($(feature-libopenssl), 1)
705
+
$(call detected,CONFIG_LIBOPENSSL)
706
+
CFLAGS += -DHAVE_LIBOPENSSL_SUPPORT
707
+
endif
708
+
704
709
ifndef BUILD_BPF_SKEL
705
710
# BPF skeletons control a large number of perf features, by default
706
711
# they are enabled.
···
721
716
BUILD_BPF_SKEL := 0
722
717
else ifeq ($(filter -DHAVE_LIBBPF_SUPPORT, $(CFLAGS)),)
723
718
$(warning Warning: Disabled BPF skeletons as libbpf is required)
719
+
BUILD_BPF_SKEL := 0
720
+
else ifeq ($(filter -DHAVE_LIBOPENSSL_SUPPORT, $(CFLAGS)),)
721
+
$(warning Warning: Disabled BPF skeletons as libopenssl is required)
724
722
BUILD_BPF_SKEL := 0
725
723
else ifeq ($(call get-executable,$(CLANG)),)
726
724
$(warning Warning: Disabled BPF skeletons as clang ($(CLANG)) is missing)
+1
tools/perf/arch/arm/entry/syscalls/syscall.tbl
+1
tools/perf/arch/arm/entry/syscalls/syscall.tbl
+1
tools/perf/arch/mips/entry/syscalls/syscall_n64.tbl
+1
tools/perf/arch/mips/entry/syscalls/syscall_n64.tbl
+1
tools/perf/arch/powerpc/entry/syscalls/syscall.tbl
+1
tools/perf/arch/powerpc/entry/syscalls/syscall.tbl
+1
tools/perf/arch/s390/entry/syscalls/syscall.tbl
+1
tools/perf/arch/s390/entry/syscalls/syscall.tbl
+1
tools/perf/arch/sh/entry/syscalls/syscall.tbl
+1
tools/perf/arch/sh/entry/syscalls/syscall.tbl
+1
tools/perf/arch/sparc/entry/syscalls/syscall.tbl
+1
tools/perf/arch/sparc/entry/syscalls/syscall.tbl
+1
tools/perf/arch/x86/entry/syscalls/syscall_32.tbl
+1
tools/perf/arch/x86/entry/syscalls/syscall_32.tbl
+1
tools/perf/arch/x86/entry/syscalls/syscall_64.tbl
+1
tools/perf/arch/x86/entry/syscalls/syscall_64.tbl
+1
tools/perf/arch/xtensa/entry/syscalls/syscall.tbl
+1
tools/perf/arch/xtensa/entry/syscalls/syscall.tbl
+4
-2
tools/perf/builtin-buildid-cache.c
+4
-2
tools/perf/builtin-buildid-cache.c
···
276
276
{
277
277
char filename[PATH_MAX];
278
278
struct build_id bid = { .size = 0, };
279
+
int err;
279
280
280
281
if (!dso__build_id_filename(dso, filename, sizeof(filename), false))
281
282
return true;
282
283
283
-
if (filename__read_build_id(filename, &bid) == -1) {
284
-
if (errno == ENOENT)
284
+
err = filename__read_build_id(filename, &bid);
285
+
if (err < 0) {
286
+
if (err == -ENOENT)
285
287
return false;
286
288
287
289
pr_warning("Problems with %s file, consider removing it from the cache\n",
+1
-1
tools/perf/tests/shell/kvm.sh
+1
-1
tools/perf/tests/shell/kvm.sh
+1
-1
tools/perf/tests/shell/top.sh
+1
-1
tools/perf/tests/shell/top.sh
+21
-3
tools/perf/trace/beauty/include/linux/socket.h
+21
-3
tools/perf/trace/beauty/include/linux/socket.h
···
32
32
* 1003.1g requires sa_family_t and that sa_data is char.
33
33
*/
34
34
35
+
/* Deprecated for in-kernel use. Use struct sockaddr_unsized instead. */
35
36
struct sockaddr {
36
37
sa_family_t sa_family; /* address family, AF_xxx */
37
38
char sa_data[14]; /* 14 bytes of protocol address */
39
+
};
40
+
41
+
/**
42
+
* struct sockaddr_unsized - Unspecified size sockaddr for callbacks
43
+
* @sa_family: Address family (AF_UNIX, AF_INET, AF_INET6, etc.)
44
+
* @sa_data: Flexible array for address data
45
+
*
46
+
* This structure is designed for callback interfaces where the
47
+
* total size is known via the sockaddr_len parameter. Unlike struct
48
+
* sockaddr which has a fixed 14-byte sa_data limit or struct
49
+
* sockaddr_storage which has a fixed 128-byte sa_data limit, this
50
+
* structure can accommodate addresses of any size, but must be used
51
+
* carefully.
52
+
*/
53
+
struct sockaddr_unsized {
54
+
__kernel_sa_family_t sa_family; /* address family, AF_xxx */
55
+
char sa_data[]; /* flexible address data */
38
56
};
39
57
40
58
struct linger {
···
468
450
int addrlen);
469
451
extern int __sys_listen(int fd, int backlog);
470
452
extern int __sys_listen_socket(struct socket *sock, int backlog);
453
+
extern int do_getsockname(struct socket *sock, int peer,
454
+
struct sockaddr __user *usockaddr, int __user *usockaddr_len);
471
455
extern int __sys_getsockname(int fd, struct sockaddr __user *usockaddr,
472
-
int __user *usockaddr_len);
473
-
extern int __sys_getpeername(int fd, struct sockaddr __user *usockaddr,
474
-
int __user *usockaddr_len);
456
+
int __user *usockaddr_len, int peer);
475
457
extern int __sys_socketpair(int family, int type, int protocol,
476
458
int __user *usockvec);
477
459
extern int __sys_shutdown_sock(struct socket *sock, int how);
+12
tools/perf/trace/beauty/include/uapi/linux/fcntl.h
+12
tools/perf/trace/beauty/include/uapi/linux/fcntl.h
···
4
4
5
5
#include <asm/fcntl.h>
6
6
#include <linux/openat2.h>
7
+
#include <linux/types.h>
7
8
8
9
#define F_SETLEASE (F_LINUX_SPECIFIC_BASE + 0)
9
10
#define F_GETLEASE (F_LINUX_SPECIFIC_BASE + 1)
···
79
78
* v4.13-rc1~212^2~51.
80
79
*/
81
80
#define RWF_WRITE_LIFE_NOT_SET RWH_WRITE_LIFE_NOT_SET
81
+
82
+
/* Set/Get delegations */
83
+
#define F_GETDELEG (F_LINUX_SPECIFIC_BASE + 15)
84
+
#define F_SETDELEG (F_LINUX_SPECIFIC_BASE + 16)
85
+
86
+
/* Argument structure for F_GETDELEG and F_SETDELEG */
87
+
struct delegation {
88
+
__u32 d_flags; /* Must be 0 */
89
+
__u16 d_type; /* F_RDLCK, F_WRLCK, F_UNLCK */
90
+
__u16 __pad; /* Must be 0 */
91
+
};
82
92
83
93
/*
84
94
* Types of directory notifications that may be requested.
+2
-1
tools/perf/trace/beauty/include/uapi/linux/fs.h
+2
-1
tools/perf/trace/beauty/include/uapi/linux/fs.h
···
298
298
#define BLKROTATIONAL _IO(0x12,126)
299
299
#define BLKZEROOUT _IO(0x12,127)
300
300
#define BLKGETDISKSEQ _IOR(0x12,128,__u64)
301
-
/* 130-136 are used by zoned block device ioctls (uapi/linux/blkzoned.h) */
301
+
/* 130-136 and 142 are used by zoned block device ioctls (uapi/linux/blkzoned.h) */
302
302
/* 137-141 are used by blk-crypto ioctls (uapi/linux/blk-crypto.h) */
303
+
#define BLKTRACESETUP2 _IOWR(0x12, 142, struct blk_user_trace_setup2)
303
304
304
305
#define BMAP_IOCTL 1 /* obsolete - kept for compatibility */
305
306
#define FIBMAP _IO(0x00,1) /* bmap access */
+1
-1
tools/perf/trace/beauty/include/uapi/linux/mount.h
+1
-1
tools/perf/trace/beauty/include/uapi/linux/mount.h
+1
-1
tools/perf/trace/beauty/include/uapi/sound/asound.h
+1
-1
tools/perf/trace/beauty/include/uapi/sound/asound.h
···
60
60
unsigned char db2_sf_ss; /* sample frequency and size */
61
61
unsigned char db3; /* not used, all zeros */
62
62
unsigned char db4_ca; /* channel allocation code */
63
-
unsigned char db5_dminh_lsv; /* downmix inhibit & level-shit values */
63
+
unsigned char db5_dminh_lsv; /* downmix inhibit & level-shift values */
64
64
};
65
65
66
66
/****************************************************************************
+1
tools/perf/util/arm-spe.c
+1
tools/perf/util/arm-spe.c
+3
-1
tools/perf/util/libbfd.c
+3
-1
tools/perf/util/libbfd.c
+3
-1
tools/perf/util/symbol-elf.c
+3
-1
tools/perf/util/symbol-elf.c
+3
-1
tools/perf/util/symbol-minimal.c
+3
-1
tools/perf/util/symbol-minimal.c