Merge tag 'mips_6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

+2 -1

arch/mips/Kconfig

··· 29 29 select ARCH_WANT_IPC_PARSE_VERSION 30 30 select ARCH_WANT_LD_ORPHAN_WARN 31 31 select BUILDTIME_TABLE_SORT 32 + select BUILTIN_DTB_ALL if BUILTIN_DTB 32 33 select CLONE_BACKWARDS 33 34 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1) 34 35 select CPU_PM if CPU_IDLE || SUSPEND 35 36 select GENERIC_ATOMIC64 if !64BIT 37 + select GENERIC_BUILTIN_DTB if BUILTIN_DTB 36 38 select GENERIC_CMOS_UPDATE 37 39 select GENERIC_CPU_AUTOPROBE 38 40 select GENERIC_GETTIMEOFDAY ··· 1086 1084 1087 1085 config CSRC_R4K 1088 1086 select CLOCKSOURCE_WATCHDOG if CPU_FREQ 1089 - select HAVE_UNSTABLE_SCHED_CLOCK if SMP && 64BIT 1090 1087 bool 1091 1088 1092 1089 config CSRC_SB1250

-3

arch/mips/Makefile

··· 423 423 424 424 CLEAN_FILES += vmlinux.32 vmlinux.64 425 425 426 - # device-trees 427 - core-y += arch/mips/boot/dts/ 428 - 429 426 archprepare: 430 427 ifdef CONFIG_MIPS32_N32 431 428 @$(kecho) ' Checking missing-syscalls for N32'

-2

arch/mips/boot/dts/Makefile

··· 16 16 subdir-$(CONFIG_RALINK) += ralink 17 17 subdir-$(CONFIG_MACH_REALTEK_RTL) += realtek 18 18 subdir-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += xilfpga 19 - 20 - obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))

-2

arch/mips/boot/dts/brcm/Makefile

··· 33 33 bcm97420c.dtb \ 34 34 bcm97425svmb.dtb \ 35 35 bcm97435svmb.dtb 36 - 37 - obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

-2

arch/mips/boot/dts/cavium-octeon/Makefile

··· 1 1 # SPDX-License-Identifier: GPL-2.0 2 2 dtb-$(CONFIG_CAVIUM_OCTEON_SOC) += octeon_3xxx.dtb octeon_68xx.dtb 3 - 4 - obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

-2

arch/mips/boot/dts/ingenic/Makefile

··· 5 5 dtb-$(CONFIG_JZ4780_CI20) += ci20.dtb 6 6 dtb-$(CONFIG_X1000_CU1000_NEO) += cu1000-neo.dtb 7 7 dtb-$(CONFIG_X1830_CU1830_NEO) += cu1830-neo.dtb 8 - 9 - obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

-2

arch/mips/boot/dts/lantiq/Makefile

··· 1 1 # SPDX-License-Identifier: GPL-2.0 2 2 dtb-$(CONFIG_DT_EASY50712) += danube_easy50712.dtb 3 - 4 - obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

-2

arch/mips/boot/dts/loongson/Makefile

··· 5 5 dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_8core_rs780e.dtb 6 6 dtb-$(CONFIG_MACH_LOONGSON64) += loongson64g_4core_ls7a.dtb 7 7 dtb-$(CONFIG_MACH_LOONGSON64) += loongson64v_4core_virtio.dtb 8 - 9 - obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

-3

arch/mips/boot/dts/mscc/Makefile

··· 8 8 ocelot_pcb123.dtb \ 9 9 serval_pcb105.dtb \ 10 10 serval_pcb106.dtb 11 - 12 - 13 - obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

-2

arch/mips/boot/dts/mti/Makefile

··· 1 1 # SPDX-License-Identifier: GPL-2.0 2 2 dtb-$(CONFIG_MIPS_MALTA) += malta.dtb 3 3 dtb-$(CONFIG_LEGACY_BOARD_SEAD3) += sead3.dtb 4 - 5 - obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

-2

arch/mips/boot/dts/pic32/Makefile

··· 3 3 4 4 dtb-$(CONFIG_DTB_PIC32_NONE) += \ 5 5 pic32mzda_sk.dtb 6 - 7 - obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

-2

arch/mips/boot/dts/ralink/Makefile

··· 10 10 mt7621-gnubee-gb-pc1.dtb \ 11 11 mt7621-gnubee-gb-pc2.dtb \ 12 12 mt7621-tplink-hc220-g5-v1.dtb 13 - 14 - obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

+4 -4

arch/mips/include/asm/mach-loongson64/boot_param.h

··· 128 128 } __packed; 129 129 130 130 struct interface_info { 131 - u16 vers; /* version of the specificition */ 132 - u16 size; 133 - u8 flag; 134 - char description[64]; 131 + u16 vers; /* version of the specification */ 132 + u16 size; /* size of this interface */ 133 + u8 flag; /* used or unused */ 134 + char description[64]; /* description for each change */ 135 135 } __packed; 136 136 137 137 #define MAX_RESOURCE_NUMBER 128

+2 -2

arch/mips/include/asm/mipsregs.h

··· 2039 2039 #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7) 2040 2040 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val) 2041 2041 2042 - #define read_c0_ecc() __read_32bit_c0_register($26, 0) 2043 - #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) 2042 + #define read_c0_errctl() __read_32bit_c0_register($26, 0) 2043 + #define write_c0_errctl(val) __write_32bit_c0_register($26, 0, val) 2044 2044 2045 2045 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1) 2046 2046 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)

+1 -1

arch/mips/kernel/cevt-bcm1480.c

··· 103 103 104 104 BUG_ON(cpu > 3); /* Only have 4 general purpose timers */ 105 105 106 - sprintf(name, "bcm1480-counter-%d", cpu); 106 + sprintf(name, "bcm1480-counter-%u", cpu); 107 107 cd->name = name; 108 108 cd->features = CLOCK_EVT_FEAT_PERIODIC | 109 109 CLOCK_EVT_FEAT_ONESHOT;

+1 -1

arch/mips/kernel/ftrace.c

··· 248 248 #define S_R_SP (0xafb0 << 16) /* s{d,w} R, offset(sp) */ 249 249 #define OFFSET_MASK 0xffff /* stack offset range: 0 ~ PT_SIZE */ 250 250 251 - unsigned long ftrace_get_parent_ra_addr(unsigned long self_ra, unsigned long 251 + static unsigned long ftrace_get_parent_ra_addr(unsigned long self_ra, unsigned long 252 252 old_parent_ra, unsigned long parent_ra_addr, unsigned long fp) 253 253 { 254 254 unsigned long sp, ip, tmp;

+1

arch/mips/kernel/head.S

··· 60 60 .endm 61 61 62 62 __HEAD 63 + 63 64 #ifndef CONFIG_NO_EXCEPT_FILL 64 65 /* 65 66 * Reserved space for exception handlers.

+3 -4

arch/mips/kernel/mips-mt.c

··· 122 122 unsigned long ectlval; 123 123 unsigned long itcblkgrn; 124 124 125 - /* ErrCtl register is known as "ecc" to Linux */ 126 - ectlval = read_c0_ecc(); 127 - write_c0_ecc(ectlval | (0x1 << 26)); 125 + ectlval = read_c0_errctl(); 126 + write_c0_errctl(ectlval | (0x1 << 26)); 128 127 ehb(); 129 128 #define INDEX_0 (0x80000000) 130 129 #define INDEX_8 (0x80000008) ··· 144 145 ehb(); 145 146 /* Write out to ITU with CACHE op */ 146 147 cache_op(Index_Store_Tag_D, INDEX_0); 147 - write_c0_ecc(ectlval); 148 + write_c0_errctl(ectlval); 148 149 ehb(); 149 150 printk("Mapped %ld ITC cells starting at 0x%08x\n", 150 151 ((itcblkgrn & 0x7fe00000) >> 20), itc_base);

-4

arch/mips/kernel/spram.c

··· 26 26 27 27 #define ERRCTL_SPRAM (1 << 28) 28 28 29 - /* errctl access */ 30 - #define read_c0_errctl(x) read_c0_ecc(x) 31 - #define write_c0_errctl(x) write_c0_ecc(x) 32 - 33 29 /* 34 30 * Different semantics to the set_c0_* function built by __BUILD_SET_C0 35 31 */

+3 -3

arch/mips/kernel/syscalls/syscall_o32.tbl

··· 382 382 368 o32 io_pgetevents sys_io_pgetevents_time32 compat_sys_io_pgetevents 383 383 # room for arch specific calls 384 384 393 o32 semget sys_semget 385 - 394 o32 semctl sys_semctl compat_sys_semctl 385 + 394 o32 semctl sys_old_semctl compat_sys_old_semctl 386 386 395 o32 shmget sys_shmget 387 - 396 o32 shmctl sys_shmctl compat_sys_shmctl 387 + 396 o32 shmctl sys_old_shmctl compat_sys_old_shmctl 388 388 397 o32 shmat sys_shmat compat_sys_shmat 389 389 398 o32 shmdt sys_shmdt 390 390 399 o32 msgget sys_msgget 391 391 400 o32 msgsnd sys_msgsnd compat_sys_msgsnd 392 392 401 o32 msgrcv sys_msgrcv compat_sys_msgrcv 393 - 402 o32 msgctl sys_msgctl compat_sys_msgctl 393 + 402 o32 msgctl sys_old_msgctl compat_sys_old_msgctl 394 394 403 o32 clock_gettime64 sys_clock_gettime sys_clock_gettime 395 395 404 o32 clock_settime64 sys_clock_settime sys_clock_settime 396 396 405 o32 clock_adjtime64 sys_clock_adjtime sys_clock_adjtime

+24 -23

arch/mips/kernel/traps.c

··· 38 38 #include <linux/kdb.h> 39 39 #include <linux/irq.h> 40 40 #include <linux/perf_event.h> 41 + #include <linux/string_choices.h> 41 42 42 43 #include <asm/addrspace.h> 43 44 #include <asm/bootinfo.h> ··· 1706 1705 l2parity &= l1parity; 1707 1706 1708 1707 /* Probe L1 ECC support */ 1709 - cp0_ectl = read_c0_ecc(); 1710 - write_c0_ecc(cp0_ectl | ERRCTL_PE); 1708 + cp0_ectl = read_c0_errctl(); 1709 + write_c0_errctl(cp0_ectl | ERRCTL_PE); 1711 1710 back_to_back_c0_hazard(); 1712 - cp0_ectl = read_c0_ecc(); 1711 + cp0_ectl = read_c0_errctl(); 1713 1712 1714 1713 /* Probe L2 ECC support */ 1715 1714 gcr_ectl = read_gcr_err_control(); ··· 1728 1727 cp0_ectl |= ERRCTL_PE; 1729 1728 else 1730 1729 cp0_ectl &= ~ERRCTL_PE; 1731 - write_c0_ecc(cp0_ectl); 1730 + write_c0_errctl(cp0_ectl); 1732 1731 back_to_back_c0_hazard(); 1733 - WARN_ON(!!(read_c0_ecc() & ERRCTL_PE) != l1parity); 1732 + WARN_ON(!!(read_c0_errctl() & ERRCTL_PE) != l1parity); 1734 1733 1735 1734 /* Configure L2 ECC checking */ 1736 1735 if (l2parity) ··· 1742 1741 gcr_ectl &= CM_GCR_ERR_CONTROL_L2_ECC_EN; 1743 1742 WARN_ON(!!gcr_ectl != l2parity); 1744 1743 1745 - pr_info("Cache parity protection %sabled\n", 1746 - l1parity ? "en" : "dis"); 1744 + pr_info("Cache parity protection %s\n", 1745 + str_enabled_disabled(l1parity)); 1747 1746 return; 1748 1747 } 1749 1748 ··· 1762 1761 unsigned long errctl; 1763 1762 unsigned int l1parity_present, l2parity_present; 1764 1763 1765 - errctl = read_c0_ecc(); 1764 + errctl = read_c0_errctl(); 1766 1765 errctl &= ~(ERRCTL_PE|ERRCTL_L2P); 1767 1766 1768 1767 /* probe L1 parity support */ 1769 - write_c0_ecc(errctl | ERRCTL_PE); 1768 + write_c0_errctl(errctl | ERRCTL_PE); 1770 1769 back_to_back_c0_hazard(); 1771 - l1parity_present = (read_c0_ecc() & ERRCTL_PE); 1770 + l1parity_present = (read_c0_errctl() & ERRCTL_PE); 1772 1771 1773 1772 /* probe L2 parity support */ 1774 - write_c0_ecc(errctl|ERRCTL_L2P); 1773 + write_c0_errctl(errctl|ERRCTL_L2P); 1775 1774 back_to_back_c0_hazard(); 1776 - l2parity_present = (read_c0_ecc() & ERRCTL_L2P); 1775 + l2parity_present = (read_c0_errctl() & ERRCTL_L2P); 1777 1776 1778 1777 if (l1parity_present && l2parity_present) { 1779 1778 if (l1parity) ··· 1792 1791 1793 1792 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); 1794 1793 1795 - write_c0_ecc(errctl); 1794 + write_c0_errctl(errctl); 1796 1795 back_to_back_c0_hazard(); 1797 - errctl = read_c0_ecc(); 1796 + errctl = read_c0_errctl(); 1798 1797 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); 1799 1798 1800 1799 if (l1parity_present) 1801 - printk(KERN_INFO "Cache parity protection %sabled\n", 1802 - (errctl & ERRCTL_PE) ? "en" : "dis"); 1800 + pr_info("Cache parity protection %s\n", 1801 + str_enabled_disabled(errctl & ERRCTL_PE)); 1803 1802 1804 1803 if (l2parity_present) { 1805 1804 if (l1parity_present && l1parity) 1806 1805 errctl ^= ERRCTL_L2P; 1807 - printk(KERN_INFO "L2 cache parity protection %sabled\n", 1808 - (errctl & ERRCTL_L2P) ? "en" : "dis"); 1806 + pr_info("L2 cache parity protection %s\n", 1807 + str_enabled_disabled(errctl & ERRCTL_L2P)); 1809 1808 } 1810 1809 } 1811 1810 break; ··· 1813 1812 case CPU_5KC: 1814 1813 case CPU_5KE: 1815 1814 case CPU_LOONGSON32: 1816 - write_c0_ecc(0x80000000); 1815 + write_c0_errctl(0x80000000); 1817 1816 back_to_back_c0_hazard(); 1818 1817 /* Set the PE bit (bit 31) in the c0_errctl register. */ 1819 - printk(KERN_INFO "Cache parity protection %sabled\n", 1820 - (read_c0_ecc() & 0x80000000) ? "en" : "dis"); 1818 + pr_info("Cache parity protection %s\n", 1819 + str_enabled_disabled(read_c0_errctl() & 0x80000000)); 1821 1820 break; 1822 1821 case CPU_20KC: 1823 1822 case CPU_25KF: ··· 1888 1887 if ((cpu_has_mips_r2_r6) && 1889 1888 (((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS) || 1890 1889 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_LOONGSON))) { 1891 - pr_err("FTLB error exception, cp0_ecc=0x%08x:\n", 1892 - read_c0_ecc()); 1890 + pr_err("FTLB error exception, cp0_errctl=0x%08x:\n", 1891 + read_c0_errctl()); 1893 1892 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 1894 1893 reg_val = read_c0_cacheerr(); 1895 1894 pr_err("c0_cacheerr == %08x\n", reg_val);

-2

arch/mips/loongson64/boardinfo.c

··· 21 21 "BIOS Info\n" 22 22 "Vendor\t\t\t: %s\n" 23 23 "Version\t\t\t: %s\n" 24 - "ROM Size\t\t: %d KB\n" 25 24 "Release Date\t\t: %s\n", 26 25 strsep(&tmp_board_manufacturer, "-"), 27 26 eboard->name, 28 27 strsep(&tmp_bios_vendor, "-"), 29 28 einter->description, 30 - einter->size, 31 29 especial->special_name); 32 30 } 33 31 static struct kobj_attribute boardinfo_attr = __ATTR(boardinfo, 0444,

+2 -1

arch/mips/loongson64/env.c

··· 17 17 #include <linux/dma-map-ops.h> 18 18 #include <linux/export.h> 19 19 #include <linux/pci_ids.h> 20 + #include <linux/string_choices.h> 20 21 #include <asm/bootinfo.h> 21 22 #include <loongson.h> 22 23 #include <boot_param.h> ··· 163 162 dma_default_coherent = !eirq_source->dma_noncoherent; 164 163 } 165 164 166 - pr_info("Firmware: Coherent DMA: %s\n", dma_default_coherent ? "on" : "off"); 165 + pr_info("Firmware: Coherent DMA: %s\n", str_on_off(dma_default_coherent)); 167 166 168 167 loongson_sysconf.restart_addr = boot_p->reset_system.ResetWarm; 169 168 loongson_sysconf.poweroff_addr = boot_p->reset_system.Shutdown;

+1 -1

arch/mips/math-emu/cp1emu.c

··· 1660 1660 break; 1661 1661 } 1662 1662 1663 - case 0x3: 1663 + case 0x7: 1664 1664 if (MIPSInst_FUNC(ir) != pfetch_op) 1665 1665 return SIGILL; 1666 1666

+8

arch/mips/pci/pci-legacy.c

··· 29 29 30 30 static int pci_initialized; 31 31 32 + unsigned long pci_address_to_pio(phys_addr_t address) 33 + { 34 + if (address > IO_SPACE_LIMIT) 35 + return (unsigned long)-1; 36 + 37 + return (unsigned long) address; 38 + } 39 + 32 40 /* 33 41 * We need to avoid collisions with `mirrored' VGA ports 34 42 * and other strange ISA hardware, so we always want the