dt-bindings: clock: Add StarFive JH7110 system clock and reset generator

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Add bindings for the system clock and reset generator (SYSCRG) on the
JH7110 RISC-V SoC by StarFive Ltd.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

authored by

Emil Renner Berthing and committed by

Conor Dooley 3 years ago 7fce1e39 eeac8ede

+449

3 changed files

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Documentation

devicetree

bindings

clock

starfive,jh7110-syscrg.yaml

include

dt-bindings

clock

starfive,jh7110-crg.h

reset

starfive,jh7110-crg.h

+104

Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/starfive,jh7110-syscrg.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: StarFive JH7110 System Clock and Reset Generator 8 + 9 + maintainers: 10 + - Emil Renner Berthing <kernel@esmil.dk> 11 + 12 + properties: 13 + compatible: 14 + const: starfive,jh7110-syscrg 15 + 16 + reg: 17 + maxItems: 1 18 + 19 + clocks: 20 + oneOf: 21 + - items: 22 + - description: Main Oscillator (24 MHz) 23 + - description: GMAC1 RMII reference or GMAC1 RGMII RX 24 + - description: External I2S TX bit clock 25 + - description: External I2S TX left/right channel clock 26 + - description: External I2S RX bit clock 27 + - description: External I2S RX left/right channel clock 28 + - description: External TDM clock 29 + - description: External audio master clock 30 + 31 + - items: 32 + - description: Main Oscillator (24 MHz) 33 + - description: GMAC1 RMII reference 34 + - description: GMAC1 RGMII RX 35 + - description: External I2S TX bit clock 36 + - description: External I2S TX left/right channel clock 37 + - description: External I2S RX bit clock 38 + - description: External I2S RX left/right channel clock 39 + - description: External TDM clock 40 + - description: External audio master clock 41 + 42 + clock-names: 43 + oneOf: 44 + - items: 45 + - const: osc 46 + - enum: 47 + - gmac1_rmii_refin 48 + - gmac1_rgmii_rxin 49 + - const: i2stx_bclk_ext 50 + - const: i2stx_lrck_ext 51 + - const: i2srx_bclk_ext 52 + - const: i2srx_lrck_ext 53 + - const: tdm_ext 54 + - const: mclk_ext 55 + 56 + - items: 57 + - const: osc 58 + - const: gmac1_rmii_refin 59 + - const: gmac1_rgmii_rxin 60 + - const: i2stx_bclk_ext 61 + - const: i2stx_lrck_ext 62 + - const: i2srx_bclk_ext 63 + - const: i2srx_lrck_ext 64 + - const: tdm_ext 65 + - const: mclk_ext 66 + 67 + '#clock-cells': 68 + const: 1 69 + description: 70 + See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices. 71 + 72 + '#reset-cells': 73 + const: 1 74 + description: 75 + See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices. 76 + 77 + required: 78 + - compatible 79 + - reg 80 + - clocks 81 + - clock-names 82 + - '#clock-cells' 83 + - '#reset-cells' 84 + 85 + additionalProperties: false 86 + 87 + examples: 88 + - | 89 + clock-controller@13020000 { 90 + compatible = "starfive,jh7110-syscrg"; 91 + reg = <0x13020000 0x10000>; 92 + clocks = <&osc>, <&gmac1_rmii_refin>, 93 + <&gmac1_rgmii_rxin>, 94 + <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, 95 + <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, 96 + <&tdm_ext>, <&mclk_ext>; 97 + clock-names = "osc", "gmac1_rmii_refin", 98 + "gmac1_rgmii_rxin", 99 + "i2stx_bclk_ext", "i2stx_lrck_ext", 100 + "i2srx_bclk_ext", "i2srx_lrck_ext", 101 + "tdm_ext", "mclk_ext"; 102 + #clock-cells = <1>; 103 + #reset-cells = <1>; 104 + };

+203

include/dt-bindings/clock/starfive,jh7110-crg.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 2 + /* 3 + * Copyright 2022 Emil Renner Berthing <kernel@esmil.dk> 4 + */ 5 + 6 + #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ 7 + #define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ 8 + 9 + /* SYSCRG clocks */ 10 + #define JH7110_SYSCLK_CPU_ROOT 0 11 + #define JH7110_SYSCLK_CPU_CORE 1 12 + #define JH7110_SYSCLK_CPU_BUS 2 13 + #define JH7110_SYSCLK_GPU_ROOT 3 14 + #define JH7110_SYSCLK_PERH_ROOT 4 15 + #define JH7110_SYSCLK_BUS_ROOT 5 16 + #define JH7110_SYSCLK_NOCSTG_BUS 6 17 + #define JH7110_SYSCLK_AXI_CFG0 7 18 + #define JH7110_SYSCLK_STG_AXIAHB 8 19 + #define JH7110_SYSCLK_AHB0 9 20 + #define JH7110_SYSCLK_AHB1 10 21 + #define JH7110_SYSCLK_APB_BUS 11 22 + #define JH7110_SYSCLK_APB0 12 23 + #define JH7110_SYSCLK_PLL0_DIV2 13 24 + #define JH7110_SYSCLK_PLL1_DIV2 14 25 + #define JH7110_SYSCLK_PLL2_DIV2 15 26 + #define JH7110_SYSCLK_AUDIO_ROOT 16 27 + #define JH7110_SYSCLK_MCLK_INNER 17 28 + #define JH7110_SYSCLK_MCLK 18 29 + #define JH7110_SYSCLK_MCLK_OUT 19 30 + #define JH7110_SYSCLK_ISP_2X 20 31 + #define JH7110_SYSCLK_ISP_AXI 21 32 + #define JH7110_SYSCLK_GCLK0 22 33 + #define JH7110_SYSCLK_GCLK1 23 34 + #define JH7110_SYSCLK_GCLK2 24 35 + #define JH7110_SYSCLK_CORE 25 36 + #define JH7110_SYSCLK_CORE1 26 37 + #define JH7110_SYSCLK_CORE2 27 38 + #define JH7110_SYSCLK_CORE3 28 39 + #define JH7110_SYSCLK_CORE4 29 40 + #define JH7110_SYSCLK_DEBUG 30 41 + #define JH7110_SYSCLK_RTC_TOGGLE 31 42 + #define JH7110_SYSCLK_TRACE0 32 43 + #define JH7110_SYSCLK_TRACE1 33 44 + #define JH7110_SYSCLK_TRACE2 34 45 + #define JH7110_SYSCLK_TRACE3 35 46 + #define JH7110_SYSCLK_TRACE4 36 47 + #define JH7110_SYSCLK_TRACE_COM 37 48 + #define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38 49 + #define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39 50 + #define JH7110_SYSCLK_OSC_DIV2 40 51 + #define JH7110_SYSCLK_PLL1_DIV4 41 52 + #define JH7110_SYSCLK_PLL1_DIV8 42 53 + #define JH7110_SYSCLK_DDR_BUS 43 54 + #define JH7110_SYSCLK_DDR_AXI 44 55 + #define JH7110_SYSCLK_GPU_CORE 45 56 + #define JH7110_SYSCLK_GPU_CORE_CLK 46 57 + #define JH7110_SYSCLK_GPU_SYS_CLK 47 58 + #define JH7110_SYSCLK_GPU_APB 48 59 + #define JH7110_SYSCLK_GPU_RTC_TOGGLE 49 60 + #define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50 61 + #define JH7110_SYSCLK_ISP_TOP_CORE 51 62 + #define JH7110_SYSCLK_ISP_TOP_AXI 52 63 + #define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53 64 + #define JH7110_SYSCLK_HIFI4_CORE 54 65 + #define JH7110_SYSCLK_HIFI4_AXI 55 66 + #define JH7110_SYSCLK_AXI_CFG1_MAIN 56 67 + #define JH7110_SYSCLK_AXI_CFG1_AHB 57 68 + #define JH7110_SYSCLK_VOUT_SRC 58 69 + #define JH7110_SYSCLK_VOUT_AXI 59 70 + #define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60 71 + #define JH7110_SYSCLK_VOUT_TOP_AHB 61 72 + #define JH7110_SYSCLK_VOUT_TOP_AXI 62 73 + #define JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK 63 74 + #define JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF 64 75 + #define JH7110_SYSCLK_JPEGC_AXI 65 76 + #define JH7110_SYSCLK_CODAJ12_AXI 66 77 + #define JH7110_SYSCLK_CODAJ12_CORE 67 78 + #define JH7110_SYSCLK_CODAJ12_APB 68 79 + #define JH7110_SYSCLK_VDEC_AXI 69 80 + #define JH7110_SYSCLK_WAVE511_AXI 70 81 + #define JH7110_SYSCLK_WAVE511_BPU 71 82 + #define JH7110_SYSCLK_WAVE511_VCE 72 83 + #define JH7110_SYSCLK_WAVE511_APB 73 84 + #define JH7110_SYSCLK_VDEC_JPG 74 85 + #define JH7110_SYSCLK_VDEC_MAIN 75 86 + #define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76 87 + #define JH7110_SYSCLK_VENC_AXI 77 88 + #define JH7110_SYSCLK_WAVE420L_AXI 78 89 + #define JH7110_SYSCLK_WAVE420L_BPU 79 90 + #define JH7110_SYSCLK_WAVE420L_VCE 80 91 + #define JH7110_SYSCLK_WAVE420L_APB 81 92 + #define JH7110_SYSCLK_NOC_BUS_VENC_AXI 82 93 + #define JH7110_SYSCLK_AXI_CFG0_MAIN_DIV 83 94 + #define JH7110_SYSCLK_AXI_CFG0_MAIN 84 95 + #define JH7110_SYSCLK_AXI_CFG0_HIFI4 85 96 + #define JH7110_SYSCLK_AXIMEM2_AXI 86 97 + #define JH7110_SYSCLK_QSPI_AHB 87 98 + #define JH7110_SYSCLK_QSPI_APB 88 99 + #define JH7110_SYSCLK_QSPI_REF_SRC 89 100 + #define JH7110_SYSCLK_QSPI_REF 90 101 + #define JH7110_SYSCLK_SDIO0_AHB 91 102 + #define JH7110_SYSCLK_SDIO1_AHB 92 103 + #define JH7110_SYSCLK_SDIO0_SDCARD 93 104 + #define JH7110_SYSCLK_SDIO1_SDCARD 94 105 + #define JH7110_SYSCLK_USB_125M 95 106 + #define JH7110_SYSCLK_NOC_BUS_STG_AXI 96 107 + #define JH7110_SYSCLK_GMAC1_AHB 97 108 + #define JH7110_SYSCLK_GMAC1_AXI 98 109 + #define JH7110_SYSCLK_GMAC_SRC 99 110 + #define JH7110_SYSCLK_GMAC1_GTXCLK 100 111 + #define JH7110_SYSCLK_GMAC1_RMII_RTX 101 112 + #define JH7110_SYSCLK_GMAC1_PTP 102 113 + #define JH7110_SYSCLK_GMAC1_RX 103 114 + #define JH7110_SYSCLK_GMAC1_RX_INV 104 115 + #define JH7110_SYSCLK_GMAC1_TX 105 116 + #define JH7110_SYSCLK_GMAC1_TX_INV 106 117 + #define JH7110_SYSCLK_GMAC1_GTXC 107 118 + #define JH7110_SYSCLK_GMAC0_GTXCLK 108 119 + #define JH7110_SYSCLK_GMAC0_PTP 109 120 + #define JH7110_SYSCLK_GMAC_PHY 110 121 + #define JH7110_SYSCLK_GMAC0_GTXC 111 122 + #define JH7110_SYSCLK_IOMUX_APB 112 123 + #define JH7110_SYSCLK_MAILBOX_APB 113 124 + #define JH7110_SYSCLK_INT_CTRL_APB 114 125 + #define JH7110_SYSCLK_CAN0_APB 115 126 + #define JH7110_SYSCLK_CAN0_TIMER 116 127 + #define JH7110_SYSCLK_CAN0_CAN 117 128 + #define JH7110_SYSCLK_CAN1_APB 118 129 + #define JH7110_SYSCLK_CAN1_TIMER 119 130 + #define JH7110_SYSCLK_CAN1_CAN 120 131 + #define JH7110_SYSCLK_PWM_APB 121 132 + #define JH7110_SYSCLK_WDT_APB 122 133 + #define JH7110_SYSCLK_WDT_CORE 123 134 + #define JH7110_SYSCLK_TIMER_APB 124 135 + #define JH7110_SYSCLK_TIMER0 125 136 + #define JH7110_SYSCLK_TIMER1 126 137 + #define JH7110_SYSCLK_TIMER2 127 138 + #define JH7110_SYSCLK_TIMER3 128 139 + #define JH7110_SYSCLK_TEMP_APB 129 140 + #define JH7110_SYSCLK_TEMP_CORE 130 141 + #define JH7110_SYSCLK_SPI0_APB 131 142 + #define JH7110_SYSCLK_SPI1_APB 132 143 + #define JH7110_SYSCLK_SPI2_APB 133 144 + #define JH7110_SYSCLK_SPI3_APB 134 145 + #define JH7110_SYSCLK_SPI4_APB 135 146 + #define JH7110_SYSCLK_SPI5_APB 136 147 + #define JH7110_SYSCLK_SPI6_APB 137 148 + #define JH7110_SYSCLK_I2C0_APB 138 149 + #define JH7110_SYSCLK_I2C1_APB 139 150 + #define JH7110_SYSCLK_I2C2_APB 140 151 + #define JH7110_SYSCLK_I2C3_APB 141 152 + #define JH7110_SYSCLK_I2C4_APB 142 153 + #define JH7110_SYSCLK_I2C5_APB 143 154 + #define JH7110_SYSCLK_I2C6_APB 144 155 + #define JH7110_SYSCLK_UART0_APB 145 156 + #define JH7110_SYSCLK_UART0_CORE 146 157 + #define JH7110_SYSCLK_UART1_APB 147 158 + #define JH7110_SYSCLK_UART1_CORE 148 159 + #define JH7110_SYSCLK_UART2_APB 149 160 + #define JH7110_SYSCLK_UART2_CORE 150 161 + #define JH7110_SYSCLK_UART3_APB 151 162 + #define JH7110_SYSCLK_UART3_CORE 152 163 + #define JH7110_SYSCLK_UART4_APB 153 164 + #define JH7110_SYSCLK_UART4_CORE 154 165 + #define JH7110_SYSCLK_UART5_APB 155 166 + #define JH7110_SYSCLK_UART5_CORE 156 167 + #define JH7110_SYSCLK_PWMDAC_APB 157 168 + #define JH7110_SYSCLK_PWMDAC_CORE 158 169 + #define JH7110_SYSCLK_SPDIF_APB 159 170 + #define JH7110_SYSCLK_SPDIF_CORE 160 171 + #define JH7110_SYSCLK_I2STX0_APB 161 172 + #define JH7110_SYSCLK_I2STX0_BCLK_MST 162 173 + #define JH7110_SYSCLK_I2STX0_BCLK_MST_INV 163 174 + #define JH7110_SYSCLK_I2STX0_LRCK_MST 164 175 + #define JH7110_SYSCLK_I2STX0_BCLK 165 176 + #define JH7110_SYSCLK_I2STX0_BCLK_INV 166 177 + #define JH7110_SYSCLK_I2STX0_LRCK 167 178 + #define JH7110_SYSCLK_I2STX1_APB 168 179 + #define JH7110_SYSCLK_I2STX1_BCLK_MST 169 180 + #define JH7110_SYSCLK_I2STX1_BCLK_MST_INV 170 181 + #define JH7110_SYSCLK_I2STX1_LRCK_MST 171 182 + #define JH7110_SYSCLK_I2STX1_BCLK 172 183 + #define JH7110_SYSCLK_I2STX1_BCLK_INV 173 184 + #define JH7110_SYSCLK_I2STX1_LRCK 174 185 + #define JH7110_SYSCLK_I2SRX_APB 175 186 + #define JH7110_SYSCLK_I2SRX_BCLK_MST 176 187 + #define JH7110_SYSCLK_I2SRX_BCLK_MST_INV 177 188 + #define JH7110_SYSCLK_I2SRX_LRCK_MST 178 189 + #define JH7110_SYSCLK_I2SRX_BCLK 179 190 + #define JH7110_SYSCLK_I2SRX_BCLK_INV 180 191 + #define JH7110_SYSCLK_I2SRX_LRCK 181 192 + #define JH7110_SYSCLK_PDM_DMIC 182 193 + #define JH7110_SYSCLK_PDM_APB 183 194 + #define JH7110_SYSCLK_TDM_AHB 184 195 + #define JH7110_SYSCLK_TDM_APB 185 196 + #define JH7110_SYSCLK_TDM_INTERNAL 186 197 + #define JH7110_SYSCLK_TDM_TDM 187 198 + #define JH7110_SYSCLK_TDM_TDM_INV 188 199 + #define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189 200 + 201 + #define JH7110_SYSCLK_END 190 202 + 203 + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */

+142

include/dt-bindings/reset/starfive,jh7110-crg.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 2 + /* 3 + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk> 4 + */ 5 + 6 + #ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ 7 + #define __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ 8 + 9 + /* SYSCRG resets */ 10 + #define JH7110_SYSRST_JTAG_APB 0 11 + #define JH7110_SYSRST_SYSCON_APB 1 12 + #define JH7110_SYSRST_IOMUX_APB 2 13 + #define JH7110_SYSRST_BUS 3 14 + #define JH7110_SYSRST_DEBUG 4 15 + #define JH7110_SYSRST_CORE0 5 16 + #define JH7110_SYSRST_CORE1 6 17 + #define JH7110_SYSRST_CORE2 7 18 + #define JH7110_SYSRST_CORE3 8 19 + #define JH7110_SYSRST_CORE4 9 20 + #define JH7110_SYSRST_CORE0_ST 10 21 + #define JH7110_SYSRST_CORE1_ST 11 22 + #define JH7110_SYSRST_CORE2_ST 12 23 + #define JH7110_SYSRST_CORE3_ST 13 24 + #define JH7110_SYSRST_CORE4_ST 14 25 + #define JH7110_SYSRST_TRACE0 15 26 + #define JH7110_SYSRST_TRACE1 16 27 + #define JH7110_SYSRST_TRACE2 17 28 + #define JH7110_SYSRST_TRACE3 18 29 + #define JH7110_SYSRST_TRACE4 19 30 + #define JH7110_SYSRST_TRACE_COM 20 31 + #define JH7110_SYSRST_GPU_APB 21 32 + #define JH7110_SYSRST_GPU_DOMA 22 33 + #define JH7110_SYSRST_NOC_BUS_APB 23 34 + #define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 24 35 + #define JH7110_SYSRST_NOC_BUS_CPU_AXI 25 36 + #define JH7110_SYSRST_NOC_BUS_DISP_AXI 26 37 + #define JH7110_SYSRST_NOC_BUS_GPU_AXI 27 38 + #define JH7110_SYSRST_NOC_BUS_ISP_AXI 28 39 + #define JH7110_SYSRST_NOC_BUS_DDRC 29 40 + #define JH7110_SYSRST_NOC_BUS_STG_AXI 30 41 + #define JH7110_SYSRST_NOC_BUS_VDEC_AXI 31 42 + 43 + #define JH7110_SYSRST_NOC_BUS_VENC_AXI 32 44 + #define JH7110_SYSRST_AXI_CFG1_AHB 33 45 + #define JH7110_SYSRST_AXI_CFG1_MAIN 34 46 + #define JH7110_SYSRST_AXI_CFG0_MAIN 35 47 + #define JH7110_SYSRST_AXI_CFG0_MAIN_DIV 36 48 + #define JH7110_SYSRST_AXI_CFG0_HIFI4 37 49 + #define JH7110_SYSRST_DDR_AXI 38 50 + #define JH7110_SYSRST_DDR_OSC 39 51 + #define JH7110_SYSRST_DDR_APB 40 52 + #define JH7110_SYSRST_ISP_TOP 41 53 + #define JH7110_SYSRST_ISP_TOP_AXI 42 54 + #define JH7110_SYSRST_VOUT_TOP_SRC 43 55 + #define JH7110_SYSRST_CODAJ12_AXI 44 56 + #define JH7110_SYSRST_CODAJ12_CORE 45 57 + #define JH7110_SYSRST_CODAJ12_APB 46 58 + #define JH7110_SYSRST_WAVE511_AXI 47 59 + #define JH7110_SYSRST_WAVE511_BPU 48 60 + #define JH7110_SYSRST_WAVE511_VCE 49 61 + #define JH7110_SYSRST_WAVE511_APB 50 62 + #define JH7110_SYSRST_VDEC_JPG 51 63 + #define JH7110_SYSRST_VDEC_MAIN 52 64 + #define JH7110_SYSRST_AXIMEM0_AXI 53 65 + #define JH7110_SYSRST_WAVE420L_AXI 54 66 + #define JH7110_SYSRST_WAVE420L_BPU 55 67 + #define JH7110_SYSRST_WAVE420L_VCE 56 68 + #define JH7110_SYSRST_WAVE420L_APB 57 69 + #define JH7110_SYSRST_AXIMEM1_AXI 58 70 + #define JH7110_SYSRST_AXIMEM2_AXI 59 71 + #define JH7110_SYSRST_INTMEM 60 72 + #define JH7110_SYSRST_QSPI_AHB 61 73 + #define JH7110_SYSRST_QSPI_APB 62 74 + #define JH7110_SYSRST_QSPI_REF 63 75 + 76 + #define JH7110_SYSRST_SDIO0_AHB 64 77 + #define JH7110_SYSRST_SDIO1_AHB 65 78 + #define JH7110_SYSRST_GMAC1_AXI 66 79 + #define JH7110_SYSRST_GMAC1_AHB 67 80 + #define JH7110_SYSRST_MAILBOX_APB 68 81 + #define JH7110_SYSRST_SPI0_APB 69 82 + #define JH7110_SYSRST_SPI1_APB 70 83 + #define JH7110_SYSRST_SPI2_APB 71 84 + #define JH7110_SYSRST_SPI3_APB 72 85 + #define JH7110_SYSRST_SPI4_APB 73 86 + #define JH7110_SYSRST_SPI5_APB 74 87 + #define JH7110_SYSRST_SPI6_APB 75 88 + #define JH7110_SYSRST_I2C0_APB 76 89 + #define JH7110_SYSRST_I2C1_APB 77 90 + #define JH7110_SYSRST_I2C2_APB 78 91 + #define JH7110_SYSRST_I2C3_APB 79 92 + #define JH7110_SYSRST_I2C4_APB 80 93 + #define JH7110_SYSRST_I2C5_APB 81 94 + #define JH7110_SYSRST_I2C6_APB 82 95 + #define JH7110_SYSRST_UART0_APB 83 96 + #define JH7110_SYSRST_UART0_CORE 84 97 + #define JH7110_SYSRST_UART1_APB 85 98 + #define JH7110_SYSRST_UART1_CORE 86 99 + #define JH7110_SYSRST_UART2_APB 87 100 + #define JH7110_SYSRST_UART2_CORE 88 101 + #define JH7110_SYSRST_UART3_APB 89 102 + #define JH7110_SYSRST_UART3_CORE 90 103 + #define JH7110_SYSRST_UART4_APB 91 104 + #define JH7110_SYSRST_UART4_CORE 92 105 + #define JH7110_SYSRST_UART5_APB 93 106 + #define JH7110_SYSRST_UART5_CORE 94 107 + #define JH7110_SYSRST_SPDIF_APB 95 108 + 109 + #define JH7110_SYSRST_PWMDAC_APB 96 110 + #define JH7110_SYSRST_PDM_DMIC 97 111 + #define JH7110_SYSRST_PDM_APB 98 112 + #define JH7110_SYSRST_I2SRX_APB 99 113 + #define JH7110_SYSRST_I2SRX_BCLK 100 114 + #define JH7110_SYSRST_I2STX0_APB 101 115 + #define JH7110_SYSRST_I2STX0_BCLK 102 116 + #define JH7110_SYSRST_I2STX1_APB 103 117 + #define JH7110_SYSRST_I2STX1_BCLK 104 118 + #define JH7110_SYSRST_TDM_AHB 105 119 + #define JH7110_SYSRST_TDM_CORE 106 120 + #define JH7110_SYSRST_TDM_APB 107 121 + #define JH7110_SYSRST_PWM_APB 108 122 + #define JH7110_SYSRST_WDT_APB 109 123 + #define JH7110_SYSRST_WDT_CORE 110 124 + #define JH7110_SYSRST_CAN0_APB 111 125 + #define JH7110_SYSRST_CAN0_CORE 112 126 + #define JH7110_SYSRST_CAN0_TIMER 113 127 + #define JH7110_SYSRST_CAN1_APB 114 128 + #define JH7110_SYSRST_CAN1_CORE 115 129 + #define JH7110_SYSRST_CAN1_TIMER 116 130 + #define JH7110_SYSRST_TIMER_APB 117 131 + #define JH7110_SYSRST_TIMER0 118 132 + #define JH7110_SYSRST_TIMER1 119 133 + #define JH7110_SYSRST_TIMER2 120 134 + #define JH7110_SYSRST_TIMER3 121 135 + #define JH7110_SYSRST_INT_CTRL_APB 122 136 + #define JH7110_SYSRST_TEMP_APB 123 137 + #define JH7110_SYSRST_TEMP_CORE 124 138 + #define JH7110_SYSRST_JTAG_CERTIFICATION 125 139 + 140 + #define JH7110_SYSRST_END 126 141 + 142 + #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */