commit 7f74c2c7f760fdd44116e3dd90a5aeeb9d9333c7 · tjh.dev/kernel

+7 -7

arch/arm/mach-orion/addr-map.c

··· 265 265 } 266 266 267 267 /* 268 - * Setup windows for PCI+PCIE IO+MAM space 268 + * Setup windows for PCI+PCIe IO+MEM space. 269 269 */ 270 - orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_BASE, 271 - ORION_PCIE_IO_SIZE, ORION_PCIE_IO_REMAP); 272 - orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_BASE, 273 - ORION_PCI_IO_SIZE, ORION_PCI_IO_REMAP); 274 - orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_BASE, 270 + orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_PHYS_BASE, 271 + ORION_PCIE_IO_SIZE, ORION_PCIE_IO_BUS_BASE); 272 + orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_PHYS_BASE, 273 + ORION_PCI_IO_SIZE, ORION_PCI_IO_BUS_BASE); 274 + orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_PHYS_BASE, 275 275 ORION_PCIE_MEM_SIZE, -1); 276 - orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_BASE, 276 + orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_PHYS_BASE, 277 277 ORION_PCI_MEM_SIZE, -1); 278 278 } 279 279

+26 -26

arch/arm/mach-orion/common.c

··· 27 27 ****************************************************************************/ 28 28 static struct map_desc orion_io_desc[] __initdata = { 29 29 { 30 - .virtual = ORION_REGS_BASE, 31 - .pfn = __phys_to_pfn(ORION_REGS_BASE), 30 + .virtual = ORION_REGS_VIRT_BASE, 31 + .pfn = __phys_to_pfn(ORION_REGS_PHYS_BASE), 32 32 .length = ORION_REGS_SIZE, 33 33 .type = MT_DEVICE 34 34 }, 35 35 { 36 - .virtual = ORION_PCIE_IO_BASE, 37 - .pfn = __phys_to_pfn(ORION_PCIE_IO_BASE), 36 + .virtual = ORION_PCIE_IO_VIRT_BASE, 37 + .pfn = __phys_to_pfn(ORION_PCIE_IO_PHYS_BASE), 38 38 .length = ORION_PCIE_IO_SIZE, 39 39 .type = MT_DEVICE 40 40 }, 41 41 { 42 - .virtual = ORION_PCI_IO_BASE, 43 - .pfn = __phys_to_pfn(ORION_PCI_IO_BASE), 42 + .virtual = ORION_PCI_IO_VIRT_BASE, 43 + .pfn = __phys_to_pfn(ORION_PCI_IO_PHYS_BASE), 44 44 .length = ORION_PCI_IO_SIZE, 45 45 .type = MT_DEVICE 46 46 }, 47 47 { 48 - .virtual = ORION_PCIE_WA_BASE, 49 - .pfn = __phys_to_pfn(ORION_PCIE_WA_BASE), 48 + .virtual = ORION_PCIE_WA_VIRT_BASE, 49 + .pfn = __phys_to_pfn(ORION_PCIE_WA_PHYS_BASE), 50 50 .length = ORION_PCIE_WA_SIZE, 51 51 .type = MT_DEVICE 52 52 }, ··· 63 63 64 64 static struct resource orion_uart_resources[] = { 65 65 { 66 - .start = UART0_BASE, 67 - .end = UART0_BASE + 0xff, 66 + .start = UART0_PHYS_BASE, 67 + .end = UART0_PHYS_BASE + 0xff, 68 68 .flags = IORESOURCE_MEM, 69 69 }, 70 70 { ··· 73 73 .flags = IORESOURCE_IRQ, 74 74 }, 75 75 { 76 - .start = UART1_BASE, 77 - .end = UART1_BASE + 0xff, 76 + .start = UART1_PHYS_BASE, 77 + .end = UART1_PHYS_BASE + 0xff, 78 78 .flags = IORESOURCE_MEM, 79 79 }, 80 80 { ··· 86 86 87 87 static struct plat_serial8250_port orion_uart_data[] = { 88 88 { 89 - .mapbase = UART0_BASE, 90 - .membase = (char *)UART0_BASE, 89 + .mapbase = UART0_PHYS_BASE, 90 + .membase = (char *)UART0_VIRT_BASE, 91 91 .irq = IRQ_ORION_UART0, 92 92 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, 93 93 .iotype = UPIO_MEM, ··· 95 95 .uartclk = ORION_TCLK, 96 96 }, 97 97 { 98 - .mapbase = UART1_BASE, 99 - .membase = (char *)UART1_BASE, 98 + .mapbase = UART1_PHYS_BASE, 99 + .membase = (char *)UART1_VIRT_BASE, 100 100 .irq = IRQ_ORION_UART1, 101 101 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, 102 102 .iotype = UPIO_MEM, ··· 122 122 123 123 static struct resource orion_ehci0_resources[] = { 124 124 { 125 - .start = ORION_USB0_REG_BASE, 126 - .end = ORION_USB0_REG_BASE + SZ_4K, 125 + .start = ORION_USB0_PHYS_BASE, 126 + .end = ORION_USB0_PHYS_BASE + SZ_4K, 127 127 .flags = IORESOURCE_MEM, 128 128 }, 129 129 { ··· 135 135 136 136 static struct resource orion_ehci1_resources[] = { 137 137 { 138 - .start = ORION_USB1_REG_BASE, 139 - .end = ORION_USB1_REG_BASE + SZ_4K, 138 + .start = ORION_USB1_PHYS_BASE, 139 + .end = ORION_USB1_PHYS_BASE + SZ_4K, 140 140 .flags = IORESOURCE_MEM, 141 141 }, 142 142 { ··· 177 177 178 178 static struct resource orion_eth_shared_resources[] = { 179 179 { 180 - .start = ORION_ETH_REG_BASE, 181 - .end = ORION_ETH_REG_BASE + 0xffff, 180 + .start = ORION_ETH_PHYS_BASE, 181 + .end = ORION_ETH_PHYS_BASE + 0xffff, 182 182 .flags = IORESOURCE_MEM, 183 183 }, 184 184 }; ··· 227 227 static struct resource orion_i2c_resources[] = { 228 228 { 229 229 .name = "i2c base", 230 - .start = I2C_BASE, 231 - .end = I2C_BASE + 0x20 -1, 230 + .start = I2C_PHYS_BASE, 231 + .end = I2C_PHYS_BASE + 0x20 -1, 232 232 .flags = IORESOURCE_MEM, 233 233 }, 234 234 { ··· 255 255 static struct resource orion_sata_resources[] = { 256 256 { 257 257 .name = "sata base", 258 - .start = ORION_SATA_REG_BASE, 259 - .end = ORION_SATA_REG_BASE + 0x5000 - 1, 258 + .start = ORION_SATA_PHYS_BASE, 259 + .end = ORION_SATA_PHYS_BASE + 0x5000 - 1, 260 260 .flags = IORESOURCE_MEM, 261 261 }, 262 262 {

+2 -2

arch/arm/mach-orion/db88f5281-setup.c

··· 354 354 355 355 MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board") 356 356 /* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */ 357 - .phys_io = ORION_REGS_BASE, 358 - .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xfffc, 357 + .phys_io = ORION_REGS_PHYS_BASE, 358 + .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xfffc, 359 359 .boot_params = 0x00000100, 360 360 .init_machine = db88f5281_init, 361 361 .map_io = orion_map_io,

+4 -4

arch/arm/mach-orion/dns323-setup.c

··· 259 259 * 260 260 * Open a special address decode windows for the PCIE WA. 261 261 */ 262 - orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE); 263 - orion_write(ORION_REGS_BASE | 0x20070, 262 + orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); 263 + orion_write(ORION_REGS_VIRT_BASE | 0x20070, 264 264 (0x7941 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); 265 265 266 266 /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */ ··· 312 312 /* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */ 313 313 MACHINE_START(DNS323, "D-Link DNS-323") 314 314 /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */ 315 - .phys_io = ORION_REGS_BASE, 316 - .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC, 315 + .phys_io = ORION_REGS_PHYS_BASE, 316 + .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, 317 317 .boot_params = 0x00000100, 318 318 .init_machine = dns323_init, 319 319 .map_io = orion_map_io,

+4 -4

arch/arm/mach-orion/kurobox_pro-setup.c

··· 192 192 /* 193 193 * Open a special address decode windows for the PCIE WA. 194 194 */ 195 - orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE); 196 - orion_write(ORION_REGS_BASE | 0x20070, (0x7941 | 195 + orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); 196 + orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 | 197 197 (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); 198 198 199 199 /* ··· 224 224 225 225 MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro") 226 226 /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */ 227 - .phys_io = ORION_REGS_BASE, 228 - .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC, 227 + .phys_io = ORION_REGS_PHYS_BASE, 228 + .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, 229 229 .boot_params = 0x00000100, 230 230 .init_machine = kurobox_pro_init, 231 231 .map_io = orion_map_io,

+5 -5

arch/arm/mach-orion/pci.c

··· 156 156 orion_pcie_id(&dev, &rev); 157 157 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { 158 158 /* extended register space */ 159 - pcie_addr = ORION_PCIE_WA_BASE; 159 + pcie_addr = ORION_PCIE_WA_VIRT_BASE; 160 160 pcie_addr |= PCIE_CONF_BUS(bus->number) | 161 161 PCIE_CONF_DEV(PCI_SLOT(devfn)) | 162 162 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | ··· 241 241 */ 242 242 res[0].name = "PCI-EX I/O Space"; 243 243 res[0].flags = IORESOURCE_IO; 244 - res[0].start = ORION_PCIE_IO_REMAP; 244 + res[0].start = ORION_PCIE_IO_BUS_BASE; 245 245 res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1; 246 246 if (request_resource(&ioport_resource, &res[0])) 247 247 panic("Request PCIE IO resource failed\n"); ··· 252 252 */ 253 253 res[1].name = "PCI-EX Memory Space"; 254 254 res[1].flags = IORESOURCE_MEM; 255 - res[1].start = ORION_PCIE_MEM_BASE; 255 + res[1].start = ORION_PCIE_MEM_PHYS_BASE; 256 256 res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1; 257 257 if (request_resource(&iomem_resource, &res[1])) 258 258 panic("Request PCIE Memory resource failed\n"); ··· 477 477 */ 478 478 res[0].name = "PCI I/O Space"; 479 479 res[0].flags = IORESOURCE_IO; 480 - res[0].start = ORION_PCI_IO_REMAP; 480 + res[0].start = ORION_PCI_IO_BUS_BASE; 481 481 res[0].end = res[0].start + ORION_PCI_IO_SIZE - 1; 482 482 if (request_resource(&ioport_resource, &res[0])) 483 483 panic("Request PCI IO resource failed\n"); ··· 488 488 */ 489 489 res[1].name = "PCI Memory Space"; 490 490 res[1].flags = IORESOURCE_MEM; 491 - res[1].start = ORION_PCI_MEM_BASE; 491 + res[1].start = ORION_PCI_MEM_PHYS_BASE; 492 492 res[1].end = res[1].start + ORION_PCI_MEM_SIZE - 1; 493 493 if (request_resource(&iomem_resource, &res[1])) 494 494 panic("Request PCI Memory resource failed\n");

+4 -4

arch/arm/mach-orion/rd88f5182-setup.c

··· 263 263 /* 264 264 * Open a special address decode windows for the PCIE WA. 265 265 */ 266 - orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE); 267 - orion_write(ORION_REGS_BASE | 0x20070, (0x7941 | 266 + orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); 267 + orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 | 268 268 (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); 269 269 270 270 /* ··· 305 305 306 306 MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design") 307 307 /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */ 308 - .phys_io = ORION_REGS_BASE, 309 - .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC, 308 + .phys_io = ORION_REGS_PHYS_BASE, 309 + .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, 310 310 .boot_params = 0x00000100, 311 311 .init_machine = rd88f5182_init, 312 312 .map_io = orion_map_io,

+5 -5

arch/arm/mach-orion/ts209-setup.c

··· 244 244 * QNAP TS-[12]09 specific power off method via UART1-attached PIC 245 245 */ 246 246 247 - #define UART1_REG(x) (UART1_BASE + ((UART_##x) << 2)) 247 + #define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2)) 248 248 249 249 static void qnap_ts209_power_off(void) 250 250 { ··· 282 282 /* 283 283 * Open a special address decode windows for the PCIE WA. 284 284 */ 285 - orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE); 286 - orion_write(ORION_REGS_BASE | 0x20070, (0x7941 | 285 + orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); 286 + orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 | 287 287 (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); 288 288 289 289 /* ··· 325 325 326 326 MACHINE_START(TS209, "QNAP TS-109/TS-209") 327 327 /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */ 328 - .phys_io = ORION_REGS_BASE, 329 - .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC, 328 + .phys_io = ORION_REGS_PHYS_BASE, 329 + .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, 330 330 .boot_params = 0x00000100, 331 331 .init_machine = qnap_ts209_init, 332 332 .map_io = orion_map_io,

+7 -2

include/asm-arm/arch-orion/debug-macro.S

··· 8 8 * published by the Free Software Foundation. 9 9 */ 10 10 11 + #include <asm/arch/orion.h> 12 + 11 13 .macro addruart,rx 12 - mov \rx, #0xf1000000 13 - orr \rx, \rx, #0x00012000 14 + mrc p15, 0, \rx, c1, c0 15 + tst \rx, #1 @ MMU enabled? 16 + ldreq \rx, =ORION_REGS_PHYS_BASE 17 + ldrne \rx, =ORION_REGS_VIRT_BASE 18 + orr \rx, \rx, #0x00012000 14 19 .endm 15 20 16 21 #define UART_SHIFT 2

+2 -2

include/asm-arm/arch-orion/entry-macro.S

··· 3 3 * 4 4 * Low-level IRQ helper macros for Orion platforms 5 5 * 6 - * This file is licensed under the terms of the GNU General Public 7 - * License version 2. This program is licensed "as is" without any 6 + * This file is licensed under the terms of the GNU General Public 7 + * License version 2. This program is licensed "as is" without any 8 8 * warranty of any kind, whether express or implied. 9 9 */ 10 10

+5 -8

include/asm-arm/arch-orion/hardware.h

··· 4 4 * This program is free software; you can redistribute it and/or modify 5 5 * it under the terms of the GNU General Public License version 2 as 6 6 * published by the Free Software Foundation. 7 - * 8 7 */ 9 8 10 9 #ifndef __ASM_ARCH_HARDWARE_H__ ··· 11 12 12 13 #include "orion.h" 13 14 14 - #define PCI_MEMORY_VADDR ORION_PCI_SYS_MEM_BASE 15 - #define PCI_IO_VADDR ORION_PCI_SYS_IO_BASE 15 + #define pcibios_assign_all_busses() 1 16 16 17 - #define pcibios_assign_all_busses() 1 17 + #define PCIBIOS_MIN_IO 0x00001000 18 + #define PCIBIOS_MIN_MEM 0x01000000 19 + #define PCIMEM_BASE ORION_PCIE_MEM_PHYS_BASE 18 20 19 - #define PCIBIOS_MIN_IO 0x1000 20 - #define PCIBIOS_MIN_MEM 0x01000000 21 - #define PCIMEM_BASE PCI_MEMORY_VADDR /* mem base for VGA */ 22 21 23 - #endif /* _ASM_ARCH_HARDWARE_H */ 22 + #endif

+61 -39

include/asm-arm/arch-orion/orion.h

··· 14 14 #ifndef __ASM_ARCH_ORION_H__ 15 15 #define __ASM_ARCH_ORION_H__ 16 16 17 - /******************************************************************************* 17 + /***************************************************************************** 18 18 * Orion Address Map 19 - * Use the same mapping (1:1 virtual:physical) of internal registers and 20 - * PCI system (PCI+PCIE) for all machines. 21 - * Each machine defines the rest of its mapping (e.g. device bus flashes) 22 - ******************************************************************************/ 23 - #define ORION_REGS_BASE 0xf1000000 19 + * 20 + * virt phys size 21 + * f0000000 f0000000 16M PCIe WA space (Orion-NAS only) 22 + * f1000000 f1000000 1M on-chip peripheral registers 23 + * f2000000 f2000000 1M PCIe I/O space 24 + * f2100000 f2100000 1M PCI I/O space 25 + ****************************************************************************/ 26 + #define ORION_REGS_PHYS_BASE 0xf1000000 27 + #define ORION_REGS_VIRT_BASE 0xf1000000 24 28 #define ORION_REGS_SIZE SZ_1M 25 29 26 - #define ORION_PCI_SYS_MEM_BASE 0xe0000000 27 - #define ORION_PCIE_MEM_BASE ORION_PCI_SYS_MEM_BASE 28 - #define ORION_PCIE_MEM_SIZE SZ_128M 29 - #define ORION_PCI_MEM_BASE (ORION_PCIE_MEM_BASE + ORION_PCIE_MEM_SIZE) 30 - #define ORION_PCI_MEM_SIZE SZ_128M 31 - 32 - #define ORION_PCI_SYS_IO_BASE 0xf2000000 33 - #define ORION_PCIE_IO_BASE ORION_PCI_SYS_IO_BASE 30 + #define ORION_PCIE_IO_PHYS_BASE 0xf2000000 31 + #define ORION_PCIE_IO_VIRT_BASE 0xf2000000 32 + #define ORION_PCIE_IO_BUS_BASE 0x00000000 34 33 #define ORION_PCIE_IO_SIZE SZ_1M 35 - #define ORION_PCIE_IO_REMAP (ORION_PCIE_IO_BASE - ORION_PCI_SYS_IO_BASE) 36 - #define ORION_PCI_IO_BASE (ORION_PCIE_IO_BASE + ORION_PCIE_IO_SIZE) 34 + 35 + #define ORION_PCI_IO_PHYS_BASE 0xf2100000 36 + #define ORION_PCI_IO_VIRT_BASE 0xf2100000 37 + #define ORION_PCI_IO_BUS_BASE 0x00100000 37 38 #define ORION_PCI_IO_SIZE SZ_1M 38 - #define ORION_PCI_IO_REMAP (ORION_PCI_IO_BASE - ORION_PCI_SYS_IO_BASE) 39 + 39 40 /* Relevant only for Orion-NAS */ 40 - #define ORION_PCIE_WA_BASE 0xf0000000 41 + #define ORION_PCIE_WA_PHYS_BASE 0xf0000000 42 + #define ORION_PCIE_WA_VIRT_BASE 0xf0000000 41 43 #define ORION_PCIE_WA_SIZE SZ_16M 44 + 45 + #define ORION_PCIE_MEM_PHYS_BASE 0xe0000000 46 + #define ORION_PCIE_MEM_SIZE SZ_128M 47 + 48 + #define ORION_PCI_MEM_PHYS_BASE 0xe8000000 49 + #define ORION_PCI_MEM_SIZE SZ_128M 42 50 43 51 /******************************************************************************* 44 52 * Supported Devices & Revisions ··· 65 57 /******************************************************************************* 66 58 * Orion Registers Map 67 59 ******************************************************************************/ 68 - #define ORION_DDR_REG_BASE (ORION_REGS_BASE | 0x00000) 69 - #define ORION_DEV_BUS_REG_BASE (ORION_REGS_BASE | 0x10000) 70 - #define ORION_BRIDGE_REG_BASE (ORION_REGS_BASE | 0x20000) 71 - #define ORION_PCI_REG_BASE (ORION_REGS_BASE | 0x30000) 72 - #define ORION_PCIE_REG_BASE (ORION_REGS_BASE | 0x40000) 73 - #define ORION_USB0_REG_BASE (ORION_REGS_BASE | 0x50000) 74 - #define ORION_ETH_REG_BASE (ORION_REGS_BASE | 0x70000) 75 - #define ORION_SATA_REG_BASE (ORION_REGS_BASE | 0x80000) 76 - #define ORION_USB1_REG_BASE (ORION_REGS_BASE | 0xa0000) 60 + #define ORION_DDR_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x00000) 61 + #define ORION_DDR_REG(x) (ORION_DDR_VIRT_BASE | (x)) 77 62 78 - #define ORION_DDR_REG(x) (ORION_DDR_REG_BASE | (x)) 79 - #define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_REG_BASE | (x)) 80 - #define ORION_BRIDGE_REG(x) (ORION_BRIDGE_REG_BASE | (x)) 81 - #define ORION_PCI_REG(x) (ORION_PCI_REG_BASE | (x)) 82 - #define ORION_PCIE_REG(x) (ORION_PCIE_REG_BASE | (x)) 83 - #define ORION_USB0_REG(x) (ORION_USB0_REG_BASE | (x)) 84 - #define ORION_USB1_REG(x) (ORION_USB1_REG_BASE | (x)) 85 - #define ORION_ETH_REG(x) (ORION_ETH_REG_BASE | (x)) 86 - #define ORION_SATA_REG(x) (ORION_SATA_REG_BASE | (x)) 63 + #define ORION_DEV_BUS_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x10000) 64 + #define ORION_DEV_BUS_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x10000) 65 + #define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_VIRT_BASE | (x)) 66 + #define I2C_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x1000) 67 + #define UART0_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2000) 68 + #define UART0_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2000) 69 + #define UART1_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2100) 70 + #define UART1_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2100) 71 + 72 + #define ORION_BRIDGE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x20000) 73 + #define ORION_BRIDGE_REG(x) (ORION_BRIDGE_VIRT_BASE | (x)) 74 + 75 + #define ORION_PCI_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x30000) 76 + #define ORION_PCI_REG(x) (ORION_PCI_VIRT_BASE | (x)) 77 + 78 + #define ORION_PCIE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x40000) 79 + #define ORION_PCIE_REG(x) (ORION_PCIE_VIRT_BASE | (x)) 80 + 81 + #define ORION_USB0_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x50000) 82 + #define ORION_USB0_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x50000) 83 + #define ORION_USB0_REG(x) (ORION_USB0_VIRT_BASE | (x)) 84 + 85 + #define ORION_ETH_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x70000) 86 + #define ORION_ETH_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x70000) 87 + #define ORION_ETH_REG(x) (ORION_ETH_VIRT_BASE | (x)) 88 + 89 + #define ORION_SATA_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x80000) 90 + #define ORION_SATA_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x80000) 91 + #define ORION_SATA_REG(x) (ORION_SATA_VIRT_BASE | (x)) 92 + 93 + #define ORION_USB1_PHYS_BASE (ORION_REGS_PHYS_BASE | 0xa0000) 94 + #define ORION_USB1_VIRT_BASE (ORION_REGS_VIRT_BASE | 0xa0000) 95 + #define ORION_USB1_REG(x) (ORION_USB1_VIRT_BASE | (x)) 87 96 88 97 /******************************************************************************* 89 98 * Device Bus Registers ··· 125 100 #define DEV_BUS_CTRL ORION_DEV_BUS_REG(0x4c0) 126 101 #define DEV_BUS_INT_CAUSE ORION_DEV_BUS_REG(0x4d0) 127 102 #define DEV_BUS_INT_MASK ORION_DEV_BUS_REG(0x4d4) 128 - #define I2C_BASE ORION_DEV_BUS_REG(0x1000) 129 - #define UART0_BASE ORION_DEV_BUS_REG(0x2000) 130 - #define UART1_BASE ORION_DEV_BUS_REG(0x2100) 131 103 #define GPIO_MAX 32 132 104 133 105 /***************************************************************************

+2 -2

include/asm-arm/arch-orion/uncompress.h

··· 10 10 11 11 #include <asm/arch/orion.h> 12 12 13 - #define MV_UART_LSR ((volatile unsigned char *)(UART0_BASE + 0x14)) 14 - #define MV_UART_THR ((volatile unsigned char *)(UART0_BASE + 0x0)) 13 + #define MV_UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0)) 14 + #define MV_UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14)) 15 15 16 16 #define LSR_THRE 0x20 17 17