tjh.dev
+1
-1
drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
+1
-1
drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
···
100
100
static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
101
101
unsigned long *prate)
102
102
{
103
-
return clamp_val(rate, 50000000, 1600000000);
103
+
return clamp_val(rate, 125000000, 1600000000);
104
104
}
105
105
106
106
static const struct clk_ops mtk_mipi_tx_pll_ops = {
+1
-1
drivers/phy/sunplus/phy-sunplus-usb2.c
+1
-1
drivers/phy/sunplus/phy-sunplus-usb2.c
+4
-1
drivers/phy/ti/phy-gmii-sel.c
+4
-1
drivers/phy/ti/phy-gmii-sel.c
···
64
64
u32 num_ports;
65
65
u32 reg_offset;
66
66
u32 qsgmii_main_ports;
67
+
bool no_offset;
67
68
};
68
69
69
70
static int phy_gmii_sel_mode(struct phy *phy, enum phy_mode mode, int submode)
···
403
402
priv->num_ports = size / sizeof(u32);
404
403
if (!priv->num_ports)
405
404
return -EINVAL;
406
-
priv->reg_offset = __be32_to_cpu(*offset);
405
+
if (!priv->no_offset)
406
+
priv->reg_offset = __be32_to_cpu(*offset);
407
407
}
408
408
409
409
if_phys = devm_kcalloc(dev, priv->num_ports,
···
473
471
dev_err(dev, "Failed to get syscon %d\n", ret);
474
472
return ret;
475
473
}
474
+
priv->no_offset = true;
476
475
}
477
476
478
477
ret = phy_gmii_sel_init_ports(priv);