dt-bindings: clk: sun5i: add DRAM gates compatible

The Allwinner SoCs have a gate controller to gate the access to the DRAM
clock to the some devices that need to access the DRAM directly (mostly
display / image related IPs).

Use a simple gates driver to support the one found in the A13 / R8 SoCs.

Signed-off-by: Maxime Ripard <[e-mail]>
Acked-by: Chen-Yu Tsai <[e-mail]>
Acked-by: Rob Herring <[e-mail]>
Acked-by: Stephen Boyd <[e-mail]>
Signed-off-by: Maxime Ripard <[e-mail]>

Documentation/devicetree/bindings/clock/sunxi.txt

···
 	"allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3
 	"allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80
 	"allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10
+	"allwinner,sun5i-a13-dram-gates-clk" - for the DRAM gates on A13
 	"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
 	"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
 	"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80