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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm: sti: fix delay in VTG programming
The HDMI path introduce a delay of 6 pixels.
This delay should be take into account while programming
VTG for the HDMI. Without this delay, the HDMI active
window area is shift of 6 pixel on the right.
Set also timing for DVO output.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
+28
-3
+28
-3
drivers/gpu/drm/sti/sti_vtg.c
+28
-3
drivers/gpu/drm/sti/sti_vtg.c
···
51
51
#define VTG_TOP_V_HD_3 0x010C
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#define VTG_BOT_V_HD_3 0x0110
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+
#define VTG_H_HD_4 0x0120
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+
#define VTG_TOP_V_VD_4 0x0124
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+
#define VTG_BOT_V_VD_4 0x0128
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+
#define VTG_TOP_V_HD_4 0x012c
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+
#define VTG_BOT_V_HD_4 0x0130
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+
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#define VTG_IRQ_BOTTOM BIT(0)
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#define VTG_IRQ_TOP BIT(1)
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#define VTG_IRQ_MASK (VTG_IRQ_TOP | VTG_IRQ_BOTTOM)
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+
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+
/* Delay introduced by the HDMI in nb of pixel */
65
+
#define HDMI_DELAY (6)
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/* delay introduced by the Arbitrary Waveform Generator in nb of pixels */
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68
#define AWG_DELAY_HD (-9)
···
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133
writel(tmp, vtg->regs + VTG_VID_TFS);
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134
writel(tmp, vtg->regs + VTG_VID_BFS);
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135
145
-
/* prepare VTG set 1 and 2 for HDMI and VTG set 3 for HD DAC */
146
-
tmp = (mode->hsync_end - mode->hsync_start) << 16;
136
+
/* prepare VTG set 1 for HDMI */
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+
tmp = (mode->hsync_end - mode->hsync_start + HDMI_DELAY) << 16;
138
+
tmp |= HDMI_DELAY;
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writel(tmp, vtg->regs + VTG_H_HD_1);
148
-
writel(tmp, vtg->regs + VTG_H_HD_2);
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tmp = (mode->vsync_end - mode->vsync_start + 1) << 16;
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142
tmp |= 1;
···
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writel(0, vtg->regs + VTG_BOT_V_HD_1);
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/* prepare VTG set 2 for for HD DCS */
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+
tmp = (mode->hsync_end - mode->hsync_start) << 16;
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+
writel(tmp, vtg->regs + VTG_H_HD_2);
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+
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+
tmp = (mode->vsync_end - mode->vsync_start + 1) << 16;
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+
tmp |= 1;
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writel(tmp, vtg->regs + VTG_TOP_V_VD_2);
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writel(tmp, vtg->regs + VTG_BOT_V_VD_2);
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writel(0, vtg->regs + VTG_TOP_V_HD_2);
···
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165
tmp |= mode->htotal + AWG_DELAY_HD;
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writel(tmp, vtg->regs + VTG_TOP_V_HD_3);
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writel(tmp, vtg->regs + VTG_BOT_V_HD_3);
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+
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+
/* Prepare VTG set 4 for DVO */
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+
tmp = (mode->hsync_end - mode->hsync_start) << 16;
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+
writel(tmp, vtg->regs + VTG_H_HD_4);
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+
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+
tmp = (mode->vsync_end - mode->vsync_start + 1) << 16;
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+
tmp |= 1;
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+
writel(tmp, vtg->regs + VTG_TOP_V_VD_4);
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+
writel(tmp, vtg->regs + VTG_BOT_V_VD_4);
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+
writel(0, vtg->regs + VTG_TOP_V_HD_4);
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+
writel(0, vtg->regs + VTG_BOT_V_HD_4);
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/* mode */
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writel(type, vtg->regs + VTG_MODE);