tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm: meson: venc: use proper macros instead of magic constants

This patch add new macros which are used to set the following
registers:
- ENCI_CFILT_CTRL
- ENCI_CFILT_CTRL2
- ENCI_MACV_MAX_AMP
- ENCI_VIDEO_MODE_ADV
- ENCI_VFIFO2VD_CTL
- ENCI_VIDEO_EN
- ENCP_VIDEO_MODE
- VPU_HDMI_SETTING
- VENC_UPSAMPLE_CTRL0
- VENC_UPSAMPLE_CTRL1
- VENC_UPSAMPLE_CTRL2
- VENC_VDAC_FIFO_CTRL
- VENC_VDAC_DAC0_FILT_CTRL0
- VENC_INTCTRL

Signed-off-by: Julien Masson <jmasson@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/86r27j82ef.fsf@baylibre.com

authored by

Julien Masson and committed by
Neil Armstrong 7eef9e61 147ae1cb

+177 -32
+51
drivers/gpu/drm/meson/meson_registers.h
··· 734 734 #define VENC_UPSAMPLE_CTRL0 0x1b64 735 735 #define VENC_UPSAMPLE_CTRL1 0x1b65 736 736 #define VENC_UPSAMPLE_CTRL2 0x1b66 737 + #define VENC_UPSAMPLE_CTRL_F0_2_CLK_RATIO BIT(0) 738 + #define VENC_UPSAMPLE_CTRL_F1_EN BIT(5) 739 + #define VENC_UPSAMPLE_CTRL_F1_UPSAMPLE_EN BIT(6) 740 + #define VENC_UPSAMPLE_CTRL_INTERLACE_HIGH_LUMA (0x0 << 12) 741 + #define VENC_UPSAMPLE_CTRL_CVBS (0x1 << 12) 742 + #define VENC_UPSAMPLE_CTRL_S_VIDEO_LUMA (0x2 << 12) 743 + #define VENC_UPSAMPLE_CTRL_S_VIDEO_CHROMA (0x3 << 12) 744 + #define VENC_UPSAMPLE_CTRL_INTERLACE_PB (0x4 << 12) 745 + #define VENC_UPSAMPLE_CTRL_INTERLACE_PR (0x5 << 12) 746 + #define VENC_UPSAMPLE_CTRL_INTERLACE_R (0x6 << 12) 747 + #define VENC_UPSAMPLE_CTRL_INTERLACE_G (0x7 << 12) 748 + #define VENC_UPSAMPLE_CTRL_INTERLACE_B (0x8 << 12) 749 + #define VENC_UPSAMPLE_CTRL_PROGRESSIVE_Y (0x9 << 12) 750 + #define VENC_UPSAMPLE_CTRL_PROGRESSIVE_PB (0xa << 12) 751 + #define VENC_UPSAMPLE_CTRL_PROGRESSIVE_PR (0xb << 12) 752 + #define VENC_UPSAMPLE_CTRL_PROGRESSIVE_R (0xc << 12) 753 + #define VENC_UPSAMPLE_CTRL_PROGRESSIVE_G (0xd << 12) 754 + #define VENC_UPSAMPLE_CTRL_PROGRESSIVE_B (0xe << 12) 755 + #define VENC_UPSAMPLE_CTRL_VDAC_TEST_VALUE (0xf << 12) 737 756 #define TCON_INVERT_CTL 0x1b67 738 757 #define VENC_VIDEO_PROG_MODE 0x1b68 739 758 #define VENC_ENCI_LINE 0x1b69 ··· 761 742 #define VENC_ENCP_PIXEL 0x1b6c 762 743 #define VENC_STATA 0x1b6d 763 744 #define VENC_INTCTRL 0x1b6e 745 + #define VENC_INTCTRL_ENCI_LNRST_INT_EN BIT(1) 764 746 #define VENC_INTFLAG 0x1b6f 765 747 #define VENC_VIDEO_TST_EN 0x1b70 766 748 #define VENC_VIDEO_TST_MDSEL 0x1b71 ··· 772 752 #define VENC_VIDEO_TST_CLRBAR_WIDTH 0x1b76 773 753 #define VENC_VIDEO_TST_VDCNT_STSET 0x1b77 774 754 #define VENC_VDAC_DACSEL0 0x1b78 755 + #define VENC_VDAC_SEL_ATV_DMD BIT(5) 775 756 #define VENC_VDAC_DACSEL1 0x1b79 776 757 #define VENC_VDAC_DACSEL2 0x1b7a 777 758 #define VENC_VDAC_DACSEL3 0x1b7b ··· 793 772 #define VENC_VDAC_DAC5_GAINCTRL 0x1bfa 794 773 #define VENC_VDAC_DAC5_OFFSET 0x1bfb 795 774 #define VENC_VDAC_FIFO_CTRL 0x1bfc 775 + #define VENC_VDAC_FIFO_EN_ENCI_ENABLE BIT(13) 796 776 #define ENCL_TCON_INVERT_CTL 0x1bfd 797 777 #define ENCP_VIDEO_EN 0x1b80 798 778 #define ENCP_VIDEO_SYNC_MODE 0x1b81 ··· 809 787 #define ENCP_VIDEO_SYNC_OFFST 0x1b8b 810 788 #define ENCP_VIDEO_MACV_OFFST 0x1b8c 811 789 #define ENCP_VIDEO_MODE 0x1b8d 790 + #define ENCP_VIDEO_MODE_DE_V_HIGH BIT(14) 812 791 #define ENCP_VIDEO_MODE_ADV 0x1b8e 813 792 #define ENCP_DBG_PX_RST 0x1b90 814 793 #define ENCP_DBG_LN_RST 0x1b91 ··· 888 865 #define C656_FS_LNED 0x1be7 889 866 #define ENCI_VIDEO_MODE 0x1b00 890 867 #define ENCI_VIDEO_MODE_ADV 0x1b01 868 + #define ENCI_VIDEO_MODE_ADV_DMXMD(val) (val & 0x3) 869 + #define ENCI_VIDEO_MODE_ADV_VBICTL_LINE_17_22 BIT(2) 870 + #define ENCI_VIDEO_MODE_ADV_YBW_MEDIUM (0 << 4) 871 + #define ENCI_VIDEO_MODE_ADV_YBW_LOW (0x1 << 4) 872 + #define ENCI_VIDEO_MODE_ADV_YBW_HIGH (0x2 << 4) 891 873 #define ENCI_VIDEO_FSC_ADJ 0x1b02 892 874 #define ENCI_VIDEO_BRIGHT 0x1b03 893 875 #define ENCI_VIDEO_CONT 0x1b04 ··· 963 935 #define ENCI_DBG_MAXPX 0x1b4c 964 936 #define ENCI_DBG_MAXLN 0x1b4d 965 937 #define ENCI_MACV_MAX_AMP 0x1b50 938 + #define ENCI_MACV_MAX_AMP_ENABLE_CHANGE BIT(15) 939 + #define ENCI_MACV_MAX_AMP_VAL(val) (val & 0x83ff) 966 940 #define ENCI_MACV_PULSE_LO 0x1b51 967 941 #define ENCI_MACV_PULSE_HI 0x1b52 968 942 #define ENCI_MACV_BKP_MAX 0x1b53 969 943 #define ENCI_CFILT_CTRL 0x1b54 944 + #define ENCI_CFILT_CMPT_SEL_HIGH BIT(1) 970 945 #define ENCI_CFILT7 0x1b55 971 946 #define ENCI_YC_DELAY 0x1b56 972 947 #define ENCI_VIDEO_EN 0x1b57 948 + #define ENCI_VIDEO_EN_ENABLE BIT(0) 973 949 #define ENCI_DVI_HSO_BEGIN 0x1c00 974 950 #define ENCI_DVI_HSO_END 0x1c01 975 951 #define ENCI_DVI_VSO_BLINE_EVN 0x1c02 ··· 985 953 #define ENCI_DVI_VSO_END_EVN 0x1c08 986 954 #define ENCI_DVI_VSO_END_ODD 0x1c09 987 955 #define ENCI_CFILT_CTRL2 0x1c0a 956 + #define ENCI_CFILT_CMPT_CR_DLY(delay) (delay & 0xf) 957 + #define ENCI_CFILT_CMPT_CB_DLY(delay) ((delay & 0xf) << 4) 958 + #define ENCI_CFILT_CVBS_CR_DLY(delay) ((delay & 0xf) << 8) 959 + #define ENCI_CFILT_CVBS_CB_DLY(delay) ((delay & 0xf) << 12) 988 960 #define ENCI_DACSEL_0 0x1c0b 989 961 #define ENCI_DACSEL_1 0x1c0c 990 962 #define ENCP_DACSEL_0 0x1c0d ··· 1003 967 #define ENCI_TST_CLRBAR_WIDTH 0x1c16 1004 968 #define ENCI_TST_VDCNT_STSET 0x1c17 1005 969 #define ENCI_VFIFO2VD_CTL 0x1c18 970 + #define ENCI_VFIFO2VD_CTL_ENABLE BIT(0) 971 + #define ENCI_VFIFO2VD_CTL_VD_SEL(val) ((val & 0xff) << 8) 1006 972 #define ENCI_VFIFO2VD_PIXEL_START 0x1c19 1007 973 #define ENCI_VFIFO2VD_PIXEL_END 0x1c1a 1008 974 #define ENCI_VFIFO2VD_LINE_TOP_START 0x1c1b ··· 1067 1029 #define VENC_VDAC_DAC5_FILT_CTRL0 0x1c56 1068 1030 #define VENC_VDAC_DAC5_FILT_CTRL1 0x1c57 1069 1031 #define VENC_VDAC_DAC0_FILT_CTRL0 0x1c58 1032 + #define VENC_VDAC_DAC0_FILT_CTRL0_EN BIT(0) 1070 1033 #define VENC_VDAC_DAC0_FILT_CTRL1 0x1c59 1071 1034 #define VENC_VDAC_DAC1_FILT_CTRL0 0x1c5a 1072 1035 #define VENC_VDAC_DAC1_FILT_CTRL1 0x1c5b ··· 1473 1434 #define VIU2_SEL_VENC_ENCP (2 << 2) 1474 1435 #define VIU2_SEL_VENC_ENCT (3 << 2) 1475 1436 #define VPU_HDMI_SETTING 0x271b 1437 + #define VPU_HDMI_ENCI_DATA_TO_HDMI BIT(0) 1438 + #define VPU_HDMI_ENCP_DATA_TO_HDMI BIT(1) 1439 + #define VPU_HDMI_INV_HSYNC BIT(2) 1440 + #define VPU_HDMI_INV_VSYNC BIT(3) 1441 + #define VPU_HDMI_OUTPUT_CRYCB (0 << 5) 1442 + #define VPU_HDMI_OUTPUT_YCBCR (1 << 5) 1443 + #define VPU_HDMI_OUTPUT_YCRCB (2 << 5) 1444 + #define VPU_HDMI_OUTPUT_CBCRY (3 << 5) 1445 + #define VPU_HDMI_OUTPUT_CBYCR (4 << 5) 1446 + #define VPU_HDMI_OUTPUT_CRCBY (5 << 5) 1447 + #define VPU_HDMI_WR_RATE(rate) (((rate & 0x1f) - 1) << 8) 1448 + #define VPU_HDMI_RD_RATE(rate) (((rate & 0x1f) - 1) << 12) 1476 1449 #define ENCI_INFO_READ 0x271c 1477 1450 #define ENCP_INFO_READ 0x271d 1478 1451 #define ENCT_INFO_READ 0x271e
+124 -31
drivers/gpu/drm/meson/meson_venc.c
··· 976 976 unsigned int eof_lines; 977 977 unsigned int sof_lines; 978 978 unsigned int vsync_lines; 979 + u32 reg; 979 980 980 981 /* Use VENCI for 480i and 576i and double HDMI pixels */ 981 982 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { ··· 1049 1048 unsigned int lines_f1; 1050 1049 1051 1050 /* CVBS Filter settings */ 1052 - writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL)); 1053 - writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL2)); 1051 + writel_relaxed(ENCI_CFILT_CMPT_SEL_HIGH | 0x10, 1052 + priv->io_base + _REG(ENCI_CFILT_CTRL)); 1053 + writel_relaxed(ENCI_CFILT_CMPT_CR_DLY(2) | 1054 + ENCI_CFILT_CMPT_CB_DLY(1), 1055 + priv->io_base + _REG(ENCI_CFILT_CTRL2)); 1054 1056 1055 1057 /* Digital Video Select : Interlace, clk27 clk, external */ 1056 1058 writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING)); ··· 1075 1071 priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN)); 1076 1072 1077 1073 /* Macrovision max amplitude change */ 1078 - writel_relaxed(vmode->enci.macv_max_amp, 1079 - priv->io_base + _REG(ENCI_MACV_MAX_AMP)); 1074 + writel_relaxed(ENCI_MACV_MAX_AMP_ENABLE_CHANGE | 1075 + ENCI_MACV_MAX_AMP_VAL(vmode->enci.macv_max_amp), 1076 + priv->io_base + _REG(ENCI_MACV_MAX_AMP)); 1080 1077 1081 1078 /* Video mode */ 1082 1079 writel_relaxed(vmode->enci.video_prog_mode, ··· 1093 1088 * Bypass luma low pass filter 1094 1089 * No macrovision on CSYNC 1095 1090 */ 1096 - writel_relaxed(0x26, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV)); 1091 + writel_relaxed(ENCI_VIDEO_MODE_ADV_DMXMD(2) | 1092 + ENCI_VIDEO_MODE_ADV_VBICTL_LINE_17_22 | 1093 + ENCI_VIDEO_MODE_ADV_YBW_HIGH, 1094 + priv->io_base + _REG(ENCI_VIDEO_MODE_ADV)); 1097 1095 1098 1096 writel(vmode->enci.sch_adjust, 1099 1097 priv->io_base + _REG(ENCI_VIDEO_SCH)); ··· 1112 1104 /* UNreset Interlaced TV Encoder */ 1113 1105 writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST)); 1114 1106 1115 - /* Enable Vfifo2vd, Y_Cb_Y_Cr select */ 1116 - writel_relaxed(0x4e01, priv->io_base + _REG(ENCI_VFIFO2VD_CTL)); 1107 + /* 1108 + * Enable Vfifo2vd and set Y_Cb_Y_Cr: 1109 + * Corresponding value: 1110 + * Y => 00 or 10 1111 + * Cb => 01 1112 + * Cr => 11 1113 + * Ex: 0x4e => 01001110 would mean Cb/Y/Cr/Y 1114 + */ 1115 + writel_relaxed(ENCI_VFIFO2VD_CTL_ENABLE | 1116 + ENCI_VFIFO2VD_CTL_VD_SEL(0x4e), 1117 + priv->io_base + _REG(ENCI_VFIFO2VD_CTL)); 1117 1118 1118 1119 /* Timings */ 1119 1120 writel_relaxed(vmode->enci.pixel_start, ··· 1144 1127 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCI); 1145 1128 1146 1129 /* Interlace video enable */ 1147 - writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN)); 1130 + writel_relaxed(ENCI_VIDEO_EN_ENABLE, 1131 + priv->io_base + _REG(ENCI_VIDEO_EN)); 1148 1132 1149 1133 lines_f0 = mode->vtotal >> 1; 1150 1134 lines_f1 = lines_f0 + 1; ··· 1392 1374 writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN)); 1393 1375 1394 1376 /* Set DE signal’s polarity is active high */ 1395 - writel_bits_relaxed(BIT(14), BIT(14), 1377 + writel_bits_relaxed(ENCP_VIDEO_MODE_DE_V_HIGH, 1378 + ENCP_VIDEO_MODE_DE_V_HIGH, 1396 1379 priv->io_base + _REG(ENCP_VIDEO_MODE)); 1397 1380 1398 1381 /* Program DE timing */ ··· 1512 1493 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCP); 1513 1494 } 1514 1495 1515 - writel_relaxed((use_enci ? 1 : 2) | 1516 - (mode->flags & DRM_MODE_FLAG_PHSYNC ? 1 << 2 : 0) | 1517 - (mode->flags & DRM_MODE_FLAG_PVSYNC ? 1 << 3 : 0) | 1518 - 4 << 5 | 1519 - (venc_repeat ? 1 << 8 : 0) | 1520 - (hdmi_repeat ? 1 << 12 : 0), 1521 - priv->io_base + _REG(VPU_HDMI_SETTING)); 1496 + /* Set VPU HDMI setting */ 1497 + /* Select ENCP or ENCI data to HDMI */ 1498 + if (use_enci) 1499 + reg = VPU_HDMI_ENCI_DATA_TO_HDMI; 1500 + else 1501 + reg = VPU_HDMI_ENCP_DATA_TO_HDMI; 1502 + 1503 + /* Invert polarity of HSYNC from VENC */ 1504 + if (mode->flags & DRM_MODE_FLAG_PHSYNC) 1505 + reg |= VPU_HDMI_INV_HSYNC; 1506 + 1507 + /* Invert polarity of VSYNC from VENC */ 1508 + if (mode->flags & DRM_MODE_FLAG_PVSYNC) 1509 + reg |= VPU_HDMI_INV_VSYNC; 1510 + 1511 + /* Output data format: CbYCr */ 1512 + reg |= VPU_HDMI_OUTPUT_CBYCR; 1513 + 1514 + /* 1515 + * Write rate to the async FIFO between VENC and HDMI. 1516 + * One write every 2 wr_clk. 1517 + */ 1518 + if (venc_repeat) 1519 + reg |= VPU_HDMI_WR_RATE(2); 1520 + 1521 + /* 1522 + * Read rate to the async FIFO between VENC and HDMI. 1523 + * One read every 2 wr_clk. 1524 + */ 1525 + if (hdmi_repeat) 1526 + reg |= VPU_HDMI_RD_RATE(2); 1527 + 1528 + writel_relaxed(reg, priv->io_base + _REG(VPU_HDMI_SETTING)); 1522 1529 1523 1530 priv->venc.hdmi_repeat = hdmi_repeat; 1524 1531 priv->venc.venc_repeat = venc_repeat; ··· 1557 1512 void meson_venci_cvbs_mode_set(struct meson_drm *priv, 1558 1513 struct meson_cvbs_enci_mode *mode) 1559 1514 { 1515 + u32 reg; 1516 + 1560 1517 if (mode->mode_tag == priv->venc.current_mode) 1561 1518 return; 1562 1519 1563 1520 /* CVBS Filter settings */ 1564 - writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL)); 1565 - writel_relaxed(0x12, priv->io_base + _REG(ENCI_CFILT_CTRL2)); 1521 + writel_relaxed(ENCI_CFILT_CMPT_SEL_HIGH | 0x10, 1522 + priv->io_base + _REG(ENCI_CFILT_CTRL)); 1523 + writel_relaxed(ENCI_CFILT_CMPT_CR_DLY(2) | 1524 + ENCI_CFILT_CMPT_CB_DLY(1), 1525 + priv->io_base + _REG(ENCI_CFILT_CTRL2)); 1566 1526 1567 1527 /* Digital Video Select : Interlace, clk27 clk, external */ 1568 1528 writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING)); ··· 1589 1539 priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN)); 1590 1540 1591 1541 /* Macrovision max amplitude change */ 1592 - writel_relaxed(0x8100 + mode->macv_max_amp, 1593 - priv->io_base + _REG(ENCI_MACV_MAX_AMP)); 1542 + writel_relaxed(ENCI_MACV_MAX_AMP_ENABLE_CHANGE | 1543 + ENCI_MACV_MAX_AMP_VAL(mode->macv_max_amp), 1544 + priv->io_base + _REG(ENCI_MACV_MAX_AMP)); 1594 1545 1595 1546 /* Video mode */ 1596 1547 writel_relaxed(mode->video_prog_mode, ··· 1607 1556 * Bypass luma low pass filter 1608 1557 * No macrovision on CSYNC 1609 1558 */ 1610 - writel_relaxed(0x26, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV)); 1559 + writel_relaxed(ENCI_VIDEO_MODE_ADV_DMXMD(2) | 1560 + ENCI_VIDEO_MODE_ADV_VBICTL_LINE_17_22 | 1561 + ENCI_VIDEO_MODE_ADV_YBW_HIGH, 1562 + priv->io_base + _REG(ENCI_VIDEO_MODE_ADV)); 1611 1563 1612 1564 writel(mode->sch_adjust, priv->io_base + _REG(ENCI_VIDEO_SCH)); 1613 1565 ··· 1642 1588 /* UNreset Interlaced TV Encoder */ 1643 1589 writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST)); 1644 1590 1645 - /* Enable Vfifo2vd, Y_Cb_Y_Cr select */ 1646 - writel_relaxed(0x4e01, priv->io_base + _REG(ENCI_VFIFO2VD_CTL)); 1591 + /* 1592 + * Enable Vfifo2vd and set Y_Cb_Y_Cr: 1593 + * Corresponding value: 1594 + * Y => 00 or 10 1595 + * Cb => 01 1596 + * Cr => 11 1597 + * Ex: 0x4e => 01001110 would mean Cb/Y/Cr/Y 1598 + */ 1599 + writel_relaxed(ENCI_VFIFO2VD_CTL_ENABLE | 1600 + ENCI_VFIFO2VD_CTL_VD_SEL(0x4e), 1601 + priv->io_base + _REG(ENCI_VFIFO2VD_CTL)); 1647 1602 1648 1603 /* Power UP Dacs */ 1649 1604 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_SETTING)); 1650 1605 1651 1606 /* Video Upsampling */ 1652 - writel_relaxed(0x0061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL0)); 1653 - writel_relaxed(0x4061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL1)); 1654 - writel_relaxed(0x5061, priv->io_base + _REG(VENC_UPSAMPLE_CTRL2)); 1607 + /* 1608 + * CTRL0, CTRL1 and CTRL2: 1609 + * Filter0: input data sample every 2 cloks 1610 + * Filter1: filtering and upsample enable 1611 + */ 1612 + reg = VENC_UPSAMPLE_CTRL_F0_2_CLK_RATIO | VENC_UPSAMPLE_CTRL_F1_EN | 1613 + VENC_UPSAMPLE_CTRL_F1_UPSAMPLE_EN; 1614 + 1615 + /* 1616 + * Upsample CTRL0: 1617 + * Interlace High Bandwidth Luma 1618 + */ 1619 + writel_relaxed(VENC_UPSAMPLE_CTRL_INTERLACE_HIGH_LUMA | reg, 1620 + priv->io_base + _REG(VENC_UPSAMPLE_CTRL0)); 1621 + 1622 + /* 1623 + * Upsample CTRL1: 1624 + * Interlace Pb 1625 + */ 1626 + writel_relaxed(VENC_UPSAMPLE_CTRL_INTERLACE_PB | reg, 1627 + priv->io_base + _REG(VENC_UPSAMPLE_CTRL1)); 1628 + 1629 + /* 1630 + * Upsample CTRL2: 1631 + * Interlace R 1632 + */ 1633 + writel_relaxed(VENC_UPSAMPLE_CTRL_INTERLACE_PR | reg, 1634 + priv->io_base + _REG(VENC_UPSAMPLE_CTRL2)); 1655 1635 1656 1636 /* Select Interlace Y DACs */ 1657 1637 writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL0)); ··· 1699 1611 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCI); 1700 1612 1701 1613 /* Enable ENCI FIFO */ 1702 - writel_relaxed(0x2000, priv->io_base + _REG(VENC_VDAC_FIFO_CTRL)); 1614 + writel_relaxed(VENC_VDAC_FIFO_EN_ENCI_ENABLE, 1615 + priv->io_base + _REG(VENC_VDAC_FIFO_CTRL)); 1703 1616 1704 1617 /* Select ENCI DACs 0, 1, 4, and 5 */ 1705 1618 writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_0)); 1706 1619 writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_1)); 1707 1620 1708 1621 /* Interlace video enable */ 1709 - writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN)); 1622 + writel_relaxed(ENCI_VIDEO_EN_ENABLE, 1623 + priv->io_base + _REG(ENCI_VIDEO_EN)); 1710 1624 1711 1625 /* Configure Video Saturation / Contrast / Brightness / Hue */ 1712 1626 writel_relaxed(mode->video_saturation, ··· 1721 1631 priv->io_base + _REG(ENCI_VIDEO_HUE)); 1722 1632 1723 1633 /* Enable DAC0 Filter */ 1724 - writel_relaxed(0x1, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL0)); 1634 + writel_relaxed(VENC_VDAC_DAC0_FILT_CTRL0_EN, 1635 + priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL0)); 1725 1636 writel_relaxed(0xfc48, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL1)); 1726 1637 1727 1638 /* 0 in Macrovision register 0 */ ··· 1743 1652 1744 1653 void meson_venc_enable_vsync(struct meson_drm *priv) 1745 1654 { 1746 - writel_relaxed(2, priv->io_base + _REG(VENC_INTCTRL)); 1655 + writel_relaxed(VENC_INTCTRL_ENCI_LNRST_INT_EN, 1656 + priv->io_base + _REG(VENC_INTCTRL)); 1747 1657 regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25)); 1748 1658 } 1749 1659 ··· 1772 1680 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0); 1773 1681 1774 1682 /* Disable HDMI */ 1775 - writel_bits_relaxed(0x3, 0, 1683 + writel_bits_relaxed(VPU_HDMI_ENCI_DATA_TO_HDMI | 1684 + VPU_HDMI_ENCP_DATA_TO_HDMI, 0, 1776 1685 priv->io_base + _REG(VPU_HDMI_SETTING)); 1777 1686 1778 1687 /* Disable all encoders */
+2 -1
drivers/gpu/drm/meson/meson_venc_cvbs.c
··· 171 171 struct meson_drm *priv = meson_venc_cvbs->priv; 172 172 173 173 /* VDAC0 source is not from ATV */ 174 - writel_bits_relaxed(BIT(5), 0, priv->io_base + _REG(VENC_VDAC_DACSEL0)); 174 + writel_bits_relaxed(VENC_VDAC_SEL_ATV_DMD, 0, 175 + priv->io_base + _REG(VENC_VDAC_DACSEL0)); 175 176 176 177 if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) { 177 178 regmap_write(priv->hhi, HHI_VDAC_CNTL0, 1);