tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'samsung-clk-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung
Pull more Samsung clk driver updates from Krzysztof Kozlowski:
- ExynosAutov920: add support for additional clock controllers (M2M and
MFC)
* tag 'samsung-clk-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
clk: samsung: clk-pll: simplify samsung_pll_lock_wait()
clk: samsung: exynosautov920: add block mfc clock support
clk: samsung: exynosautov920: add clock support
dt-bindings: clock: exynosautov920: add mfc clock definitions
dt-bindings: clock: exynosautov920: add m2m clock definitions
dt-bindings: clock: google,gs101-clock: add power-domains
+155
-31
+3
Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
+3
Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
+42
Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml
+42
Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml
···
38
38
- samsung,exynosautov920-cmu-hsi0
39
39
- samsung,exynosautov920-cmu-hsi1
40
40
- samsung,exynosautov920-cmu-hsi2
41
+
- samsung,exynosautov920-cmu-m2m
42
+
- samsung,exynosautov920-cmu-mfc
41
43
- samsung,exynosautov920-cmu-misc
42
44
- samsung,exynosautov920-cmu-peric0
43
45
- samsung,exynosautov920-cmu-peric1
···
227
225
- const: ufs
228
226
- const: embd
229
227
- const: ethernet
228
+
229
+
- if:
230
+
properties:
231
+
compatible:
232
+
contains:
233
+
const: samsung,exynosautov920-cmu-m2m
234
+
235
+
then:
236
+
properties:
237
+
clocks:
238
+
items:
239
+
- description: External reference clock (38.4 MHz)
240
+
- description: CMU_M2M NOC clock (from CMU_TOP)
241
+
- description: CMU_M2M JPEG clock (from CMU_TOP)
242
+
243
+
clock-names:
244
+
items:
245
+
- const: oscclk
246
+
- const: noc
247
+
- const: jpeg
248
+
249
+
- if:
250
+
properties:
251
+
compatible:
252
+
contains:
253
+
const: samsung,exynosautov920-cmu-mfc
254
+
255
+
then:
256
+
properties:
257
+
clocks:
258
+
items:
259
+
- description: External reference clock (38.4 MHz)
260
+
- description: CMU_MFC MFC clock (from CMU_TOP)
261
+
- description: CMU_MFC WFD clock (from CMU_TOP)
262
+
263
+
clock-names:
264
+
items:
265
+
- const: oscclk
266
+
- const: mfc
267
+
- const: wfd
230
268
231
269
required:
232
270
- compatible
+90
drivers/clk/samsung/clk-exynosautov920.c
+90
drivers/clk/samsung/clk-exynosautov920.c
···
27
27
#define CLKS_NR_HSI0 (CLK_DOUT_HSI0_PCIE_APB + 1)
28
28
#define CLKS_NR_HSI1 (CLK_MOUT_HSI1_USBDRD + 1)
29
29
#define CLKS_NR_HSI2 (CLK_DOUT_HSI2_ETHERNET_PTP + 1)
30
+
#define CLKS_NR_M2M (CLK_DOUT_M2M_NOCP + 1)
31
+
#define CLKS_NR_MFC (CLK_DOUT_MFC_NOCP + 1)
30
32
31
33
/* ---- CMU_TOP ------------------------------------------------------------ */
32
34
···
1823
1821
.clk_name = "noc",
1824
1822
};
1825
1823
1824
+
/* ---- CMU_M2M --------------------------------------------------------- */
1825
+
1826
+
/* Register Offset definitions for CMU_M2M (0x1a800000) */
1827
+
#define PLL_CON0_MUX_CLKCMU_M2M_JPEG_USER 0x600
1828
+
#define PLL_CON0_MUX_CLKCMU_M2M_NOC_USER 0x610
1829
+
#define CLK_CON_DIV_DIV_CLK_M2M_NOCP 0x1800
1830
+
1831
+
static const unsigned long m2m_clk_regs[] __initconst = {
1832
+
PLL_CON0_MUX_CLKCMU_M2M_JPEG_USER,
1833
+
PLL_CON0_MUX_CLKCMU_M2M_NOC_USER,
1834
+
CLK_CON_DIV_DIV_CLK_M2M_NOCP,
1835
+
};
1836
+
1837
+
/* List of parent clocks for Muxes in CMU_M2M */
1838
+
PNAME(mout_clkcmu_m2m_noc_user_p) = { "oscclk", "dout_clkcmu_m2m_noc" };
1839
+
PNAME(mout_clkcmu_m2m_jpeg_user_p) = { "oscclk", "dout_clkcmu_m2m_jpeg" };
1840
+
1841
+
static const struct samsung_mux_clock m2m_mux_clks[] __initconst = {
1842
+
MUX(CLK_MOUT_M2M_JPEG_USER, "mout_clkcmu_m2m_jpeg_user",
1843
+
mout_clkcmu_m2m_jpeg_user_p, PLL_CON0_MUX_CLKCMU_M2M_JPEG_USER, 4, 1),
1844
+
MUX(CLK_MOUT_M2M_NOC_USER, "mout_clkcmu_m2m_noc_user",
1845
+
mout_clkcmu_m2m_noc_user_p, PLL_CON0_MUX_CLKCMU_M2M_NOC_USER, 4, 1),
1846
+
};
1847
+
1848
+
static const struct samsung_div_clock m2m_div_clks[] __initconst = {
1849
+
DIV(CLK_DOUT_M2M_NOCP, "dout_m2m_nocp",
1850
+
"mout_clkcmu_m2m_noc_user", CLK_CON_DIV_DIV_CLK_M2M_NOCP,
1851
+
0, 3),
1852
+
};
1853
+
1854
+
static const struct samsung_cmu_info m2m_cmu_info __initconst = {
1855
+
.mux_clks = m2m_mux_clks,
1856
+
.nr_mux_clks = ARRAY_SIZE(m2m_mux_clks),
1857
+
.div_clks = m2m_div_clks,
1858
+
.nr_div_clks = ARRAY_SIZE(m2m_div_clks),
1859
+
.nr_clk_ids = CLKS_NR_M2M,
1860
+
.clk_regs = m2m_clk_regs,
1861
+
.nr_clk_regs = ARRAY_SIZE(m2m_clk_regs),
1862
+
.clk_name = "noc",
1863
+
};
1864
+
1865
+
/* ---- CMU_MFC --------------------------------------------------------- */
1866
+
1867
+
/* Register Offset definitions for CMU_MFC (0x19c00000) */
1868
+
#define PLL_CON0_MUX_CLKCMU_MFC_MFC_USER 0x600
1869
+
#define PLL_CON0_MUX_CLKCMU_MFC_WFD_USER 0x610
1870
+
#define CLK_CON_DIV_DIV_CLK_MFC_NOCP 0x1800
1871
+
1872
+
static const unsigned long mfc_clk_regs[] __initconst = {
1873
+
PLL_CON0_MUX_CLKCMU_MFC_MFC_USER,
1874
+
PLL_CON0_MUX_CLKCMU_MFC_WFD_USER,
1875
+
CLK_CON_DIV_DIV_CLK_MFC_NOCP,
1876
+
};
1877
+
1878
+
/* List of parent clocks for Muxes in CMU_MFC */
1879
+
PNAME(mout_clkcmu_mfc_mfc_user_p) = { "oscclk", "dout_clkcmu_mfc_mfc" };
1880
+
PNAME(mout_clkcmu_mfc_wfd_user_p) = { "oscclk", "dout_clkcmu_mfc_wfd" };
1881
+
1882
+
static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {
1883
+
MUX(CLK_MOUT_MFC_MFC_USER, "mout_clkcmu_mfc_mfc_user",
1884
+
mout_clkcmu_mfc_mfc_user_p, PLL_CON0_MUX_CLKCMU_MFC_MFC_USER, 4, 1),
1885
+
MUX(CLK_MOUT_MFC_WFD_USER, "mout_clkcmu_mfc_wfd_user",
1886
+
mout_clkcmu_mfc_wfd_user_p, PLL_CON0_MUX_CLKCMU_MFC_WFD_USER, 4, 1),
1887
+
};
1888
+
1889
+
static const struct samsung_div_clock mfc_div_clks[] __initconst = {
1890
+
DIV(CLK_DOUT_MFC_NOCP, "dout_mfc_nocp",
1891
+
"mout_clkcmu_mfc_mfc_user", CLK_CON_DIV_DIV_CLK_MFC_NOCP,
1892
+
0, 3),
1893
+
};
1894
+
1895
+
static const struct samsung_cmu_info mfc_cmu_info __initconst = {
1896
+
.mux_clks = mfc_mux_clks,
1897
+
.nr_mux_clks = ARRAY_SIZE(mfc_mux_clks),
1898
+
.div_clks = mfc_div_clks,
1899
+
.nr_div_clks = ARRAY_SIZE(mfc_div_clks),
1900
+
.nr_clk_ids = CLKS_NR_MFC,
1901
+
.clk_regs = mfc_clk_regs,
1902
+
.nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
1903
+
.clk_name = "noc",
1904
+
};
1905
+
1826
1906
static int __init exynosautov920_cmu_probe(struct platform_device *pdev)
1827
1907
{
1828
1908
const struct samsung_cmu_info *info;
···
1935
1851
}, {
1936
1852
.compatible = "samsung,exynosautov920-cmu-hsi2",
1937
1853
.data = &hsi2_cmu_info,
1854
+
}, {
1855
+
.compatible = "samsung,exynosautov920-cmu-m2m",
1856
+
.data = &m2m_cmu_info,
1857
+
}, {
1858
+
.compatible = "samsung,exynosautov920-cmu-mfc",
1859
+
.data = &mfc_cmu_info,
1938
1860
},
1939
1861
{ }
1940
1862
};
+10
-31
drivers/clk/samsung/clk-pll.c
+10
-31
drivers/clk/samsung/clk-pll.c
···
11
11
#include <linux/iopoll.h>
12
12
#include <linux/delay.h>
13
13
#include <linux/slab.h>
14
-
#include <linux/timekeeping.h>
15
14
#include <linux/clk-provider.h>
16
15
#include <linux/io.h>
17
16
#include "clk.h"
18
17
#include "clk-pll.h"
19
18
20
-
#define PLL_TIMEOUT_US 20000U
21
-
#define PLL_TIMEOUT_LOOPS 1000000U
19
+
#define PLL_TIMEOUT_LOOPS 20000U
22
20
23
21
struct samsung_clk_pll {
24
22
struct clk_hw hw;
···
69
71
return 0;
70
72
}
71
73
72
-
static bool pll_early_timeout = true;
73
-
74
-
static int __init samsung_pll_disable_early_timeout(void)
75
-
{
76
-
pll_early_timeout = false;
77
-
return 0;
78
-
}
79
-
arch_initcall(samsung_pll_disable_early_timeout);
80
-
81
74
/* Wait until the PLL is locked */
82
75
static int samsung_pll_lock_wait(struct samsung_clk_pll *pll,
83
76
unsigned int reg_mask)
84
77
{
85
-
int i, ret;
78
+
int ret;
86
79
u32 val;
87
80
88
81
/*
···
82
93
* initialized, another when the timekeeping is suspended. udelay() also
83
94
* cannot be used when the clocksource is not running on arm64, since
84
95
* the current timer is used as cycle counter. So a simple busy loop
85
-
* is used here in that special cases. The limit of iterations has been
86
-
* derived from experimental measurements of various PLLs on multiple
87
-
* Exynos SoC variants. Single register read time was usually in range
88
-
* 0.4...1.5 us, never less than 0.4 us.
96
+
* is used here.
97
+
* The limit of iterations has been derived from experimental
98
+
* measurements of various PLLs on multiple Exynos SoC variants. Single
99
+
* register read time was usually in range 0.4...1.5 us, never less than
100
+
* 0.4 us.
89
101
*/
90
-
if (pll_early_timeout || timekeeping_suspended) {
91
-
i = PLL_TIMEOUT_LOOPS;
92
-
while (i-- > 0) {
93
-
if (readl_relaxed(pll->con_reg) & reg_mask)
94
-
return 0;
95
-
96
-
cpu_relax();
97
-
}
98
-
ret = -ETIMEDOUT;
99
-
} else {
100
-
ret = readl_relaxed_poll_timeout_atomic(pll->con_reg, val,
101
-
val & reg_mask, 0, PLL_TIMEOUT_US);
102
-
}
103
-
102
+
ret = readl_relaxed_poll_timeout_atomic(pll->con_reg, val,
103
+
val & reg_mask, 0,
104
+
PLL_TIMEOUT_LOOPS);
104
105
if (ret < 0)
105
106
pr_err("Could not lock PLL %s\n", clk_hw_get_name(&pll->hw));
106
107
+10
include/dt-bindings/clock/samsung,exynosautov920.h
+10
include/dt-bindings/clock/samsung,exynosautov920.h
···
295
295
#define CLK_DOUT_HSI2_ETHERNET 6
296
296
#define CLK_DOUT_HSI2_ETHERNET_PTP 7
297
297
298
+
/* CMU_M2M */
299
+
#define CLK_MOUT_M2M_JPEG_USER 1
300
+
#define CLK_MOUT_M2M_NOC_USER 2
301
+
#define CLK_DOUT_M2M_NOCP 3
302
+
303
+
/* CMU_MFC */
304
+
#define CLK_MOUT_MFC_MFC_USER 1
305
+
#define CLK_MOUT_MFC_WFD_USER 2
306
+
#define CLK_DOUT_MFC_NOCP 3
307
+
298
308
#endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H */