···11+J-Core SPI master22+33+Required properties:44+55+- compatible: Must be "jcore,spi2".66+77+- reg: Memory region for registers.88+99+- #address-cells: Must be 1.1010+1111+- #size-cells: Must be 0.1212+1313+Optional properties:1414+1515+- clocks: If a phandle named "ref_clk" is present, SPI clock speed1616+ programming is relative to the frequency of the indicated clock.1717+ Necessary only if the input clock rate is something other than a1818+ fixed 50 MHz.1919+2020+- clock-names: Clock names, one for each phandle in clocks.2121+2222+See spi-bus.txt for additional properties not specific to this device.2323+2424+Example:2525+2626+spi@40 {2727+ compatible = "jcore,spi2";2828+ #address-cells = <1>;2929+ #size-cells = <0>;3030+ reg = <0x40 0x8>;3131+ spi-max-frequency = <25000000>;3232+ clocks = <&bus_clk>;3333+ clock-names = "ref_clk";3434+}