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drm/i915/reg: separate VLV_DSPCLK_GATE_D from DSPCLK_GATE_D

All the places that use DSPCLK_GATE_D are specific to certain platforms,
and the parametrization of it to support VLV/CHV MMIO display base isn't
really buying us anything. Add a separate macro for VLV_DSPCLK_GATE_D
and use it.

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://lore.kernel.org/r/ac16d9d5192595944bf9bcf70aa721b504bc90c0.1754499175.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Jani Nikula 7e757092 85cac9ff

+10 -10
+1 -1
drivers/gpu/drm/i915/display/intel_display_power_well.c
··· 1209 1209 * (and never recovering) in this case. intel_dsi_post_disable() will 1210 1210 * clear it when we turn off the display. 1211 1211 */ 1212 - intel_de_rmw(display, DSPCLK_GATE_D(display), 1212 + intel_de_rmw(display, VLV_DSPCLK_GATE_D, 1213 1213 ~DPOUNIT_CLOCK_GATE_DISABLE, VRHUNIT_CLOCK_GATE_DISABLE); 1214 1214 1215 1215 /*
+1 -1
drivers/gpu/drm/i915/display/intel_gmbus.c
··· 219 219 bool enable) 220 220 { 221 221 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 222 - intel_de_rmw(display, DSPCLK_GATE_D(display), 222 + intel_de_rmw(display, DSPCLK_GATE_D, 223 223 PNV_GMBUSUNIT_CLOCK_GATE_DISABLE, 224 224 !enable ? PNV_GMBUSUNIT_CLOCK_GATE_DISABLE : 0); 225 225 }
+2 -3
drivers/gpu/drm/i915/display/intel_overlay.c
··· 217 217 218 218 /* WA_OVERLAY_CLKGATE:alm */ 219 219 if (enable) 220 - intel_de_write(display, DSPCLK_GATE_D(display), 0); 220 + intel_de_write(display, DSPCLK_GATE_D, 0); 221 221 else 222 - intel_de_write(display, DSPCLK_GATE_D(display), 223 - OVRUNIT_CLOCK_GATE_DISABLE); 222 + intel_de_write(display, DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); 224 223 225 224 /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */ 226 225 pci_bus_read_config_byte(pdev->bus,
+2 -2
drivers/gpu/drm/i915/display/vlv_dsi.c
··· 761 761 762 762 if (display->platform.valleyview || display->platform.cherryview) { 763 763 /* Disable DPOunit clock gating, can stall pipe */ 764 - intel_de_rmw(display, DSPCLK_GATE_D(display), 764 + intel_de_rmw(display, VLV_DSPCLK_GATE_D, 765 765 0, DPOUNIT_CLOCK_GATE_DISABLE); 766 766 } 767 767 ··· 918 918 } else { 919 919 vlv_dsi_pll_disable(encoder); 920 920 921 - intel_de_rmw(display, DSPCLK_GATE_D(display), 921 + intel_de_rmw(display, VLV_DSPCLK_GATE_D, 922 922 DPOUNIT_CLOCK_GATE_DISABLE, 0); 923 923 } 924 924
+2 -1
drivers/gpu/drm/i915/i915_reg.h
··· 613 613 #define DSTATE_GFX_CLOCK_GATING (1 << 1) 614 614 #define DSTATE_DOT_CLOCK_GATING (1 << 0) 615 615 616 - #define DSPCLK_GATE_D(__i915) _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200) 616 + #define DSPCLK_GATE_D _MMIO(0x6200) 617 + #define VLV_DSPCLK_GATE_D _MMIO(VLV_DISPLAY_BASE + 0x6200) 617 618 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 618 619 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 619 620 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
+2 -2
drivers/gpu/drm/i915/intel_clock_gating.c
··· 620 620 OVCUNIT_CLOCK_GATE_DISABLE; 621 621 if (IS_GM45(i915)) 622 622 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; 623 - intel_uncore_write(&i915->uncore, DSPCLK_GATE_D(i915), dspclk_gate); 623 + intel_uncore_write(&i915->uncore, DSPCLK_GATE_D, dspclk_gate); 624 624 625 625 g4x_disable_trickle_feed(i915); 626 626 } ··· 631 631 632 632 intel_uncore_write(uncore, RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); 633 633 intel_uncore_write(uncore, RENCLK_GATE_D2, 0); 634 - intel_uncore_write(uncore, DSPCLK_GATE_D(i915), 0); 634 + intel_uncore_write(uncore, DSPCLK_GATE_D, 0); 635 635 intel_uncore_write(uncore, RAMCLK_GATE_D, 0); 636 636 intel_uncore_write16(uncore, DEUC, 0); 637 637 intel_uncore_write(uncore,