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drm: pl111: Absorb the external register header
The PL111 DRM driver is now the sole user of the external
CLCD registers header file, so let's absorb that into the
pl111_drm.h file and save the external include.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Cc: Russell King <linux@armlinux.org.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20200609200446.153209-3-linus.walleij@linaro.org
+73
-91
-1
drivers/gpu/drm/pl111/pl111_debugfs.c
-1
drivers/gpu/drm/pl111/pl111_debugfs.c
-1
drivers/gpu/drm/pl111/pl111_display.c
-1
drivers/gpu/drm/pl111/pl111_display.c
+73
drivers/gpu/drm/pl111/pl111_drm.h
+73
drivers/gpu/drm/pl111/pl111_drm.h
···
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#include <drm/drm_panel.h>
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#include <drm/drm_simple_kms_helper.h>
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+
/*
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* CLCD Controller Internal Register addresses
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*/
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#define CLCD_TIM0 0x00000000
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#define CLCD_TIM1 0x00000004
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#define CLCD_TIM2 0x00000008
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#define CLCD_TIM3 0x0000000c
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#define CLCD_UBAS 0x00000010
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#define CLCD_LBAS 0x00000014
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+
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#define CLCD_PL110_IENB 0x00000018
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#define CLCD_PL110_CNTL 0x0000001c
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#define CLCD_PL110_STAT 0x00000020
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#define CLCD_PL110_INTR 0x00000024
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#define CLCD_PL110_UCUR 0x00000028
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#define CLCD_PL110_LCUR 0x0000002C
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+
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#define CLCD_PL111_CNTL 0x00000018
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#define CLCD_PL111_IENB 0x0000001c
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#define CLCD_PL111_RIS 0x00000020
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#define CLCD_PL111_MIS 0x00000024
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#define CLCD_PL111_ICR 0x00000028
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#define CLCD_PL111_UCUR 0x0000002c
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#define CLCD_PL111_LCUR 0x00000030
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+
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#define CLCD_PALL 0x00000200
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#define CLCD_PALETTE 0x00000200
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+
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#define TIM2_PCD_LO_MASK GENMASK(4, 0)
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#define TIM2_PCD_LO_BITS 5
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#define TIM2_CLKSEL (1 << 5)
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#define TIM2_ACB_MASK GENMASK(10, 6)
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#define TIM2_IVS (1 << 11)
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#define TIM2_IHS (1 << 12)
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#define TIM2_IPC (1 << 13)
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#define TIM2_IOE (1 << 14)
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#define TIM2_BCD (1 << 26)
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#define TIM2_PCD_HI_MASK GENMASK(31, 27)
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#define TIM2_PCD_HI_BITS 5
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#define TIM2_PCD_HI_SHIFT 27
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+
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#define CNTL_LCDEN (1 << 0)
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#define CNTL_LCDBPP1 (0 << 1)
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#define CNTL_LCDBPP2 (1 << 1)
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#define CNTL_LCDBPP4 (2 << 1)
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#define CNTL_LCDBPP8 (3 << 1)
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#define CNTL_LCDBPP16 (4 << 1)
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#define CNTL_LCDBPP16_565 (6 << 1)
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#define CNTL_LCDBPP16_444 (7 << 1)
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#define CNTL_LCDBPP24 (5 << 1)
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#define CNTL_LCDBW (1 << 4)
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#define CNTL_LCDTFT (1 << 5)
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#define CNTL_LCDMONO8 (1 << 6)
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#define CNTL_LCDDUAL (1 << 7)
80
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#define CNTL_BGR (1 << 8)
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#define CNTL_BEBO (1 << 9)
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#define CNTL_BEPO (1 << 10)
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#define CNTL_LCDPWR (1 << 11)
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#define CNTL_LCDVCOMP(x) ((x) << 12)
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#define CNTL_LDMAFIFOTIME (1 << 15)
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#define CNTL_WATERMARK (1 << 16)
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+
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/* ST Microelectronics variant bits */
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#define CNTL_ST_1XBPP_444 0x0
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#define CNTL_ST_1XBPP_5551 (1 << 17)
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#define CNTL_ST_1XBPP_565 (1 << 18)
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#define CNTL_ST_CDWID_12 0x0
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#define CNTL_ST_CDWID_16 (1 << 19)
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#define CNTL_ST_CDWID_18 (1 << 20)
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#define CNTL_ST_CDWID_24 ((1 << 19) | (1 << 20))
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#define CNTL_ST_CEAEN (1 << 21)
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#define CNTL_ST_LCDBPP24_PACKED (6 << 1)
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+
26
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#define CLCD_IRQ_NEXTBASE_UPDATE BIT(2)
27
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28
101
struct drm_minor;
-1
drivers/gpu/drm/pl111/pl111_drv.c
-1
drivers/gpu/drm/pl111/pl111_drv.c
-1
drivers/gpu/drm/pl111/pl111_versatile.c
-1
drivers/gpu/drm/pl111/pl111_versatile.c
-87
include/linux/amba/clcd-regs.h
-87
include/linux/amba/clcd-regs.h
···
1
-
/*
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* David A Rusling
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*
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* Copyright (C) 2001 ARM Limited
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
9
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*/
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#ifndef AMBA_CLCD_REGS_H
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#define AMBA_CLCD_REGS_H
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-
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/*
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* CLCD Controller Internal Register addresses
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*/
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#define CLCD_TIM0 0x00000000
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#define CLCD_TIM1 0x00000004
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#define CLCD_TIM2 0x00000008
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#define CLCD_TIM3 0x0000000c
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#define CLCD_UBAS 0x00000010
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#define CLCD_LBAS 0x00000014
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-
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#define CLCD_PL110_IENB 0x00000018
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#define CLCD_PL110_CNTL 0x0000001c
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#define CLCD_PL110_STAT 0x00000020
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#define CLCD_PL110_INTR 0x00000024
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#define CLCD_PL110_UCUR 0x00000028
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#define CLCD_PL110_LCUR 0x0000002C
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-
31
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#define CLCD_PL111_CNTL 0x00000018
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#define CLCD_PL111_IENB 0x0000001c
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#define CLCD_PL111_RIS 0x00000020
34
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#define CLCD_PL111_MIS 0x00000024
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#define CLCD_PL111_ICR 0x00000028
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#define CLCD_PL111_UCUR 0x0000002c
37
-
#define CLCD_PL111_LCUR 0x00000030
38
-
39
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#define CLCD_PALL 0x00000200
40
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#define CLCD_PALETTE 0x00000200
41
-
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#define TIM2_PCD_LO_MASK GENMASK(4, 0)
43
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#define TIM2_PCD_LO_BITS 5
44
-
#define TIM2_CLKSEL (1 << 5)
45
-
#define TIM2_ACB_MASK GENMASK(10, 6)
46
-
#define TIM2_IVS (1 << 11)
47
-
#define TIM2_IHS (1 << 12)
48
-
#define TIM2_IPC (1 << 13)
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#define TIM2_IOE (1 << 14)
50
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#define TIM2_BCD (1 << 26)
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#define TIM2_PCD_HI_MASK GENMASK(31, 27)
52
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#define TIM2_PCD_HI_BITS 5
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#define TIM2_PCD_HI_SHIFT 27
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-
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#define CNTL_LCDEN (1 << 0)
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#define CNTL_LCDBPP1 (0 << 1)
57
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#define CNTL_LCDBPP2 (1 << 1)
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#define CNTL_LCDBPP4 (2 << 1)
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#define CNTL_LCDBPP8 (3 << 1)
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#define CNTL_LCDBPP16 (4 << 1)
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#define CNTL_LCDBPP16_565 (6 << 1)
62
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#define CNTL_LCDBPP16_444 (7 << 1)
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#define CNTL_LCDBPP24 (5 << 1)
64
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#define CNTL_LCDBW (1 << 4)
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#define CNTL_LCDTFT (1 << 5)
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#define CNTL_LCDMONO8 (1 << 6)
67
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#define CNTL_LCDDUAL (1 << 7)
68
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#define CNTL_BGR (1 << 8)
69
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#define CNTL_BEBO (1 << 9)
70
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#define CNTL_BEPO (1 << 10)
71
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#define CNTL_LCDPWR (1 << 11)
72
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#define CNTL_LCDVCOMP(x) ((x) << 12)
73
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#define CNTL_LDMAFIFOTIME (1 << 15)
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#define CNTL_WATERMARK (1 << 16)
75
-
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/* ST Microelectronics variant bits */
77
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#define CNTL_ST_1XBPP_444 0x0
78
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#define CNTL_ST_1XBPP_5551 (1 << 17)
79
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#define CNTL_ST_1XBPP_565 (1 << 18)
80
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#define CNTL_ST_CDWID_12 0x0
81
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#define CNTL_ST_CDWID_16 (1 << 19)
82
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#define CNTL_ST_CDWID_18 (1 << 20)
83
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#define CNTL_ST_CDWID_24 ((1 << 19)|(1 << 20))
84
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#define CNTL_ST_CEAEN (1 << 21)
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#define CNTL_ST_LCDBPP24_PACKED (6 << 1)
86
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#endif /* AMBA_CLCD_REGS_H */