tjh.dev / kernel
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MIPS: remove CONFIG_DMA_COHERENT

We can just check for !CONFIG_DMA_NONCOHERENT instead and simplify things
a lot.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/19530/
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: David Daney <david.daney@cavium.com>
Cc: Kevin Cernekee <cernekee@gmail.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Tom Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: iommu@lists.linux-foundation.org
Cc: linux-mips@linux-mips.org

authored by

Christoph Hellwig and committed by
Paul Burton 7e4dbdc1 972dc3b7

+6 -24
-16
arch/mips/Kconfig
··· 666 666 select FW_ARC64 667 667 select BOOT_ELF64 668 668 select DEFAULT_SGI_PARTITION 669 - select DMA_COHERENT 670 669 select SYS_HAS_EARLY_PRINTK 671 670 select HW_HAS_PCI 672 671 select NR_CPUS_DEFAULT_64 ··· 742 743 config SIBYTE_CRHINE 743 744 bool "Sibyte BCM91120C-CRhine" 744 745 select BOOT_ELF32 745 - select DMA_COHERENT 746 746 select SIBYTE_BCM1120 747 747 select SWAP_IO_SPACE 748 748 select SYS_HAS_CPU_SB1 ··· 751 753 config SIBYTE_CARMEL 752 754 bool "Sibyte BCM91120x-Carmel" 753 755 select BOOT_ELF32 754 - select DMA_COHERENT 755 756 select SIBYTE_BCM1120 756 757 select SWAP_IO_SPACE 757 758 select SYS_HAS_CPU_SB1 ··· 760 763 config SIBYTE_CRHONE 761 764 bool "Sibyte BCM91125C-CRhone" 762 765 select BOOT_ELF32 763 - select DMA_COHERENT 764 766 select SIBYTE_BCM1125 765 767 select SWAP_IO_SPACE 766 768 select SYS_HAS_CPU_SB1 ··· 770 774 config SIBYTE_RHONE 771 775 bool "Sibyte BCM91125E-Rhone" 772 776 select BOOT_ELF32 773 - select DMA_COHERENT 774 777 select SIBYTE_BCM1125H 775 778 select SWAP_IO_SPACE 776 779 select SYS_HAS_CPU_SB1 ··· 779 784 config SIBYTE_SWARM 780 785 bool "Sibyte BCM91250A-SWARM" 781 786 select BOOT_ELF32 782 - select DMA_COHERENT 783 787 select HAVE_PATA_PLATFORM 784 788 select SIBYTE_SB1250 785 789 select SWAP_IO_SPACE ··· 791 797 config SIBYTE_LITTLESUR 792 798 bool "Sibyte BCM91250C2-LittleSur" 793 799 select BOOT_ELF32 794 - select DMA_COHERENT 795 800 select HAVE_PATA_PLATFORM 796 801 select SIBYTE_SB1250 797 802 select SWAP_IO_SPACE ··· 802 809 config SIBYTE_SENTOSA 803 810 bool "Sibyte BCM91250E-Sentosa" 804 811 select BOOT_ELF32 805 - select DMA_COHERENT 806 812 select SIBYTE_SB1250 807 813 select SWAP_IO_SPACE 808 814 select SYS_HAS_CPU_SB1 ··· 811 819 config SIBYTE_BIGSUR 812 820 bool "Sibyte BCM91480B-BigSur" 813 821 select BOOT_ELF32 814 - select DMA_COHERENT 815 822 select NR_CPUS_DEFAULT_4 816 823 select SIBYTE_BCM1x80 817 824 select SWAP_IO_SPACE ··· 887 896 select CEVT_R4K 888 897 select ARCH_HAS_PHYS_TO_DMA 889 898 select PHYS_ADDR_T_64BIT 890 - select DMA_COHERENT 891 899 select SYS_SUPPORTS_64BIT_KERNEL 892 900 select SYS_SUPPORTS_BIG_ENDIAN 893 901 select EDAC_SUPPORT ··· 935 945 select PHYS_ADDR_T_64BIT 936 946 select SYS_SUPPORTS_BIG_ENDIAN 937 947 select SYS_SUPPORTS_HIGHMEM 938 - select DMA_COHERENT 939 948 select NR_CPUS_DEFAULT_32 940 949 select CEVT_R4K 941 950 select CSRC_R4K ··· 962 973 select SYS_SUPPORTS_BIG_ENDIAN 963 974 select SYS_SUPPORTS_LITTLE_ENDIAN 964 975 select SYS_SUPPORTS_HIGHMEM 965 - select DMA_COHERENT 966 976 select NR_CPUS_DEFAULT_32 967 977 select CEVT_R4K 968 978 select CSRC_R4K ··· 980 992 bool "Para-Virtualized guest system" 981 993 select CEVT_R4K 982 994 select CSRC_R4K 983 - select DMA_COHERENT 984 995 select SYS_SUPPORTS_64BIT_KERNEL 985 996 select SYS_SUPPORTS_32BIT_KERNEL 986 997 select SYS_SUPPORTS_BIG_ENDIAN ··· 1104 1117 config DMA_PERDEV_COHERENT 1105 1118 bool 1106 1119 select DMA_MAYBE_COHERENT 1107 - 1108 - config DMA_COHERENT 1109 - bool 1110 1120 1111 1121 config DMA_NONCOHERENT 1112 1122 bool
+3 -3
arch/mips/include/asm/dma-coherence.h
··· 21 21 extern enum coherent_io_user_state coherentio; 22 22 extern int hw_coherentio; 23 23 #else 24 - #ifdef CONFIG_DMA_COHERENT 25 - #define coherentio IO_COHERENCE_ENABLED 26 - #else 24 + #ifdef CONFIG_DMA_NONCOHERENT 27 25 #define coherentio IO_COHERENCE_DISABLED 26 + #else 27 + #define coherentio IO_COHERENCE_ENABLED 28 28 #endif 29 29 #define hw_coherentio 0 30 30 #endif /* CONFIG_DMA_MAYBE_COHERENT */
+1 -2
arch/mips/include/asm/mach-generic/kmalloc.h
··· 2 2 #ifndef __ASM_MACH_GENERIC_KMALLOC_H 3 3 #define __ASM_MACH_GENERIC_KMALLOC_H 4 4 5 - 6 - #ifndef CONFIG_DMA_COHERENT 5 + #ifdef CONFIG_DMA_NONCOHERENT 7 6 /* 8 7 * Total overkill for most systems but need as a safe default. 9 8 * Set this one if any device in the system might do non-coherent DMA.
+2 -2
arch/mips/mti-malta/malta-setup.c
··· 227 227 } else 228 228 BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE; 229 229 230 - #ifdef CONFIG_DMA_COHERENT 230 + #ifndef CONFIG_DMA_NONCOHERENT 231 231 if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { 232 232 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; 233 233 pr_info("Enabled Bonito CPU coherency\n"); ··· 279 279 */ 280 280 enable_dma(4); 281 281 282 - #ifdef CONFIG_DMA_COHERENT 282 + #ifndef CONFIG_DMA_NONCOHERENT 283 283 if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO) 284 284 panic("Hardware DMA cache coherency not supported"); 285 285 #endif
-1
arch/mips/sibyte/Kconfig
··· 70 70 71 71 config SIBYTE_SB1xxx_SOC 72 72 bool 73 - select DMA_COHERENT 74 73 select IRQ_MIPS_CPU 75 74 select SWAP_IO_SPACE 76 75 select SYS_SUPPORTS_32BIT_KERNEL