tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/amd/display/dc/irq: Remove duplications of hpd_ack function from IRQ

The major of dcn and dce irqs share a copy-pasted collection
of copy-pasted function, which is: hpd_ack.

This patch removes the multiple copy-pasted by moving them to
the irq_service.c and make the irq_service's
calls the functions implemented by the irq_service.c
instead.

The hpd_ack function is replaced by hpd0_ack and hpd1_ack, the
required constants are also added.

The changes were not tested on actual hardware. I am only able
to verify that the changes keep the code compileable and do my
best to look repeatedly if I am not actually changing any code.

Signed-off-by: Sebastian Aguilera Novoa <saguileran@ime.usp.br>
Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Sebastian Aguilera Novoa and committed by
Alex Deucher 7e340d3c d8d47f73

+90 -489
+1 -28
drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
··· 37 37 38 38 #include "ivsrcid/ivsrcid_vislands30.h" 39 39 40 - static bool hpd_ack( 41 - struct irq_service *irq_service, 42 - const struct irq_source_info *info) 43 - { 44 - uint32_t addr = info->status_reg; 45 - uint32_t value = dm_read_reg(irq_service->ctx, addr); 46 - uint32_t current_status = 47 - get_reg_field_value( 48 - value, 49 - HPD0_DC_HPD_INT_STATUS, 50 - DC_HPD_SENSE_DELAYED); 51 - 52 - dal_irq_service_ack_generic(irq_service, info); 53 - 54 - value = dm_read_reg(irq_service->ctx, info->enable_reg); 55 - 56 - set_reg_field_value( 57 - value, 58 - current_status ? 0 : 1, 59 - HPD0_DC_HPD_INT_CONTROL, 60 - DC_HPD_INT_POLARITY); 61 - 62 - dm_write_reg(irq_service->ctx, info->enable_reg, value); 63 - 64 - return true; 65 - } 66 - 67 40 static struct irq_source_info_funcs hpd_irq_info_funcs = { 68 41 .set = NULL, 69 - .ack = hpd_ack 42 + .ack = hpd0_ack 70 43 }; 71 44 72 45 static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
+1 -30
drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
··· 46 46 47 47 #include "dc_types.h" 48 48 49 - static bool hpd_ack( 50 - struct irq_service *irq_service, 51 - const struct irq_source_info *info) 52 - { 53 - uint32_t addr = info->status_reg; 54 - uint32_t value = dm_read_reg(irq_service->ctx, addr); 55 - uint32_t current_status = 56 - get_reg_field_value( 57 - value, 58 - DC_HPD1_INT_STATUS, 59 - DC_HPD1_SENSE_DELAYED); 60 - 61 - dal_irq_service_ack_generic(irq_service, info); 62 - 63 - value = dm_read_reg(irq_service->ctx, info->enable_reg); 64 - 65 - set_reg_field_value( 66 - value, 67 - current_status ? 0 : 1, 68 - DC_HPD1_INT_CONTROL, 69 - DC_HPD1_INT_POLARITY); 70 - 71 - dm_write_reg(irq_service->ctx, info->enable_reg, value); 72 - 73 - return true; 74 - } 75 - 76 49 static struct irq_source_info_funcs hpd_irq_info_funcs = { 77 50 .set = NULL, 78 - .ack = hpd_ack 51 + .ack = hpd1_ack 79 52 }; 80 53 81 54 static struct irq_source_info_funcs hpd_rx_irq_info_funcs = { ··· 364 391 dce60_irq_construct(irq_service, init_data); 365 392 return irq_service; 366 393 } 367 - 368 -
+1 -30
drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
··· 37 37 38 38 #include "dc_types.h" 39 39 40 - static bool hpd_ack( 41 - struct irq_service *irq_service, 42 - const struct irq_source_info *info) 43 - { 44 - uint32_t addr = info->status_reg; 45 - uint32_t value = dm_read_reg(irq_service->ctx, addr); 46 - uint32_t current_status = 47 - get_reg_field_value( 48 - value, 49 - DC_HPD1_INT_STATUS, 50 - DC_HPD1_SENSE_DELAYED); 51 - 52 - dal_irq_service_ack_generic(irq_service, info); 53 - 54 - value = dm_read_reg(irq_service->ctx, info->enable_reg); 55 - 56 - set_reg_field_value( 57 - value, 58 - current_status ? 0 : 1, 59 - DC_HPD1_INT_CONTROL, 60 - DC_HPD1_INT_POLARITY); 61 - 62 - dm_write_reg(irq_service->ctx, info->enable_reg, value); 63 - 64 - return true; 65 - } 66 - 67 40 static struct irq_source_info_funcs hpd_irq_info_funcs = { 68 41 .set = NULL, 69 - .ack = hpd_ack 42 + .ack = hpd1_ack 70 43 }; 71 44 72 45 static struct irq_source_info_funcs hpd_rx_irq_info_funcs = { ··· 276 303 dce80_irq_construct(irq_service, init_data); 277 304 return irq_service; 278 305 } 279 - 280 -
+1 -28
drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
··· 129 129 } 130 130 } 131 131 132 - static bool hpd_ack( 133 - struct irq_service *irq_service, 134 - const struct irq_source_info *info) 135 - { 136 - uint32_t addr = info->status_reg; 137 - uint32_t value = dm_read_reg(irq_service->ctx, addr); 138 - uint32_t current_status = 139 - get_reg_field_value( 140 - value, 141 - HPD0_DC_HPD_INT_STATUS, 142 - DC_HPD_SENSE_DELAYED); 143 - 144 - dal_irq_service_ack_generic(irq_service, info); 145 - 146 - value = dm_read_reg(irq_service->ctx, info->enable_reg); 147 - 148 - set_reg_field_value( 149 - value, 150 - current_status ? 0 : 1, 151 - HPD0_DC_HPD_INT_CONTROL, 152 - DC_HPD_INT_POLARITY); 153 - 154 - dm_write_reg(irq_service->ctx, info->enable_reg, value); 155 - 156 - return true; 157 - } 158 - 159 132 static struct irq_source_info_funcs hpd_irq_info_funcs = { 160 133 .set = NULL, 161 - .ack = hpd_ack 134 + .ack = hpd0_ack 162 135 }; 163 136 164 137 static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
+1 -28
drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
··· 130 130 } 131 131 } 132 132 133 - static bool hpd_ack( 134 - struct irq_service *irq_service, 135 - const struct irq_source_info *info) 136 - { 137 - uint32_t addr = info->status_reg; 138 - uint32_t value = dm_read_reg(irq_service->ctx, addr); 139 - uint32_t current_status = 140 - get_reg_field_value( 141 - value, 142 - HPD0_DC_HPD_INT_STATUS, 143 - DC_HPD_SENSE_DELAYED); 144 - 145 - dal_irq_service_ack_generic(irq_service, info); 146 - 147 - value = dm_read_reg(irq_service->ctx, info->enable_reg); 148 - 149 - set_reg_field_value( 150 - value, 151 - current_status ? 0 : 1, 152 - HPD0_DC_HPD_INT_CONTROL, 153 - DC_HPD_INT_POLARITY); 154 - 155 - dm_write_reg(irq_service->ctx, info->enable_reg, value); 156 - 157 - return true; 158 - } 159 - 160 133 static struct irq_source_info_funcs hpd_irq_info_funcs = { 161 134 .set = NULL, 162 - .ack = hpd_ack 135 + .ack = hpd0_ack 163 136 }; 164 137 165 138 static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
+1 -28
drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
··· 80 80 } 81 81 } 82 82 83 - static bool hpd_ack( 84 - struct irq_service *irq_service, 85 - const struct irq_source_info *info) 86 - { 87 - uint32_t addr = info->status_reg; 88 - uint32_t value = dm_read_reg(irq_service->ctx, addr); 89 - uint32_t current_status = 90 - get_reg_field_value( 91 - value, 92 - HPD0_DC_HPD_INT_STATUS, 93 - DC_HPD_SENSE_DELAYED); 94 - 95 - dal_irq_service_ack_generic(irq_service, info); 96 - 97 - value = dm_read_reg(irq_service->ctx, info->enable_reg); 98 - 99 - set_reg_field_value( 100 - value, 101 - current_status ? 0 : 1, 102 - HPD0_DC_HPD_INT_CONTROL, 103 - DC_HPD_INT_POLARITY); 104 - 105 - dm_write_reg(irq_service->ctx, info->enable_reg, value); 106 - 107 - return true; 108 - } 109 - 110 83 static struct irq_source_info_funcs hpd_irq_info_funcs = { 111 84 .set = NULL, 112 - .ack = hpd_ack 85 + .ack = hpd0_ack 113 86 }; 114 87 115 88 static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
+1 -28
drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
··· 132 132 return DC_IRQ_SOURCE_INVALID; 133 133 } 134 134 135 - static bool hpd_ack( 136 - struct irq_service *irq_service, 137 - const struct irq_source_info *info) 138 - { 139 - uint32_t addr = info->status_reg; 140 - uint32_t value = dm_read_reg(irq_service->ctx, addr); 141 - uint32_t current_status = 142 - get_reg_field_value( 143 - value, 144 - HPD0_DC_HPD_INT_STATUS, 145 - DC_HPD_SENSE_DELAYED); 146 - 147 - dal_irq_service_ack_generic(irq_service, info); 148 - 149 - value = dm_read_reg(irq_service->ctx, info->enable_reg); 150 - 151 - set_reg_field_value( 152 - value, 153 - current_status ? 0 : 1, 154 - HPD0_DC_HPD_INT_CONTROL, 155 - DC_HPD_INT_POLARITY); 156 - 157 - dm_write_reg(irq_service->ctx, info->enable_reg, value); 158 - 159 - return true; 160 - } 161 - 162 135 static struct irq_source_info_funcs hpd_irq_info_funcs = { 163 136 .set = NULL, 164 - .ack = hpd_ack 137 + .ack = hpd0_ack 165 138 }; 166 139 167 140 static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
+1 -29
drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
··· 139 139 } 140 140 } 141 141 142 - static bool hpd_ack( 143 - struct irq_service *irq_service, 144 - const struct irq_source_info *info) 145 - { 146 - uint32_t addr = info->status_reg; 147 - uint32_t value = dm_read_reg(irq_service->ctx, addr); 148 - uint32_t current_status = 149 - get_reg_field_value( 150 - value, 151 - HPD0_DC_HPD_INT_STATUS, 152 - DC_HPD_SENSE_DELAYED); 153 - 154 - dal_irq_service_ack_generic(irq_service, info); 155 - 156 - value = dm_read_reg(irq_service->ctx, info->enable_reg); 157 - 158 - set_reg_field_value( 159 - value, 160 - current_status ? 0 : 1, 161 - HPD0_DC_HPD_INT_CONTROL, 162 - DC_HPD_INT_POLARITY); 163 - 164 - dm_write_reg(irq_service->ctx, info->enable_reg, value); 165 - 166 - return true; 167 - } 168 - 169 142 static struct irq_source_info_funcs hpd_irq_info_funcs = { 170 143 .set = NULL, 171 - .ack = hpd_ack 144 + .ack = hpd0_ack 172 145 }; 173 146 174 147 static struct irq_source_info_funcs hpd_rx_irq_info_funcs = { ··· 420 447 dcn30_irq_construct(irq_service, init_data); 421 448 return irq_service; 422 449 } 423 -
+1 -18
drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
··· 126 126 } 127 127 } 128 128 129 - static bool hpd_ack(struct irq_service *irq_service, const struct irq_source_info *info) 130 - { 131 - uint32_t addr = info->status_reg; 132 - uint32_t value = dm_read_reg(irq_service->ctx, addr); 133 - uint32_t current_status = get_reg_field_value(value, HPD0_DC_HPD_INT_STATUS, DC_HPD_SENSE_DELAYED); 134 - 135 - dal_irq_service_ack_generic(irq_service, info); 136 - 137 - value = dm_read_reg(irq_service->ctx, info->enable_reg); 138 - 139 - set_reg_field_value(value, current_status ? 0 : 1, HPD0_DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY); 140 - 141 - dm_write_reg(irq_service->ctx, info->enable_reg, value); 142 - 143 - return true; 144 - } 145 - 146 129 static struct irq_source_info_funcs hpd_irq_info_funcs = { 147 130 .set = NULL, 148 - .ack = hpd_ack 131 + .ack = hpd0_ack 149 132 }; 150 133 151 134 static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
+1 -18
drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
··· 77 77 } 78 78 } 79 79 80 - static bool hpd_ack(struct irq_service *irq_service, const struct irq_source_info *info) 81 - { 82 - uint32_t addr = info->status_reg; 83 - uint32_t value = dm_read_reg(irq_service->ctx, addr); 84 - uint32_t current_status = get_reg_field_value(value, HPD0_DC_HPD_INT_STATUS, DC_HPD_SENSE_DELAYED); 85 - 86 - dal_irq_service_ack_generic(irq_service, info); 87 - 88 - value = dm_read_reg(irq_service->ctx, info->enable_reg); 89 - 90 - set_reg_field_value(value, current_status ? 0 : 1, HPD0_DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY); 91 - 92 - dm_write_reg(irq_service->ctx, info->enable_reg, value); 93 - 94 - return true; 95 - } 96 - 97 80 static struct irq_source_info_funcs hpd_irq_info_funcs = { 98 81 .set = NULL, 99 - .ack = hpd_ack 82 + .ack = hpd0_ack 100 83 }; 101 84 102 85 static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
+1 -28
drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
··· 128 128 } 129 129 } 130 130 131 - static bool hpd_ack( 132 - struct irq_service *irq_service, 133 - const struct irq_source_info *info) 134 - { 135 - uint32_t addr = info->status_reg; 136 - uint32_t value = dm_read_reg(irq_service->ctx, addr); 137 - uint32_t current_status = 138 - get_reg_field_value( 139 - value, 140 - HPD0_DC_HPD_INT_STATUS, 141 - DC_HPD_SENSE_DELAYED); 142 - 143 - dal_irq_service_ack_generic(irq_service, info); 144 - 145 - value = dm_read_reg(irq_service->ctx, info->enable_reg); 146 - 147 - set_reg_field_value( 148 - value, 149 - current_status ? 0 : 1, 150 - HPD0_DC_HPD_INT_CONTROL, 151 - DC_HPD_INT_POLARITY); 152 - 153 - dm_write_reg(irq_service->ctx, info->enable_reg, value); 154 - 155 - return true; 156 - } 157 - 158 131 static struct irq_source_info_funcs hpd_irq_info_funcs = { 159 132 .set = NULL, 160 - .ack = hpd_ack 133 + .ack = hpd0_ack 161 134 }; 162 135 163 136 static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
+1 -28
drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
··· 130 130 } 131 131 } 132 132 133 - static bool hpd_ack( 134 - struct irq_service *irq_service, 135 - const struct irq_source_info *info) 136 - { 137 - uint32_t addr = info->status_reg; 138 - uint32_t value = dm_read_reg(irq_service->ctx, addr); 139 - uint32_t current_status = 140 - get_reg_field_value( 141 - value, 142 - HPD0_DC_HPD_INT_STATUS, 143 - DC_HPD_SENSE_DELAYED); 144 - 145 - dal_irq_service_ack_generic(irq_service, info); 146 - 147 - value = dm_read_reg(irq_service->ctx, info->enable_reg); 148 - 149 - set_reg_field_value( 150 - value, 151 - current_status ? 0 : 1, 152 - HPD0_DC_HPD_INT_CONTROL, 153 - DC_HPD_INT_POLARITY); 154 - 155 - dm_write_reg(irq_service->ctx, info->enable_reg, value); 156 - 157 - return true; 158 - } 159 - 160 133 static struct irq_source_info_funcs hpd_irq_info_funcs = { 161 134 .set = NULL, 162 - .ack = hpd_ack 135 + .ack = hpd0_ack 163 136 }; 164 137 165 138 static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
+1 -28
drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
··· 135 135 } 136 136 } 137 137 138 - static bool hpd_ack( 139 - struct irq_service *irq_service, 140 - const struct irq_source_info *info) 141 - { 142 - uint32_t addr = info->status_reg; 143 - uint32_t value = dm_read_reg(irq_service->ctx, addr); 144 - uint32_t current_status = 145 - get_reg_field_value( 146 - value, 147 - HPD0_DC_HPD_INT_STATUS, 148 - DC_HPD_SENSE_DELAYED); 149 - 150 - dal_irq_service_ack_generic(irq_service, info); 151 - 152 - value = dm_read_reg(irq_service->ctx, info->enable_reg); 153 - 154 - set_reg_field_value( 155 - value, 156 - current_status ? 0 : 1, 157 - HPD0_DC_HPD_INT_CONTROL, 158 - DC_HPD_INT_POLARITY); 159 - 160 - dm_write_reg(irq_service->ctx, info->enable_reg, value); 161 - 162 - return true; 163 - } 164 - 165 138 static struct irq_source_info_funcs hpd_irq_info_funcs = { 166 139 .set = NULL, 167 - .ack = hpd_ack 140 + .ack = hpd0_ack 168 141 }; 169 142 170 143 static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
+1 -28
drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
··· 129 129 } 130 130 } 131 131 132 - static bool hpd_ack( 133 - struct irq_service *irq_service, 134 - const struct irq_source_info *info) 135 - { 136 - uint32_t addr = info->status_reg; 137 - uint32_t value = dm_read_reg(irq_service->ctx, addr); 138 - uint32_t current_status = 139 - get_reg_field_value( 140 - value, 141 - HPD0_DC_HPD_INT_STATUS, 142 - DC_HPD_SENSE_DELAYED); 143 - 144 - dal_irq_service_ack_generic(irq_service, info); 145 - 146 - value = dm_read_reg(irq_service->ctx, info->enable_reg); 147 - 148 - set_reg_field_value( 149 - value, 150 - current_status ? 0 : 1, 151 - HPD0_DC_HPD_INT_CONTROL, 152 - DC_HPD_INT_POLARITY); 153 - 154 - dm_write_reg(irq_service->ctx, info->enable_reg, value); 155 - 156 - return true; 157 - } 158 - 159 132 static struct irq_source_info_funcs hpd_irq_info_funcs = { 160 133 .set = NULL, 161 - .ack = hpd_ack 134 + .ack = hpd0_ack 162 135 }; 163 136 164 137 static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
+1 -28
drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
··· 127 127 } 128 128 } 129 129 130 - static bool hpd_ack( 131 - struct irq_service *irq_service, 132 - const struct irq_source_info *info) 133 - { 134 - uint32_t addr = info->status_reg; 135 - uint32_t value = dm_read_reg(irq_service->ctx, addr); 136 - uint32_t current_status = 137 - get_reg_field_value( 138 - value, 139 - HPD0_DC_HPD_INT_STATUS, 140 - DC_HPD_SENSE_DELAYED); 141 - 142 - dal_irq_service_ack_generic(irq_service, info); 143 - 144 - value = dm_read_reg(irq_service->ctx, info->enable_reg); 145 - 146 - set_reg_field_value( 147 - value, 148 - current_status ? 0 : 1, 149 - HPD0_DC_HPD_INT_CONTROL, 150 - DC_HPD_INT_POLARITY); 151 - 152 - dm_write_reg(irq_service->ctx, info->enable_reg, value); 153 - 154 - return true; 155 - } 156 - 157 130 static struct irq_source_info_funcs hpd_irq_info_funcs = { 158 131 .set = NULL, 159 - .ack = hpd_ack 132 + .ack = hpd0_ack 160 133 }; 161 134 162 135 static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
+1 -28
drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
··· 106 106 } 107 107 } 108 108 109 - static bool hpd_ack( 110 - struct irq_service *irq_service, 111 - const struct irq_source_info *info) 112 - { 113 - uint32_t addr = info->status_reg; 114 - uint32_t value = dm_read_reg(irq_service->ctx, addr); 115 - uint32_t current_status = 116 - get_reg_field_value( 117 - value, 118 - HPD0_DC_HPD_INT_STATUS, 119 - DC_HPD_SENSE_DELAYED); 120 - 121 - dal_irq_service_ack_generic(irq_service, info); 122 - 123 - value = dm_read_reg(irq_service->ctx, info->enable_reg); 124 - 125 - set_reg_field_value( 126 - value, 127 - current_status ? 0 : 1, 128 - HPD0_DC_HPD_INT_CONTROL, 129 - DC_HPD_INT_POLARITY); 130 - 131 - dm_write_reg(irq_service->ctx, info->enable_reg, value); 132 - 133 - return true; 134 - } 135 - 136 109 static struct irq_source_info_funcs hpd_irq_info_funcs = { 137 110 .set = NULL, 138 - .ack = hpd_ack 111 + .ack = hpd0_ack 139 112 }; 140 113 141 114 static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
+1 -28
drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
··· 105 105 } 106 106 } 107 107 108 - static bool hpd_ack( 109 - struct irq_service *irq_service, 110 - const struct irq_source_info *info) 111 - { 112 - uint32_t addr = info->status_reg; 113 - uint32_t value = dm_read_reg(irq_service->ctx, addr); 114 - uint32_t current_status = 115 - get_reg_field_value( 116 - value, 117 - HPD0_DC_HPD_INT_STATUS, 118 - DC_HPD_SENSE_DELAYED); 119 - 120 - dal_irq_service_ack_generic(irq_service, info); 121 - 122 - value = dm_read_reg(irq_service->ctx, info->enable_reg); 123 - 124 - set_reg_field_value( 125 - value, 126 - current_status ? 0 : 1, 127 - HPD0_DC_HPD_INT_CONTROL, 128 - DC_HPD_INT_POLARITY); 129 - 130 - dm_write_reg(irq_service->ctx, info->enable_reg, value); 131 - 132 - return true; 133 - } 134 - 135 108 static struct irq_source_info_funcs hpd_irq_info_funcs = { 136 109 .set = NULL, 137 - .ack = hpd_ack 110 + .ack = hpd0_ack 138 111 }; 139 112 140 113 static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
+1 -28
drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
··· 109 109 } 110 110 } 111 111 112 - static bool hpd_ack( 113 - struct irq_service *irq_service, 114 - const struct irq_source_info *info) 115 - { 116 - uint32_t addr = info->status_reg; 117 - uint32_t value = dm_read_reg(irq_service->ctx, addr); 118 - uint32_t current_status = 119 - get_reg_field_value( 120 - value, 121 - HPD0_DC_HPD_INT_STATUS, 122 - DC_HPD_SENSE_DELAYED); 123 - 124 - dal_irq_service_ack_generic(irq_service, info); 125 - 126 - value = dm_read_reg(irq_service->ctx, info->enable_reg); 127 - 128 - set_reg_field_value( 129 - value, 130 - current_status ? 0 : 1, 131 - HPD0_DC_HPD_INT_CONTROL, 132 - DC_HPD_INT_POLARITY); 133 - 134 - dm_write_reg(irq_service->ctx, info->enable_reg, value); 135 - 136 - return true; 137 - } 138 - 139 112 static struct irq_source_info_funcs hpd_irq_info_funcs = { 140 113 .set = NULL, 141 - .ack = hpd_ack 114 + .ack = hpd0_ack 142 115 }; 143 116 144 117 static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
+64
drivers/gpu/drm/amd/display/dc/irq/irq_service.c
··· 41 41 #include "reg_helper.h" 42 42 #include "irq_service.h" 43 43 44 + //HPD0_DC_HPD_INT_STATUS 45 + #define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L 46 + #define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L 47 + #define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 48 + #define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 49 + //HPD1_DC_HPD_INT_STATUS 50 + #define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED_MASK 0x10 51 + #define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED__SHIFT 0x4 52 + #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK 0x100 53 + #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY__SHIFT 0x8 44 54 45 55 46 56 #define CTX \ ··· 186 176 irq_service, 187 177 src_id, 188 178 ext_id); 179 + } 180 + 181 + bool hpd0_ack( 182 + struct irq_service *irq_service, 183 + const struct irq_source_info *info) 184 + { 185 + uint32_t addr = info->status_reg; 186 + uint32_t value = dm_read_reg(irq_service->ctx, addr); 187 + uint32_t current_status = 188 + get_reg_field_value( 189 + value, 190 + HPD0_DC_HPD_INT_STATUS, 191 + DC_HPD_SENSE_DELAYED); 192 + 193 + dal_irq_service_ack_generic(irq_service, info); 194 + 195 + value = dm_read_reg(irq_service->ctx, info->enable_reg); 196 + 197 + set_reg_field_value( 198 + value, 199 + current_status ? 0 : 1, 200 + HPD0_DC_HPD_INT_CONTROL, 201 + DC_HPD_INT_POLARITY); 202 + 203 + dm_write_reg(irq_service->ctx, info->enable_reg, value); 204 + 205 + return true; 206 + } 207 + 208 + bool hpd1_ack( 209 + struct irq_service *irq_service, 210 + const struct irq_source_info *info) 211 + { 212 + uint32_t addr = info->status_reg; 213 + uint32_t value = dm_read_reg(irq_service->ctx, addr); 214 + uint32_t current_status = 215 + get_reg_field_value( 216 + value, 217 + DC_HPD1_INT_STATUS, 218 + DC_HPD1_SENSE_DELAYED); 219 + 220 + dal_irq_service_ack_generic(irq_service, info); 221 + 222 + value = dm_read_reg(irq_service->ctx, info->enable_reg); 223 + 224 + set_reg_field_value( 225 + value, 226 + current_status ? 0 : 1, 227 + DC_HPD1_INT_CONTROL, 228 + DC_HPD1_INT_POLARITY); 229 + 230 + dm_write_reg(irq_service->ctx, info->enable_reg, value); 231 + 232 + return true; 189 233 }
+8
drivers/gpu/drm/amd/display/dc/irq/irq_service.h
··· 82 82 const struct irq_source_info *info, 83 83 bool enable); 84 84 85 + bool hpd0_ack( 86 + struct irq_service *irq_service, 87 + const struct irq_source_info *info); 88 + 89 + bool hpd1_ack( 90 + struct irq_service *irq_service, 91 + const struct irq_source_info *info); 92 + 85 93 #endif