tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch '20220706154337.2026269-1-robert.foss@linaro.org' into clk-for-5.20
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Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
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Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
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$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250
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title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350
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maintainers:
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- Jonathan Marek <jonathan@marek.ca>
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description: |
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Qualcomm display clock control module which supports the clocks, resets and
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power domains on SM8150 and SM8250.
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power domains on SM8150/SM8250/SM8350.
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See also:
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dt-bindings/clock/qcom,dispcc-sm8150.h
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dt-bindings/clock/qcom,dispcc-sm8250.h
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dt-bindings/clock/qcom,dispcc-sm8350.h
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properties:
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compatible:
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- qcom,sc8180x-dispcc
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- qcom,sm8150-dispcc
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- qcom,sm8250-dispcc
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- qcom,sm8350-dispcc
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clocks:
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items:
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Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml
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Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,gpucc-sm8350.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Graphics Clock & Reset Controller Binding
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maintainers:
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- Robert Foss <robert.foss@linaro.org>
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description: |
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Qualcomm graphics clock control module which supports the clocks, resets and
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power domains on Qualcomm SoCs.
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See also:
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dt-bindings/clock/qcom,gpucc-sm8350.h
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properties:
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compatible:
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enum:
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- qcom,sm8350-gpucc
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clocks:
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items:
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- description: Board XO source
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- description: GPLL0 main branch source
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- description: GPLL0 div branch source
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sm8350.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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clock-controller@3d90000 {
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compatible = "qcom,sm8350-gpucc";
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reg = <0 0x03d90000 0 0x9000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_GPU_GPLL0_CLK_SRC>,
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<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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};
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...
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include/dt-bindings/clock/qcom,gpucc-sm8350.h
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include/dt-bindings/clock/qcom,gpucc-sm8350.h
···
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2022, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H
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#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H
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/* GPU_CC clocks */
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#define GPU_CC_AHB_CLK 0
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#define GPU_CC_CB_CLK 1
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#define GPU_CC_CRC_AHB_CLK 2
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#define GPU_CC_CX_APB_CLK 3
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#define GPU_CC_CX_GMU_CLK 4
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#define GPU_CC_CX_QDSS_AT_CLK 5
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#define GPU_CC_CX_QDSS_TRIG_CLK 6
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#define GPU_CC_CX_QDSS_TSCTR_CLK 7
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#define GPU_CC_CX_SNOC_DVM_CLK 8
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#define GPU_CC_CXO_AON_CLK 9
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#define GPU_CC_CXO_CLK 10
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#define GPU_CC_FREQ_MEASURE_CLK 11
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#define GPU_CC_GMU_CLK_SRC 12
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#define GPU_CC_GX_GMU_CLK 13
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#define GPU_CC_GX_QDSS_TSCTR_CLK 14
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#define GPU_CC_GX_VSENSE_CLK 15
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#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16
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#define GPU_CC_HUB_AHB_DIV_CLK_SRC 17
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#define GPU_CC_HUB_AON_CLK 18
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#define GPU_CC_HUB_CLK_SRC 19
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#define GPU_CC_HUB_CX_INT_CLK 20
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#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 21
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#define GPU_CC_MND1X_0_GFX3D_CLK 22
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#define GPU_CC_MND1X_1_GFX3D_CLK 23
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#define GPU_CC_PLL0 24
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#define GPU_CC_PLL1 25
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#define GPU_CC_SLEEP_CLK 26
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/* GPU_CC resets */
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#define GPUCC_GPU_CC_ACD_BCR 0
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#define GPUCC_GPU_CC_CB_BCR 1
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#define GPUCC_GPU_CC_CX_BCR 2
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#define GPUCC_GPU_CC_FAST_HUB_BCR 3
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#define GPUCC_GPU_CC_GFX3D_AON_BCR 4
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#define GPUCC_GPU_CC_GMU_BCR 5
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#define GPUCC_GPU_CC_GX_BCR 6
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#define GPUCC_GPU_CC_XO_BCR 7
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/* GPU_CC GDSCRs */
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#define GPU_CX_GDSC 0
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#define GPU_GX_GDSC 1
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#endif