dt-bindings: dmaengine: xilinx_dma: add optional xlnx,sg-length-width property

The width of the "length register" cannot be autodetected, and it is now
specified with a DT property. Add documentation for it.

Cc: Rob Herring <[e-mail]>
Cc: Mark Rutland <[e-mail]>
Cc: [e-mail]
Cc: Radhey Shyam Pandey <[e-mail]>
Signed-off-by: Andrea Merello <[e-mail]>
Reviewed-by: Radhey Shyam Pandey <[e-mail]>
Reviewed-by: Rob Herring <[e-mail]>
Signed-off-by: Vinod Koul <[e-mail]>

Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt

···
 - xlnx,include-sg: Tells configured for Scatter-mode in
 	the hardware.
 Optional properties for AXI DMA:
+- xlnx,sg-length-width: Should be set to the width in bits of the length
+	register as configured in h/w. Takes values {8...26}. If the property
+	is missing or invalid then the default value 23 is used. This is the
+	maximum value that is supported by all IP versions.
 - xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware.
 Optional properties for VDMA:
 - xlnx,flush-fsync: Tells which channel to Flush on Frame sync.