tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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* use 'unsigned long' as address supplied to au_write[bwl]() * remove two already unused and commented structures * added an ULL suffix to several address constants that use bits 35-32

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

authored by

Pete Popov and committed by
Ralf Baechle 7de8d232 9447cbfc

+32 -95
+32 -95
include/asm-mips/mach-au1x00/au1000.h
··· 60 60 mdelay(ms); 61 61 } 62 62 63 - void static inline au_writeb(u8 val, int reg) 63 + void static inline au_writeb(u8 val, unsigned long reg) 64 64 { 65 65 *(volatile u8 *)(reg) = val; 66 66 } 67 67 68 - void static inline au_writew(u16 val, int reg) 68 + void static inline au_writew(u16 val, unsigned long reg) 69 69 { 70 70 *(volatile u16 *)(reg) = val; 71 71 } 72 72 73 - void static inline au_writel(u32 val, int reg) 73 + void static inline au_writel(u32 val, unsigned long reg) 74 74 { 75 75 *(volatile u32 *)(reg) = val; 76 76 } 77 77 78 - static inline u8 au_readb(unsigned long port) 78 + static inline u8 au_readb(unsigned long reg) 79 79 { 80 - return (*(volatile u8 *)port); 80 + return (*(volatile u8 *)reg); 81 81 } 82 82 83 - static inline u16 au_readw(unsigned long port) 83 + static inline u16 au_readw(unsigned long reg) 84 84 { 85 - return (*(volatile u16 *)port); 85 + return (*(volatile u16 *)reg); 86 86 } 87 87 88 - static inline u32 au_readl(unsigned long port) 88 + static inline u32 au_readl(unsigned long reg) 89 89 { 90 - return (*(volatile u32 *)port); 90 + return (*(volatile u32 *)reg); 91 91 } 92 92 93 93 /* These next three functions should be a generic part of the MIPS ··· 181 181 #define MEM_SDSLEEP (0x0030) 182 182 #define MEM_SDSMCKE (0x0034) 183 183 184 - #ifndef ASSEMBLER 185 - /*typedef volatile struct 186 - { 187 - uint32 sdmode0; 188 - uint32 sdmode1; 189 - uint32 sdmode2; 190 - uint32 sdaddr0; 191 - uint32 sdaddr1; 192 - uint32 sdaddr2; 193 - uint32 sdrefcfg; 194 - uint32 sdautoref; 195 - uint32 sdwrmd0; 196 - uint32 sdwrmd1; 197 - uint32 sdwrmd2; 198 - uint32 sdsleep; 199 - uint32 sdsmcke; 200 - 201 - } AU1X00_SDRAM;*/ 202 - #endif 203 - 204 184 /* 205 185 * MEM_SDMODE register content definitions 206 186 */ ··· 266 286 #define MEM_SDSREF (0x08D0) 267 287 #define MEM_SDSLEEP MEM_SDSREF 268 288 269 - #ifndef ASSEMBLER 270 - /*typedef volatile struct 271 - { 272 - uint32 sdmode0; 273 - uint32 reserved0; 274 - uint32 sdmode1; 275 - uint32 reserved1; 276 - uint32 sdmode2; 277 - uint32 reserved2[3]; 278 - uint32 sdaddr0; 279 - uint32 reserved3; 280 - uint32 sdaddr1; 281 - uint32 reserved4; 282 - uint32 sdaddr2; 283 - uint32 reserved5[3]; 284 - uint32 sdconfiga; 285 - uint32 reserved6; 286 - uint32 sdconfigb; 287 - uint32 reserved7; 288 - uint32 sdstat; 289 - uint32 reserved8; 290 - uint32 sderraddr; 291 - uint32 reserved9; 292 - uint32 sdstride0; 293 - uint32 reserved10; 294 - uint32 sdstride1; 295 - uint32 reserved11; 296 - uint32 sdstride2; 297 - uint32 reserved12[3]; 298 - uint32 sdwrmd0; 299 - uint32 reserved13; 300 - uint32 sdwrmd1; 301 - uint32 reserved14; 302 - uint32 sdwrmd2; 303 - uint32 reserved15[11]; 304 - uint32 sdprecmd; 305 - uint32 reserved16; 306 - uint32 sdautoref; 307 - uint32 reserved17; 308 - uint32 sdsref; 309 - 310 - } AU1550_SDRAM;*/ 311 - #endif 312 289 #endif 313 290 314 291 /* ··· 302 365 #define SSI0_PHYS_ADDR 0x11600000 303 366 #define SSI1_PHYS_ADDR 0x11680000 304 367 #define SYS_PHYS_ADDR 0x11900000 305 - #define PCMCIA_IO_PHYS_ADDR 0xF00000000 306 - #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000 307 - #define PCMCIA_MEM_PHYS_ADDR 0xF80000000 368 + #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 369 + #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 370 + #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL 308 371 #endif 309 372 310 373 /********************************************************************/ ··· 336 399 #define UART3_PHYS_ADDR 0x11400000 337 400 #define GPIO2_PHYS_ADDR 0x11700000 338 401 #define SYS_PHYS_ADDR 0x11900000 339 - #define PCI_MEM_PHYS_ADDR 0x400000000 340 - #define PCI_IO_PHYS_ADDR 0x500000000 341 - #define PCI_CONFIG0_PHYS_ADDR 0x600000000 342 - #define PCI_CONFIG1_PHYS_ADDR 0x680000000 343 - #define PCMCIA_IO_PHYS_ADDR 0xF00000000 344 - #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000 345 - #define PCMCIA_MEM_PHYS_ADDR 0xF80000000 402 + #define PCI_MEM_PHYS_ADDR 0x400000000ULL 403 + #define PCI_IO_PHYS_ADDR 0x500000000ULL 404 + #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL 405 + #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL 406 + #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 407 + #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 408 + #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL 346 409 #endif 347 410 348 411 /********************************************************************/ ··· 379 442 #define GPIO2_PHYS_ADDR 0x11700000 380 443 #define SYS_PHYS_ADDR 0x11900000 381 444 #define LCD_PHYS_ADDR 0x15000000 382 - #define PCMCIA_IO_PHYS_ADDR 0xF00000000 383 - #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000 384 - #define PCMCIA_MEM_PHYS_ADDR 0xF80000000 445 + #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 446 + #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 447 + #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL 385 448 #endif 386 449 387 450 /***********************************************************************/ ··· 410 473 #define PSC1_PHYS_ADDR 0x11B00000 411 474 #define PSC2_PHYS_ADDR 0x10A00000 412 475 #define PSC3_PHYS_ADDR 0x10B00000 413 - #define PCI_MEM_PHYS_ADDR 0x400000000 414 - #define PCI_IO_PHYS_ADDR 0x500000000 415 - #define PCI_CONFIG0_PHYS_ADDR 0x600000000 416 - #define PCI_CONFIG1_PHYS_ADDR 0x680000000 417 - #define PCMCIA_IO_PHYS_ADDR 0xF00000000 418 - #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000 419 - #define PCMCIA_MEM_PHYS_ADDR 0xF80000000 476 + #define PCI_MEM_PHYS_ADDR 0x400000000ULL 477 + #define PCI_IO_PHYS_ADDR 0x500000000ULL 478 + #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL 479 + #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL 480 + #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 481 + #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 482 + #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL 420 483 #endif 421 484 422 485 /***********************************************************************/ ··· 437 500 #define DDMA_PHYS_ADDR 0x14002000 438 501 #define PSC0_PHYS_ADDR 0x11A00000 439 502 #define PSC1_PHYS_ADDR 0x11B00000 440 - #define PCMCIA_IO_PHYS_ADDR 0xF00000000 441 - #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000 442 - #define PCMCIA_MEM_PHYS_ADDR 0xF80000000 443 503 #define SD0_PHYS_ADDR 0x10600000 444 504 #define SD1_PHYS_ADDR 0x10680000 445 505 #define LCD_PHYS_ADDR 0x15000000 446 506 #define SWCNT_PHYS_ADDR 0x1110010C 447 507 #define MAEFE_PHYS_ADDR 0x14012000 448 508 #define MAEBE_PHYS_ADDR 0x14010000 509 + #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 510 + #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 511 + #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL 449 512 #endif 450 513 451 514