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linux
arm64: dts: qcom: sc7280: Add cpufreq hw node
Add cpufreq HW device node to scale 4-Silver/3-Gold/1-Gold+
cores on SC7280 SoCs.
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1618020280-5470-2-git-send-email-tdas@codeaurora.org
[bjorn: Dropped reg-names]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
authored by
Taniya Das
and committed by
Bjorn Andersson
7dbd121a
822c8f2a
+18
+18
arch/arm64/boot/dts/qcom/sc7280.dtsi
+18
arch/arm64/boot/dts/qcom/sc7280.dtsi
···
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&LITTLE_CPU_SLEEP_1
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&CLUSTER_SLEEP_0>;
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next-level-cache = <&L2_0>;
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+
qcom,freq-domain = <&cpufreq_hw 0>;
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#cooling-cells = <2>;
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L2_0: l2-cache {
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compatible = "cache";
···
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&LITTLE_CPU_SLEEP_1
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&CLUSTER_SLEEP_0>;
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next-level-cache = <&L2_100>;
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+
qcom,freq-domain = <&cpufreq_hw 0>;
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#cooling-cells = <2>;
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L2_100: l2-cache {
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compatible = "cache";
···
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&LITTLE_CPU_SLEEP_1
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&CLUSTER_SLEEP_0>;
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next-level-cache = <&L2_200>;
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+
qcom,freq-domain = <&cpufreq_hw 0>;
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#cooling-cells = <2>;
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L2_200: l2-cache {
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compatible = "cache";
···
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&LITTLE_CPU_SLEEP_1
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&CLUSTER_SLEEP_0>;
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next-level-cache = <&L2_300>;
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+
qcom,freq-domain = <&cpufreq_hw 0>;
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#cooling-cells = <2>;
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L2_300: l2-cache {
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compatible = "cache";
···
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&BIG_CPU_SLEEP_1
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&CLUSTER_SLEEP_0>;
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next-level-cache = <&L2_400>;
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+
qcom,freq-domain = <&cpufreq_hw 1>;
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#cooling-cells = <2>;
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L2_400: l2-cache {
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compatible = "cache";
···
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&BIG_CPU_SLEEP_1
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&CLUSTER_SLEEP_0>;
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next-level-cache = <&L2_500>;
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+
qcom,freq-domain = <&cpufreq_hw 1>;
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#cooling-cells = <2>;
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L2_500: l2-cache {
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compatible = "cache";
···
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&BIG_CPU_SLEEP_1
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&CLUSTER_SLEEP_0>;
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next-level-cache = <&L2_600>;
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+
qcom,freq-domain = <&cpufreq_hw 1>;
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#cooling-cells = <2>;
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L2_600: l2-cache {
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compatible = "cache";
···
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&BIG_CPU_SLEEP_1
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&CLUSTER_SLEEP_0>;
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next-level-cache = <&L2_700>;
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+
qcom,freq-domain = <&cpufreq_hw 1>;
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#cooling-cells = <2>;
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L2_700: l2-cache {
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compatible = "cache";
···
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clock-names = "xo";
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#clock-cells = <1>;
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};
1149
+
};
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+
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+
cpufreq_hw: cpufreq@18591000 {
1152
+
compatible = "qcom,cpufreq-epss";
1153
+
reg = <0 0x18591000 0 0x1000>,
1154
+
<0 0x18592000 0 0x1000>,
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+
<0 0x18593000 0 0x1000>;
1156
+
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
1157
+
clock-names = "xo", "alternate";
1158
+
#freq-domain-cells = <1>;
1157
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};
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1160
};
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1161