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dt-bindings: net: stmmac: Convert the binding to a schemas

Switch the STMMAC / Synopsys DesignWare MAC controller binding to a YAML
schema to enable the DT validation.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Rob Herring <robh@kernel.org>

authored by

Maxime Ripard and committed by
Rob Herring
7db3545a 7a47b908

+391 -178
+390
Documentation/devicetree/bindings/net/snps,dwmac.yaml
··· 1 + # SPDX-License-Identifier: GPL-2.0 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/net/snps,dwmac.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Synopsys DesignWare MAC Device Tree Bindings 8 + 9 + maintainers: 10 + - Alexandre Torgue <alexandre.torgue@st.com> 11 + - Giuseppe Cavallaro <peppe.cavallaro@st.com> 12 + - Jose Abreu <joabreu@synopsys.com> 13 + 14 + # Select every compatible, including the deprecated ones. This way, we 15 + # will be able to report a warning when we have that compatible, since 16 + # we will validate the node thanks to the select, but won't report it 17 + # as a valid value in the compatible property description 18 + select: 19 + properties: 20 + compatible: 21 + contains: 22 + enum: 23 + - snps,dwmac 24 + - snps,dwmac-3.50a 25 + - snps,dwmac-3.610 26 + - snps,dwmac-3.70a 27 + - snps,dwmac-3.710 28 + - snps,dwmac-4.00 29 + - snps,dwmac-4.10a 30 + - snps,dwxgmac 31 + - snps,dwxgmac-2.10 32 + 33 + # Deprecated 34 + - st,spear600-gmac 35 + 36 + required: 37 + - compatible 38 + 39 + properties: 40 + 41 + # We need to include all the compatibles from schemas that will 42 + # include that schemas, otherwise compatible won't validate for 43 + # those. 44 + compatible: 45 + contains: 46 + enum: 47 + - snps,dwmac 48 + - snps,dwmac-3.50a 49 + - snps,dwmac-3.610 50 + - snps,dwmac-3.70a 51 + - snps,dwmac-3.710 52 + - snps,dwmac-4.00 53 + - snps,dwmac-4.10a 54 + - snps,dwxgmac 55 + - snps,dwxgmac-2.10 56 + 57 + reg: 58 + maxItems: 1 59 + 60 + interrupts: 61 + minItems: 1 62 + maxItems: 3 63 + items: 64 + - description: Combined signal for various interrupt events 65 + - description: The interrupt to manage the remote wake-up packet detection 66 + - description: The interrupt that occurs when Rx exits the LPI state 67 + 68 + interrupt-names: 69 + minItems: 1 70 + maxItems: 3 71 + items: 72 + - const: macirq 73 + - const: eth_wake_irq 74 + - const: eth_lpi 75 + 76 + clocks: 77 + minItems: 1 78 + maxItems: 3 79 + items: 80 + - description: GMAC main clock 81 + - description: Peripheral registers interface clock 82 + - description: 83 + PTP reference clock. This clock is used for programming the 84 + Timestamp Addend Register. If not passed then the system 85 + clock will be used and this is fine on some platforms. 86 + 87 + clock-names: 88 + additionalItems: true 89 + contains: 90 + enum: 91 + - stmmaceth 92 + - pclk 93 + - ptp_ref 94 + 95 + resets: 96 + maxItems: 1 97 + description: 98 + MAC Reset signal. 99 + 100 + reset-names: 101 + const: stmmaceth 102 + 103 + snps,axi-config: 104 + $ref: /schemas/types.yaml#definitions/phandle 105 + description: 106 + AXI BUS Mode parameters. Phandle to a node that can contain the 107 + following properties 108 + * snps,lpi_en, enable Low Power Interface 109 + * snps,xit_frm, unlock on WoL 110 + * snps,wr_osr_lmt, max write outstanding req. limit 111 + * snps,rd_osr_lmt, max read outstanding req. limit 112 + * snps,kbbe, do not cross 1KiB boundary. 113 + * snps,blen, this is a vector of supported burst length. 114 + * snps,fb, fixed-burst 115 + * snps,mb, mixed-burst 116 + * snps,rb, rebuild INCRx Burst 117 + 118 + snps,mtl-rx-config: 119 + $ref: /schemas/types.yaml#definitions/phandle 120 + description: 121 + Multiple RX Queues parameters. Phandle to a node that can 122 + contain the following properties 123 + * snps,rx-queues-to-use, number of RX queues to be used in the 124 + driver 125 + * Choose one of these RX scheduling algorithms 126 + * snps,rx-sched-sp, Strict priority 127 + * snps,rx-sched-wsp, Weighted Strict priority 128 + * For each RX queue 129 + * Choose one of these modes 130 + * snps,dcb-algorithm, Queue to be enabled as DCB 131 + * snps,avb-algorithm, Queue to be enabled as AVB 132 + * snps,map-to-dma-channel, Channel to map 133 + * Specifiy specific packet routing 134 + * snps,route-avcp, AV Untagged Control packets 135 + * snps,route-ptp, PTP Packets 136 + * snps,route-dcbcp, DCB Control Packets 137 + * snps,route-up, Untagged Packets 138 + * snps,route-multi-broad, Multicast & Broadcast Packets 139 + * snps,priority, RX queue priority (Range 0x0 to 0xF) 140 + 141 + snps,mtl-tx-config: 142 + $ref: /schemas/types.yaml#definitions/phandle 143 + description: 144 + Multiple TX Queues parameters. Phandle to a node that can 145 + contain the following properties 146 + * snps,tx-queues-to-use, number of TX queues to be used in the 147 + driver 148 + * Choose one of these TX scheduling algorithms 149 + * snps,tx-sched-wrr, Weighted Round Robin 150 + * snps,tx-sched-wfq, Weighted Fair Queuing 151 + * snps,tx-sched-dwrr, Deficit Weighted Round Robin 152 + * snps,tx-sched-sp, Strict priority 153 + * For each TX queue 154 + * snps,weight, TX queue weight (if using a DCB weight 155 + algorithm) 156 + * Choose one of these modes 157 + * snps,dcb-algorithm, TX queue will be working in DCB 158 + * snps,avb-algorithm, TX queue will be working in AVB 159 + [Attention] Queue 0 is reserved for legacy traffic 160 + and so no AVB is available in this queue. 161 + * Configure Credit Base Shaper (if AVB Mode selected) 162 + * snps,send_slope, enable Low Power Interface 163 + * snps,idle_slope, unlock on WoL 164 + * snps,high_credit, max write outstanding req. limit 165 + * snps,low_credit, max read outstanding req. limit 166 + * snps,priority, TX queue priority (Range 0x0 to 0xF) 167 + 168 + snps,reset-gpio: 169 + maxItems: 1 170 + description: 171 + PHY Reset GPIO 172 + 173 + snps,reset-active-low: 174 + $ref: /schemas/types.yaml#definitions/flag 175 + description: 176 + Indicates that the PHY Reset is active low 177 + 178 + snps,reset-delays-us: 179 + allOf: 180 + - $ref: /schemas/types.yaml#definitions/uint32-array 181 + - minItems: 3 182 + maxItems: 3 183 + description: 184 + Triplet of delays. The 1st cell is reset pre-delay in micro 185 + seconds. The 2nd cell is reset pulse in micro seconds. The 3rd 186 + cell is reset post-delay in micro seconds. 187 + 188 + snps,aal: 189 + $ref: /schemas/types.yaml#definitions/flag 190 + description: 191 + Use Address-Aligned Beats 192 + 193 + snps,fixed-burst: 194 + $ref: /schemas/types.yaml#definitions/flag 195 + description: 196 + Program the DMA to use the fixed burst mode 197 + 198 + snps,mixed-burst: 199 + $ref: /schemas/types.yaml#definitions/flag 200 + description: 201 + Program the DMA to use the mixed burst mode 202 + 203 + snps,force_thresh_dma_mode: 204 + $ref: /schemas/types.yaml#definitions/flag 205 + description: 206 + Force DMA to use the threshold mode for both tx and rx 207 + 208 + snps,force_sf_dma_mode: 209 + $ref: /schemas/types.yaml#definitions/flag 210 + description: 211 + Force DMA to use the Store and Forward mode for both tx and 212 + rx. This flag is ignored if force_thresh_dma_mode is set. 213 + 214 + snps,en-tx-lpi-clockgating: 215 + $ref: /schemas/types.yaml#definitions/flag 216 + description: 217 + Enable gating of the MAC TX clock during TX low-power mode 218 + 219 + snps,multicast-filter-bins: 220 + $ref: /schemas/types.yaml#definitions/uint32 221 + description: 222 + Number of multicast filter hash bins supported by this device 223 + instance 224 + 225 + snps,perfect-filter-entries: 226 + $ref: /schemas/types.yaml#definitions/uint32 227 + description: 228 + Number of perfect filter entries supported by this device 229 + instance 230 + 231 + snps,ps-speed: 232 + $ref: /schemas/types.yaml#definitions/uint32 233 + description: 234 + Port selection speed that can be passed to the core when PCS 235 + is supported. For example, this is used in case of SGMII and 236 + MAC2MAC connection. 237 + 238 + mdio: 239 + type: object 240 + description: 241 + Creates and registers an MDIO bus. 242 + 243 + properties: 244 + compatible: 245 + const: snps,dwmac-mdio 246 + 247 + required: 248 + - compatible 249 + 250 + required: 251 + - compatible 252 + - reg 253 + - interrupts 254 + - interrupt-names 255 + - phy-connection-type 256 + 257 + dependencies: 258 + snps,reset-active-low: ["snps,reset-gpio"] 259 + snps,reset-delay-us: ["snps,reset-gpio"] 260 + 261 + allOf: 262 + - $ref: "ethernet-controller.yaml#" 263 + - if: 264 + properties: 265 + compatible: 266 + contains: 267 + enum: 268 + - snps,dwxgmac 269 + - snps,dwxgmac-2.10 270 + - st,spear600-gmac 271 + 272 + then: 273 + properties: 274 + snps,pbl: 275 + allOf: 276 + - $ref: /schemas/types.yaml#definitions/uint32 277 + - enum: [2, 4, 8] 278 + description: 279 + Programmable Burst Length (tx and rx) 280 + 281 + snps,txpbl: 282 + allOf: 283 + - $ref: /schemas/types.yaml#definitions/uint32 284 + - enum: [2, 4, 8] 285 + description: 286 + Tx Programmable Burst Length. If set, DMA tx will use this 287 + value rather than snps,pbl. 288 + 289 + snps,rxpbl: 290 + allOf: 291 + - $ref: /schemas/types.yaml#definitions/uint32 292 + - enum: [2, 4, 8] 293 + description: 294 + Rx Programmable Burst Length. If set, DMA rx will use this 295 + value rather than snps,pbl. 296 + 297 + snps,no-pbl-x8: 298 + $ref: /schemas/types.yaml#definitions/flag 299 + description: 300 + Don\'t multiply the pbl/txpbl/rxpbl values by 8. For core 301 + rev < 3.50, don\'t multiply the values by 4. 302 + 303 + - if: 304 + properties: 305 + compatible: 306 + contains: 307 + enum: 308 + - snps,dwmac-4.00 309 + - snps,dwmac-4.10a 310 + - snps,dwxgmac 311 + - snps,dwxgmac-2.10 312 + - st,spear600-gmac 313 + 314 + then: 315 + snps,tso: 316 + $ref: /schemas/types.yaml#definitions/flag 317 + description: 318 + Enables the TSO feature otherwise it will be managed by 319 + MAC HW capability register. 320 + 321 + examples: 322 + - | 323 + stmmac_axi_setup: stmmac-axi-config { 324 + snps,wr_osr_lmt = <0xf>; 325 + snps,rd_osr_lmt = <0xf>; 326 + snps,blen = <256 128 64 32 0 0 0>; 327 + }; 328 + 329 + mtl_rx_setup: rx-queues-config { 330 + snps,rx-queues-to-use = <1>; 331 + snps,rx-sched-sp; 332 + queue0 { 333 + snps,dcb-algorithm; 334 + snps,map-to-dma-channel = <0x0>; 335 + snps,priority = <0x0>; 336 + }; 337 + }; 338 + 339 + mtl_tx_setup: tx-queues-config { 340 + snps,tx-queues-to-use = <2>; 341 + snps,tx-sched-wrr; 342 + queue0 { 343 + snps,weight = <0x10>; 344 + snps,dcb-algorithm; 345 + snps,priority = <0x0>; 346 + }; 347 + 348 + queue1 { 349 + snps,avb-algorithm; 350 + snps,send_slope = <0x1000>; 351 + snps,idle_slope = <0x1000>; 352 + snps,high_credit = <0x3E800>; 353 + snps,low_credit = <0xFFC18000>; 354 + snps,priority = <0x1>; 355 + }; 356 + }; 357 + 358 + gmac0: ethernet@e0800000 { 359 + compatible = "snps,dwxgmac-2.10", "snps,dwxgmac"; 360 + reg = <0xe0800000 0x8000>; 361 + interrupt-parent = <&vic1>; 362 + interrupts = <24 23 22>; 363 + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; 364 + mac-address = [000000000000]; /* Filled in by U-Boot */ 365 + max-frame-size = <3800>; 366 + phy-connection-type = "gmii"; 367 + snps,multicast-filter-bins = <256>; 368 + snps,perfect-filter-entries = <128>; 369 + rx-fifo-depth = <16384>; 370 + tx-fifo-depth = <16384>; 371 + clocks = <&clock>; 372 + clock-names = "stmmaceth"; 373 + snps,axi-config = <&stmmac_axi_setup>; 374 + snps,mtl-rx-config = <&mtl_rx_setup>; 375 + snps,mtl-tx-config = <&mtl_tx_setup>; 376 + mdio0 { 377 + #address-cells = <1>; 378 + #size-cells = <0>; 379 + compatible = "snps,dwmac-mdio"; 380 + phy1: ethernet-phy@0 { 381 + reg = <0>; 382 + }; 383 + }; 384 + }; 385 + 386 + # FIXME: We should set it, but it would report all the generic 387 + # properties as additional properties. 388 + # additionalProperties: false 389 + 390 + ...
+1 -178
Documentation/devicetree/bindings/net/stmmac.txt
··· 1 - * STMicroelectronics 10/100/1000/2500/10000 Ethernet (GMAC/XGMAC) 2 - 3 - Required properties: 4 - - compatible: Should be "snps,dwmac-<ip_version>", "snps,dwmac" or 5 - "snps,dwxgmac-<ip_version>", "snps,dwxgmac". 6 - For backwards compatibility: "st,spear600-gmac" is also supported. 7 - - reg: Address and length of the register set for the device 8 - - interrupts: Should contain the STMMAC interrupts 9 - - interrupt-names: Should contain a list of interrupt names corresponding to 10 - the interrupts in the interrupts property, if available. 11 - Valid interrupt names are: 12 - - "macirq" (combined signal for various interrupt events) 13 - - "eth_wake_irq" (the interrupt to manage the remote wake-up packet detection) 14 - - "eth_lpi" (the interrupt that occurs when Rx exits the LPI state) 15 - - phy-mode: See ethernet.txt file in the same directory. 16 - - snps,reset-gpio gpio number for phy reset. 17 - - snps,reset-active-low boolean flag to indicate if phy reset is active low. 18 - - snps,reset-delays-us is triplet of delays 19 - The 1st cell is reset pre-delay in micro seconds. 20 - The 2nd cell is reset pulse in micro seconds. 21 - The 3rd cell is reset post-delay in micro seconds. 22 - 23 - Optional properties: 24 - - resets: Should contain a phandle to the STMMAC reset signal, if any 25 - - reset-names: Should contain the reset signal name "stmmaceth", if a 26 - reset phandle is given 27 - - max-frame-size: See ethernet.txt file in the same directory 28 - - clocks: If present, the first clock should be the GMAC main clock and 29 - the second clock should be peripheral's register interface clock. Further 30 - clocks may be specified in derived bindings. 31 - - clock-names: One name for each entry in the clocks property, the 32 - first one should be "stmmaceth" and the second one should be "pclk". 33 - - ptp_ref: this is the PTP reference clock; in case of the PTP is available 34 - this clock is used for programming the Timestamp Addend Register. If not 35 - passed then the system clock will be used and this is fine on some 36 - platforms. 37 - - tx-fifo-depth: See ethernet.txt file in the same directory 38 - - rx-fifo-depth: See ethernet.txt file in the same directory 39 - - snps,pbl Programmable Burst Length (tx and rx) 40 - - snps,txpbl Tx Programmable Burst Length. Only for GMAC and newer. 41 - If set, DMA tx will use this value rather than snps,pbl. 42 - - snps,rxpbl Rx Programmable Burst Length. Only for GMAC and newer. 43 - If set, DMA rx will use this value rather than snps,pbl. 44 - - snps,no-pbl-x8 Don't multiply the pbl/txpbl/rxpbl values by 8. 45 - For core rev < 3.50, don't multiply the values by 4. 46 - - snps,aal Address-Aligned Beats 47 - - snps,fixed-burst Program the DMA to use the fixed burst mode 48 - - snps,mixed-burst Program the DMA to use the mixed burst mode 49 - - snps,force_thresh_dma_mode Force DMA to use the threshold mode for 50 - both tx and rx 51 - - snps,force_sf_dma_mode Force DMA to use the Store and Forward 52 - mode for both tx and rx. This flag is 53 - ignored if force_thresh_dma_mode is set. 54 - - snps,en-tx-lpi-clockgating Enable gating of the MAC TX clock during 55 - TX low-power mode 56 - - snps,multicast-filter-bins: Number of multicast filter hash bins 57 - supported by this device instance 58 - - snps,perfect-filter-entries: Number of perfect filter entries supported 59 - by this device instance 60 - - snps,ps-speed: port selection speed that can be passed to the core when 61 - PCS is supported. For example, this is used in case of SGMII 62 - and MAC2MAC connection. 63 - - snps,tso: this enables the TSO feature otherwise it will be managed by 64 - MAC HW capability register. Only for GMAC4 and newer. 65 - - AXI BUS Mode parameters: below the list of all the parameters to program the 66 - AXI register inside the DMA module: 67 - - snps,lpi_en: enable Low Power Interface 68 - - snps,xit_frm: unlock on WoL 69 - - snps,wr_osr_lmt: max write outstanding req. limit 70 - - snps,rd_osr_lmt: max read outstanding req. limit 71 - - snps,kbbe: do not cross 1KiB boundary. 72 - - snps,blen: this is a vector of supported burst length. 73 - - snps,fb: fixed-burst 74 - - snps,mb: mixed-burst 75 - - snps,rb: rebuild INCRx Burst 76 - - mdio: with compatible = "snps,dwmac-mdio", create and register mdio bus. 77 - - Multiple RX Queues parameters: below the list of all the parameters to 78 - configure the multiple RX queues: 79 - - snps,rx-queues-to-use: number of RX queues to be used in the driver 80 - - Choose one of these RX scheduling algorithms: 81 - - snps,rx-sched-sp: Strict priority 82 - - snps,rx-sched-wsp: Weighted Strict priority 83 - - For each RX queue 84 - - Choose one of these modes: 85 - - snps,dcb-algorithm: Queue to be enabled as DCB 86 - - snps,avb-algorithm: Queue to be enabled as AVB 87 - - snps,map-to-dma-channel: Channel to map 88 - - Specifiy specific packet routing: 89 - - snps,route-avcp: AV Untagged Control packets 90 - - snps,route-ptp: PTP Packets 91 - - snps,route-dcbcp: DCB Control Packets 92 - - snps,route-up: Untagged Packets 93 - - snps,route-multi-broad: Multicast & Broadcast Packets 94 - - snps,priority: RX queue priority (Range: 0x0 to 0xF) 95 - - Multiple TX Queues parameters: below the list of all the parameters to 96 - configure the multiple TX queues: 97 - - snps,tx-queues-to-use: number of TX queues to be used in the driver 98 - - Choose one of these TX scheduling algorithms: 99 - - snps,tx-sched-wrr: Weighted Round Robin 100 - - snps,tx-sched-wfq: Weighted Fair Queuing 101 - - snps,tx-sched-dwrr: Deficit Weighted Round Robin 102 - - snps,tx-sched-sp: Strict priority 103 - - For each TX queue 104 - - snps,weight: TX queue weight (if using a DCB weight algorithm) 105 - - Choose one of these modes: 106 - - snps,dcb-algorithm: TX queue will be working in DCB 107 - - snps,avb-algorithm: TX queue will be working in AVB 108 - [Attention] Queue 0 is reserved for legacy traffic 109 - and so no AVB is available in this queue. 110 - - Configure Credit Base Shaper (if AVB Mode selected): 111 - - snps,send_slope: enable Low Power Interface 112 - - snps,idle_slope: unlock on WoL 113 - - snps,high_credit: max write outstanding req. limit 114 - - snps,low_credit: max read outstanding req. limit 115 - - snps,priority: TX queue priority (Range: 0x0 to 0xF) 116 - Examples: 117 - 118 - stmmac_axi_setup: stmmac-axi-config { 119 - snps,wr_osr_lmt = <0xf>; 120 - snps,rd_osr_lmt = <0xf>; 121 - snps,blen = <256 128 64 32 0 0 0>; 122 - }; 123 - 124 - mtl_rx_setup: rx-queues-config { 125 - snps,rx-queues-to-use = <1>; 126 - snps,rx-sched-sp; 127 - queue0 { 128 - snps,dcb-algorithm; 129 - snps,map-to-dma-channel = <0x0>; 130 - snps,priority = <0x0>; 131 - }; 132 - }; 133 - 134 - mtl_tx_setup: tx-queues-config { 135 - snps,tx-queues-to-use = <2>; 136 - snps,tx-sched-wrr; 137 - queue0 { 138 - snps,weight = <0x10>; 139 - snps,dcb-algorithm; 140 - snps,priority = <0x0>; 141 - }; 142 - 143 - queue1 { 144 - snps,avb-algorithm; 145 - snps,send_slope = <0x1000>; 146 - snps,idle_slope = <0x1000>; 147 - snps,high_credit = <0x3E800>; 148 - snps,low_credit = <0xFFC18000>; 149 - snps,priority = <0x1>; 150 - }; 151 - }; 152 - 153 - gmac0: ethernet@e0800000 { 154 - compatible = "st,spear600-gmac"; 155 - reg = <0xe0800000 0x8000>; 156 - interrupt-parent = <&vic1>; 157 - interrupts = <24 23 22>; 158 - interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; 159 - mac-address = [000000000000]; /* Filled in by U-Boot */ 160 - max-frame-size = <3800>; 161 - phy-mode = "gmii"; 162 - snps,multicast-filter-bins = <256>; 163 - snps,perfect-filter-entries = <128>; 164 - rx-fifo-depth = <16384>; 165 - tx-fifo-depth = <16384>; 166 - clocks = <&clock>; 167 - clock-names = "stmmaceth"; 168 - snps,axi-config = <&stmmac_axi_setup>; 169 - mdio0 { 170 - #address-cells = <1>; 171 - #size-cells = <0>; 172 - compatible = "snps,dwmac-mdio"; 173 - phy1: ethernet-phy@0 { 174 - }; 175 - }; 176 - snps,mtl-rx-config = <&mtl_rx_setup>; 177 - snps,mtl-tx-config = <&mtl_tx_setup>; 178 - }; 1 + This file has moved to snps,dwmac.yaml.