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dt-bindings: dsp: fsl: Add DSP core binding support
This describes the DSP device tree node.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20190821164730.7385-2-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
authored by
Daniel Baluta
and committed by
Mark Brown
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Documentation/devicetree/bindings/dsp/fsl,dsp.yaml
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Documentation/devicetree/bindings/dsp/fsl,dsp.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dsp/fsl,dsp.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP i.MX8 DSP core
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maintainers:
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- Daniel Baluta <daniel.baluta@nxp.com>
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description: |
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Some boards from i.MX8 family contain a DSP core used for
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advanced pre- and post- audio processing.
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properties:
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compatible:
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enum:
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- fsl,imx8qxp-dsp
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reg:
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description: Should contain register location and length
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clocks:
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items:
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- description: ipg clock
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- description: ocram clock
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- description: core clock
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clock-names:
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items:
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- const: ipg
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- const: ocram
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- const: core
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power-domains:
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description:
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List of phandle and PM domain specifier as documented in
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Documentation/devicetree/bindings/power/power_domain.txt
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maxItems: 4
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mboxes:
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description:
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List of <&phandle type channel> - 2 channels for TXDB, 2 channels for RXDB
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(see mailbox/fsl,mu.txt)
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maxItems: 4
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mbox-names:
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items:
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- const: txdb0
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- const: txdb1
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- const: rxdb0
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- const: rxdb1
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memory-region:
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description:
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phandle to a node describing reserved memory (System RAM memory)
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used by DSP (see bindings/reserved-memory/reserved-memory.txt)
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- power-domains
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- mboxes
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- mbox-names
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- memory-region
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examples:
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- |
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#include <dt-bindings/firmware/imx/rsrc.h>
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#include <dt-bindings/clock/imx8-clock.h>
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dsp@596e8000 {
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compatible = "fsl,imx8qxp-dsp";
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reg = <0x596e8000 0x88000>;
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clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,
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<&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
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<&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
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clock-names = "ipg", "ocram", "core";
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power-domains = <&pd IMX_SC_R_MU_13A>,
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<&pd IMX_SC_R_MU_13B>,
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<&pd IMX_SC_R_DSP>,
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<&pd IMX_SC_R_DSP_RAM>;
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mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1";
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mboxes = <&lsio_mu13 2 0>, <&lsio_mu13 2 1>, <&lsio_mu13 3 0>, <&lsio_mu13 3 1>;
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};