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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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kernel
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linux
[PATCH] ppc32: Fix MPC83xx IPIC external interrupt pending register offset
The pending registers for IRQ1-IRQ7 were pointing to the interrupt pending
register instead of the external one.
Signed-off-by: Tony Li <Tony.Li@freescale.com>
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
authored by Kumar Gala and committed by Linus Torvalds 7d681b23 340ea397
+7
-7
arch/ppc/syslib/ipic.c
+7
-7
arch/ppc/syslib/ipic.c
···
79
.prio_mask = 7,
80
},
81
[17] = {
82
-
.pend = IPIC_SIPNR_H,
83
.mask = IPIC_SEMSR,
84
.prio = IPIC_SMPRR_A,
85
.force = IPIC_SEFCR,
···
87
.prio_mask = 5,
88
},
89
[18] = {
90
-
.pend = IPIC_SIPNR_H,
91
.mask = IPIC_SEMSR,
92
.prio = IPIC_SMPRR_A,
93
.force = IPIC_SEFCR,
···
95
.prio_mask = 6,
96
},
97
[19] = {
98
-
.pend = IPIC_SIPNR_H,
99
.mask = IPIC_SEMSR,
100
.prio = IPIC_SMPRR_A,
101
.force = IPIC_SEFCR,
···
103
.prio_mask = 7,
104
},
105
[20] = {
106
-
.pend = IPIC_SIPNR_H,
107
.mask = IPIC_SEMSR,
108
.prio = IPIC_SMPRR_B,
109
.force = IPIC_SEFCR,
···
111
.prio_mask = 4,
112
},
113
[21] = {
114
-
.pend = IPIC_SIPNR_H,
115
.mask = IPIC_SEMSR,
116
.prio = IPIC_SMPRR_B,
117
.force = IPIC_SEFCR,
···
119
.prio_mask = 5,
120
},
121
[22] = {
122
-
.pend = IPIC_SIPNR_H,
123
.mask = IPIC_SEMSR,
124
.prio = IPIC_SMPRR_B,
125
.force = IPIC_SEFCR,
···
127
.prio_mask = 6,
128
},
129
[23] = {
130
-
.pend = IPIC_SIPNR_H,
131
.mask = IPIC_SEMSR,
132
.prio = IPIC_SMPRR_B,
133
.force = IPIC_SEFCR,
···
79
.prio_mask = 7,
80
},
81
[17] = {
82
+
.pend = IPIC_SEPNR,
83
.mask = IPIC_SEMSR,
84
.prio = IPIC_SMPRR_A,
85
.force = IPIC_SEFCR,
···
87
.prio_mask = 5,
88
},
89
[18] = {
90
+
.pend = IPIC_SEPNR,
91
.mask = IPIC_SEMSR,
92
.prio = IPIC_SMPRR_A,
93
.force = IPIC_SEFCR,
···
95
.prio_mask = 6,
96
},
97
[19] = {
98
+
.pend = IPIC_SEPNR,
99
.mask = IPIC_SEMSR,
100
.prio = IPIC_SMPRR_A,
101
.force = IPIC_SEFCR,
···
103
.prio_mask = 7,
104
},
105
[20] = {
106
+
.pend = IPIC_SEPNR,
107
.mask = IPIC_SEMSR,
108
.prio = IPIC_SMPRR_B,
109
.force = IPIC_SEFCR,
···
111
.prio_mask = 4,
112
},
113
[21] = {
114
+
.pend = IPIC_SEPNR,
115
.mask = IPIC_SEMSR,
116
.prio = IPIC_SMPRR_B,
117
.force = IPIC_SEFCR,
···
119
.prio_mask = 5,
120
},
121
[22] = {
122
+
.pend = IPIC_SEPNR,
123
.mask = IPIC_SEMSR,
124
.prio = IPIC_SMPRR_B,
125
.force = IPIC_SEFCR,
···
127
.prio_mask = 6,
128
},
129
[23] = {
130
+
.pend = IPIC_SEPNR,
131
.mask = IPIC_SEMSR,
132
.prio = IPIC_SMPRR_B,
133
.force = IPIC_SEFCR,