···11+/*22+ * Copyright (c) 2015 MediaTek Inc.33+ * Author: Mars.C <mars.cheng@mediatek.com>44+ *55+ * This program is free software; you can redistribute it and/or modify66+ * it under the terms of the GNU General Public License version 2 as77+ * published by the Free Software Foundation.88+ *99+ * This program is distributed in the hope that it will be useful,1010+ * but WITHOUT ANY WARRANTY; without even the implied warranty of1111+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the1212+ * GNU General Public License for more details.1313+ */1414+1515+/dts-v1/;1616+#include "mt6580.dtsi"1717+1818+/ {1919+ model = "MediaTek MT6580 evaluation board";2020+ compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";2121+2222+ aliases {2323+ serial0 = &uart0;2424+ serial1 = &uart1;2525+ };2626+2727+ chosen {2828+ stdout-path = "serial0:921600n8";2929+ };3030+3131+ memory {3232+ reg = <0x80000000 0x20000000>;3333+ };3434+};3535+3636+&uart0 {3737+ status = "okay";3838+};
+116
arch/arm/boot/dts/mt6580.dtsi
···11+/*22+ * Copyright (c) 2015 MediaTek Inc.33+ * Author: Mars.C <mars.cheng@mediatek.com>44+ *55+ * This program is free software; you can redistribute it and/or modify66+ * it under the terms of the GNU General Public License version 2 as77+ * published by the Free Software Foundation.88+ *99+ * This program is distributed in the hope that it will be useful,1010+ * but WITHOUT ANY WARRANTY; without even the implied warranty of1111+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the1212+ * GNU General Public License for more details.1313+ */1414+1515+#include <dt-bindings/interrupt-controller/irq.h>1616+#include <dt-bindings/interrupt-controller/arm-gic.h>1717+#include "skeleton.dtsi"1818+1919+/ {2020+ compatible = "mediatek,mt6580";2121+ #address-cells = <1>;2222+ #size-cells = <1>;2323+ interrupt-parent = <&sysirq>;2424+2525+ cpus {2626+ #address-cells = <1>;2727+ #size-cells = <0>;2828+2929+ cpu@0 {3030+ device_type = "cpu";3131+ compatible = "arm,cortex-a7";3232+ reg = <0x0>;3333+ };3434+ cpu@1 {3535+ device_type = "cpu";3636+ compatible = "arm,cortex-a7";3737+ reg = <0x1>;3838+ };3939+ cpu@2 {4040+ device_type = "cpu";4141+ compatible = "arm,cortex-a7";4242+ reg = <0x2>;4343+ };4444+ cpu@3 {4545+ device_type = "cpu";4646+ compatible = "arm,cortex-a7";4747+ reg = <0x3>;4848+ };4949+5050+ };5151+5252+ system_clk: dummy13m {5353+ compatible = "fixed-clock";5454+ clock-frequency = <13000000>;5555+ #clock-cells = <0>;5656+ };5757+5858+ rtc_clk: dummy32k {5959+ compatible = "fixed-clock";6060+ clock-frequency = <32000>;6161+ #clock-cells = <0>;6262+ };6363+6464+ uart_clk: dummy26m {6565+ compatible = "fixed-clock";6666+ clock-frequency = <26000000>;6767+ #clock-cells = <0>;6868+ };6969+7070+ timer: timer@10008000 {7171+ compatible = "mediatek,mt6580-timer",7272+ "mediatek,mt6577-timer";7373+ reg = <0x10008000 0x80>;7474+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;7575+ clocks = <&system_clk>, <&rtc_clk>;7676+ clock-names = "system-clk", "rtc-clk";7777+ };7878+7979+ sysirq: interrupt-controller@10200100 {8080+ compatible = "mediatek,mt6580-sysirq",8181+ "mediatek,mt6577-sysirq";8282+ interrupt-controller;8383+ #interrupt-cells = <3>;8484+ interrupt-parent = <&gic>;8585+ reg = <0x10200100 0x1c>;8686+ };8787+8888+ gic: interrupt-controller@10211000 {8989+ compatible = "arm,cortex-a7-gic";9090+ interrupt-controller;9191+ #interrupt-cells = <3>;9292+ interrupt-parent = <&gic>;9393+ reg = <0x10211000 0x1000>,9494+ <0x10212000 0x1000>,9595+ <0x10214000 0x2000>,9696+ <0x10216000 0x2000>;9797+ };9898+9999+ uart0: serial@11005000 {100100+ compatible = "mediatek,mt6580-uart",101101+ "mediatek,mt6577-uart";102102+ reg = <0x11005000 0x400>;103103+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;104104+ clocks = <&uart_clk>;105105+ status = "disabled";106106+ };107107+108108+ uart1: serial@11006000 {109109+ compatible = "mediatek,mt6580-uart",110110+ "mediatek,mt6577-uart";111111+ reg = <0x11006000 0x400>;112112+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;113113+ clocks = <&uart_clk>;114114+ status = "disabled";115115+ };116116+};