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ARM: dts: qcom: sdx55-fn980: Enable PCIe EP

Enable PCIe Endpoint controller on the Telit FN980 TLB board based
on Qualcomm SDX55 platform.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211126070520.28979-5-manivannan.sadhasivam@linaro.org

authored by

Manivannan Sadhasivam and committed by
Bjorn Andersson
7cecfb53 e6b69813

+46
+46
arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts
··· 243 243 vdda-pll-supply = <&vreg_l4e_bb_0p875>; 244 244 }; 245 245 246 + &pcie_ep { 247 + status = "okay"; 248 + 249 + pinctrl-names = "default"; 250 + pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default 251 + &pcie_ep_wake_default>; 252 + }; 253 + 246 254 &qpic_bam { 247 255 status = "ok"; 248 256 }; ··· 273 265 &remoteproc_mpss { 274 266 status = "okay"; 275 267 memory-region = <&mpss_adsp_mem>; 268 + }; 269 + 270 + &tlmm { 271 + pcie_ep_clkreq_default: pcie_ep_clkreq_default { 272 + mux { 273 + pins = "gpio56"; 274 + function = "pcie_clkreq"; 275 + }; 276 + config { 277 + pins = "gpio56"; 278 + drive-strength = <2>; 279 + bias-disable; 280 + }; 281 + }; 282 + 283 + pcie_ep_perst_default: pcie_ep_perst_default { 284 + mux { 285 + pins = "gpio57"; 286 + function = "gpio"; 287 + }; 288 + config { 289 + pins = "gpio57"; 290 + drive-strength = <2>; 291 + bias-pull-down; 292 + }; 293 + }; 294 + 295 + pcie_ep_wake_default: pcie_ep_wake_default { 296 + mux { 297 + pins = "gpio53"; 298 + function = "gpio"; 299 + }; 300 + config { 301 + pins = "gpio53"; 302 + drive-strength = <2>; 303 + bias-disable; 304 + }; 305 + }; 276 306 }; 277 307 278 308 &usb_hsphy {