tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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drm/amdgpu/ih: store the full context id

The contextID field (formerly known as src_data) of the IH
vector stores client specific information about an interrupt.
It was expanded from 32 bits to 128 on newer asics. Expand the
src_id field to handle this.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Alex Deucher 7ccf5aa8 d766e6a3

+38 -36
+3 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
··· 50 50 dma_addr_t rb_dma_addr; /* only used when use_bus_addr = true */ 51 51 }; 52 52 53 + #define AMDGPU_IH_SRC_DATA_MAX_SIZE_DW 4 54 + 53 55 struct amdgpu_iv_entry { 54 56 unsigned client_id; 55 57 unsigned src_id; 56 - unsigned src_data; 58 + unsigned src_data[AMDGPU_IH_SRC_DATA_MAX_SIZE_DW]; 57 59 unsigned ring_id; 58 60 unsigned vm_id; 59 61 unsigned vm_id_src;
+1 -1
drivers/gpu/drm/amd/amdgpu/cik_ih.c
··· 250 250 251 251 entry->client_id = AMDGPU_IH_CLIENTID_LEGACY; 252 252 entry->src_id = dw[0] & 0xff; 253 - entry->src_data = dw[1] & 0xfffffff; 253 + entry->src_data[0] = dw[1] & 0xfffffff; 254 254 entry->ring_id = dw[2] & 0xff; 255 255 entry->vm_id = (dw[2] >> 8) & 0xff; 256 256 entry->pas_id = (dw[2] >> 16) & 0xffff;
+1 -1
drivers/gpu/drm/amd/amdgpu/cz_ih.c
··· 229 229 230 230 entry->client_id = AMDGPU_IH_CLIENTID_LEGACY; 231 231 entry->src_id = dw[0] & 0xff; 232 - entry->src_data = dw[1] & 0xfffffff; 232 + entry->src_data[0] = dw[1] & 0xfffffff; 233 233 entry->ring_id = dw[2] & 0xff; 234 234 entry->vm_id = (dw[2] >> 8) & 0xff; 235 235 entry->pas_id = (dw[2] >> 16) & 0xffff;
+5 -5
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
··· 3398 3398 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 3399 3399 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); 3400 3400 3401 - switch (entry->src_data) { 3401 + switch (entry->src_data[0]) { 3402 3402 case 0: /* vblank */ 3403 3403 if (disp_int & interrupt_status_offsets[crtc].vblank) 3404 3404 dce_v10_0_crtc_vblank_int_ack(adev, crtc); ··· 3421 3421 3422 3422 break; 3423 3423 default: 3424 - DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3424 + DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3425 3425 break; 3426 3426 } 3427 3427 ··· 3435 3435 uint32_t disp_int, mask; 3436 3436 unsigned hpd; 3437 3437 3438 - if (entry->src_data >= adev->mode_info.num_hpd) { 3439 - DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3438 + if (entry->src_data[0] >= adev->mode_info.num_hpd) { 3439 + DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3440 3440 return 0; 3441 3441 } 3442 3442 3443 - hpd = entry->src_data; 3443 + hpd = entry->src_data[0]; 3444 3444 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3445 3445 mask = interrupt_status_offsets[hpd].hpd; 3446 3446
+5 -5
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
··· 3462 3462 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 3463 3463 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); 3464 3464 3465 - switch (entry->src_data) { 3465 + switch (entry->src_data[0]) { 3466 3466 case 0: /* vblank */ 3467 3467 if (disp_int & interrupt_status_offsets[crtc].vblank) 3468 3468 dce_v11_0_crtc_vblank_int_ack(adev, crtc); ··· 3485 3485 3486 3486 break; 3487 3487 default: 3488 - DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3488 + DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3489 3489 break; 3490 3490 } 3491 3491 ··· 3499 3499 uint32_t disp_int, mask; 3500 3500 unsigned hpd; 3501 3501 3502 - if (entry->src_data >= adev->mode_info.num_hpd) { 3503 - DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3502 + if (entry->src_data[0] >= adev->mode_info.num_hpd) { 3503 + DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3504 3504 return 0; 3505 3505 } 3506 3506 3507 - hpd = entry->src_data; 3507 + hpd = entry->src_data[0]; 3508 3508 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3509 3509 mask = interrupt_status_offsets[hpd].hpd; 3510 3510
+5 -5
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
··· 2592 2592 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 2593 2593 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); 2594 2594 2595 - switch (entry->src_data) { 2595 + switch (entry->src_data[0]) { 2596 2596 case 0: /* vblank */ 2597 2597 if (disp_int & interrupt_status_offsets[crtc].vblank) 2598 2598 WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK); ··· 2613 2613 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 2614 2614 break; 2615 2615 default: 2616 - DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 2616 + DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 2617 2617 break; 2618 2618 } 2619 2619 ··· 2703 2703 uint32_t disp_int, mask, tmp; 2704 2704 unsigned hpd; 2705 2705 2706 - if (entry->src_data >= adev->mode_info.num_hpd) { 2707 - DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 2706 + if (entry->src_data[0] >= adev->mode_info.num_hpd) { 2707 + DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 2708 2708 return 0; 2709 2709 } 2710 2710 2711 - hpd = entry->src_data; 2711 + hpd = entry->src_data[0]; 2712 2712 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 2713 2713 mask = interrupt_status_offsets[hpd].hpd; 2714 2714
+5 -5
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
··· 3159 3159 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 3160 3160 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); 3161 3161 3162 - switch (entry->src_data) { 3162 + switch (entry->src_data[0]) { 3163 3163 case 0: /* vblank */ 3164 3164 if (disp_int & interrupt_status_offsets[crtc].vblank) 3165 3165 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK); ··· 3180 3180 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3181 3181 break; 3182 3182 default: 3183 - DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3183 + DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3184 3184 break; 3185 3185 } 3186 3186 ··· 3270 3270 uint32_t disp_int, mask, tmp; 3271 3271 unsigned hpd; 3272 3272 3273 - if (entry->src_data >= adev->mode_info.num_hpd) { 3274 - DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3273 + if (entry->src_data[0] >= adev->mode_info.num_hpd) { 3274 + DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3275 3275 return 0; 3276 3276 } 3277 3277 3278 - hpd = entry->src_data; 3278 + hpd = entry->src_data[0]; 3279 3279 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3280 3280 mask = interrupt_status_offsets[hpd].hpd; 3281 3281
+1 -1
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
··· 1093 1093 1094 1094 if (printk_ratelimit()) { 1095 1095 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1096 - entry->src_id, entry->src_data); 1096 + entry->src_id, entry->src_data[0]); 1097 1097 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1098 1098 addr); 1099 1099 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
+1 -1
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
··· 1264 1264 1265 1265 if (printk_ratelimit()) { 1266 1266 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1267 - entry->src_id, entry->src_data); 1267 + entry->src_id, entry->src_data[0]); 1268 1268 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1269 1269 addr); 1270 1270 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
+2 -2
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
··· 1301 1301 1302 1302 if (amdgpu_sriov_vf(adev)) { 1303 1303 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1304 - entry->src_id, entry->src_data); 1304 + entry->src_id, entry->src_data[0]); 1305 1305 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n"); 1306 1306 return 0; 1307 1307 } ··· 1320 1320 1321 1321 if (printk_ratelimit()) { 1322 1322 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1323 - entry->src_id, entry->src_data); 1323 + entry->src_id, entry->src_data[0]); 1324 1324 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1325 1325 addr); 1326 1326 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
+1 -1
drivers/gpu/drm/amd/amdgpu/iceland_ih.c
··· 229 229 230 230 entry->client_id = AMDGPU_IH_CLIENTID_LEGACY; 231 231 entry->src_id = dw[0] & 0xff; 232 - entry->src_data = dw[1] & 0xfffffff; 232 + entry->src_data[0] = dw[1] & 0xfffffff; 233 233 entry->ring_id = dw[2] & 0xff; 234 234 entry->vm_id = (dw[2] >> 8) & 0xff; 235 235 entry->pas_id = (dw[2] >> 16) & 0xffff;
+1 -1
drivers/gpu/drm/amd/amdgpu/si_ih.c
··· 131 131 132 132 entry->client_id = AMDGPU_IH_CLIENTID_LEGACY; 133 133 entry->src_id = dw[0] & 0xff; 134 - entry->src_data = dw[1] & 0xfffffff; 134 + entry->src_data[0] = dw[1] & 0xfffffff; 135 135 entry->ring_id = dw[2] & 0xff; 136 136 entry->vm_id = (dw[2] >> 8) & 0xff; 137 137
+1 -1
drivers/gpu/drm/amd/amdgpu/tonga_ih.c
··· 240 240 241 241 entry->client_id = AMDGPU_IH_CLIENTID_LEGACY; 242 242 entry->src_id = dw[0] & 0xff; 243 - entry->src_data = dw[1] & 0xfffffff; 243 + entry->src_data[0] = dw[1] & 0xfffffff; 244 244 entry->ring_id = dw[2] & 0xff; 245 245 entry->vm_id = (dw[2] >> 8) & 0xff; 246 246 entry->pas_id = (dw[2] >> 16) & 0xffff;
+3 -3
drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
··· 560 560 struct amdgpu_iv_entry *entry) 561 561 { 562 562 DRM_DEBUG("IH: VCE\n"); 563 - switch (entry->src_data) { 563 + switch (entry->src_data[0]) { 564 564 case 0: 565 565 case 1: 566 - amdgpu_fence_process(&adev->vce.ring[entry->src_data]); 566 + amdgpu_fence_process(&adev->vce.ring[entry->src_data[0]]); 567 567 break; 568 568 default: 569 569 DRM_ERROR("Unhandled interrupt: %d %d\n", 570 - entry->src_id, entry->src_data); 570 + entry->src_id, entry->src_data[0]); 571 571 break; 572 572 } 573 573
+3 -3
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
··· 695 695 696 696 WREG32_FIELD(VCE_SYS_INT_STATUS, VCE_SYS_INT_TRAP_INTERRUPT_INT, 1); 697 697 698 - switch (entry->src_data) { 698 + switch (entry->src_data[0]) { 699 699 case 0: 700 700 case 1: 701 701 case 2: 702 - amdgpu_fence_process(&adev->vce.ring[entry->src_data]); 702 + amdgpu_fence_process(&adev->vce.ring[entry->src_data[0]]); 703 703 break; 704 704 default: 705 705 DRM_ERROR("Unhandled interrupt: %d %d\n", 706 - entry->src_id, entry->src_data); 706 + entry->src_id, entry->src_data[0]); 707 707 break; 708 708 } 709 709