tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/amd/display: Program ACP related register

- Setup the shift and mask of HDMI_ACP_SEND register
- Program the register in hdmi stream encoder
- Also update ACP register in azalia configuration

Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alan Liu <HaoPing.Liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Alan Liu and committed by
Alex Deucher 7c50a3e9 b3859b16

+31 -30
+11
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
··· 486 486 487 487 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, value); 488 488 489 + /* ACP Data - Supports AI */ 490 + value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA); 491 + 492 + set_reg_field_value( 493 + value, 494 + audio_info->flags.info.SUPPORT_AI, 495 + AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA, 496 + SUPPORTS_AI); 497 + 498 + AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA, value); 499 + 489 500 /* Audio Descriptors */ 490 501 /* pass through all formats */ 491 502 for (format_index = 0; format_index < AUDIO_FORMAT_CODE_COUNT;
+2 -1
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
··· 33 33 #define DC_LOGGER \ 34 34 enc110->base.ctx->logger 35 35 36 - 37 36 #define REG(reg)\ 38 37 (enc110->regs->reg) 39 38 ··· 633 634 HDMI_GC_CONT, 1, 634 635 HDMI_GC_SEND, 1, 635 636 HDMI_NULL_SEND, 1); 637 + 638 + REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0); 636 639 637 640 /* following belongs to audio */ 638 641 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
+6 -8
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h
··· 115 115 #define SE_SF(reg_name, field_name, post_fix)\ 116 116 .field_name = reg_name ## __ ## field_name ## post_fix 117 117 118 - #define SE_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\ 118 + #define SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh)\ 119 119 SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\ 120 120 SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC0_UPDATE, mask_sh),\ 121 121 SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC2_UPDATE, mask_sh),\ ··· 140 140 SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\ 141 141 SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\ 142 142 SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\ 143 + SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh),\ 143 144 SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\ 144 145 SE_SF(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\ 145 146 SE_SF(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\ ··· 203 202 SE_SF(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\ 204 203 SE_SF(DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh) 205 204 206 - #define SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh)\ 207 - SE_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) 208 - 209 - #define SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)\ 205 + #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\ 210 206 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\ 211 207 SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\ 212 208 SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\ ··· 225 227 SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\ 226 228 SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\ 227 229 SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\ 230 + SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh),\ 228 231 SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\ 229 232 SE_SF(DIG0_AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\ 230 233 SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\ ··· 286 287 SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\ 287 288 SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\ 288 289 SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh) 289 - 290 - #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\ 291 - SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) 292 290 293 291 #define SE_COMMON_MASK_SH_LIST_DCE80_100(mask_sh)\ 294 292 SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\ ··· 410 414 uint8_t HDMI_GC_SEND; 411 415 uint8_t HDMI_NULL_SEND; 412 416 uint8_t HDMI_DATA_SCRAMBLE_EN; 417 + uint8_t HDMI_ACP_SEND; 413 418 uint8_t HDMI_AUDIO_INFO_SEND; 414 419 uint8_t AFMT_AUDIO_INFO_UPDATE; 415 420 uint8_t HDMI_AUDIO_INFO_LINE; ··· 542 545 uint32_t HDMI_GC_SEND; 543 546 uint32_t HDMI_NULL_SEND; 544 547 uint32_t HDMI_DATA_SCRAMBLE_EN; 548 + uint32_t HDMI_ACP_SEND; 545 549 uint32_t HDMI_AUDIO_INFO_SEND; 546 550 uint32_t AFMT_AUDIO_INFO_UPDATE; 547 551 uint32_t HDMI_AUDIO_INFO_LINE;
+2 -1
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
··· 37 37 #define DC_LOGGER \ 38 38 enc1->base.ctx->logger 39 39 40 - 41 40 #define REG(reg)\ 42 41 (enc1->regs->reg) 43 42 ··· 595 596 HDMI_GC_CONT, 1, 596 597 HDMI_GC_SEND, 1, 597 598 HDMI_NULL_SEND, 1); 599 + 600 + REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0); 598 601 599 602 /* following belongs to audio */ 600 603 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
+2 -14
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
··· 194 194 #define SE_SF(reg_name, field_name, post_fix)\ 195 195 .field_name = reg_name ## __ ## field_name ## post_fix 196 196 197 - #define SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)\ 197 + #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\ 198 198 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\ 199 199 SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\ 200 200 SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\ ··· 211 211 SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\ 212 212 SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\ 213 213 SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\ 214 + SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh),\ 214 215 SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\ 215 216 SE_SF(DIG0_AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\ 216 217 SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\ ··· 339 338 SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\ 340 339 SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh),\ 341 340 SE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh) 342 - 343 - #if defined(CONFIG_DRM_AMD_DC_HDCP) 344 - #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\ 345 - SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh),\ 346 - SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh) 347 - #else 348 - #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\ 349 - SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) 350 - #endif 351 341 352 342 #define SE_COMMON_MASK_SH_LIST_DCN10(mask_sh)\ 353 343 SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\ ··· 578 586 579 587 struct dcn10_stream_encoder_shift { 580 588 SE_REG_FIELD_LIST_DCN1_0(uint8_t); 581 - #if defined(CONFIG_DRM_AMD_DC_HDCP) 582 589 uint8_t HDMI_ACP_SEND; 583 - #endif 584 590 SE_REG_FIELD_LIST_DCN2_0(uint8_t); 585 591 SE_REG_FIELD_LIST_DCN3_0(uint8_t); 586 592 SE_REG_FIELD_LIST_DCN3_2(uint8_t); ··· 587 597 588 598 struct dcn10_stream_encoder_mask { 589 599 SE_REG_FIELD_LIST_DCN1_0(uint32_t); 590 - #if defined(CONFIG_DRM_AMD_DC_HDCP) 591 600 uint32_t HDMI_ACP_SEND; 592 - #endif 593 601 SE_REG_FIELD_LIST_DCN2_0(uint32_t); 594 602 SE_REG_FIELD_LIST_DCN3_0(uint32_t); 595 603 SE_REG_FIELD_LIST_DCN3_2(uint32_t);
-1
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
··· 35 35 #define DC_LOGGER \ 36 36 enc1->base.ctx->logger 37 37 38 - 39 38 #define REG(reg)\ 40 39 (enc1->regs->reg) 41 40
+3 -1
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
··· 35 35 #define DC_LOGGER \ 36 36 enc1->base.ctx->logger 37 37 38 - 39 38 #define REG(reg)\ 40 39 (enc1->regs->reg) 41 40 ··· 650 651 HDMI_GC_CONT, 1, 651 652 HDMI_GC_SEND, 1, 652 653 HDMI_NULL_SEND, 1); 654 + 655 + /* Disable Audio Content Protection packet transmission */ 656 + REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0); 653 657 654 658 /* following belongs to audio */ 655 659 /* Enable Audio InfoFrame packet transmission. */
+2 -4
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h
··· 112 112 SRI(DIG_CLOCK_PATTERN, DIG, id) 113 113 114 114 115 - #define SE_COMMON_MASK_SH_LIST_DCN30_BASE(mask_sh)\ 115 + #define SE_COMMON_MASK_SH_LIST_DCN30(mask_sh)\ 116 116 SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\ 117 117 SE_SF(DP0_DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\ 118 118 SE_SF(DIG0_HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\ ··· 124 124 SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\ 125 125 SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\ 126 126 SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\ 127 + SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh),\ 127 128 SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\ 128 129 SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\ 129 130 SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\ ··· 273 272 SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_COMBINE, mask_sh),\ 274 273 SE_SF(DP0_DP_SEC_FRAMING4, DP_SST_SDP_SPLITTING, mask_sh),\ 275 274 SE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh) 276 - 277 - #define SE_COMMON_MASK_SH_LIST_DCN30(mask_sh)\ 278 - SE_COMMON_MASK_SH_LIST_DCN30_BASE(mask_sh) 279 275 280 276 void dcn30_dio_stream_encoder_construct( 281 277 struct dcn10_stream_encoder *enc1,
+1
drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
··· 30 30 31 31 #include "audio_types.h" 32 32 #include "hw_shared.h" 33 + #include "dc_link.h" 33 34 34 35 struct dc_bios; 35 36 struct dc_context;
+2
drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
··· 7486 7486 #define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x00000004 7487 7487 #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L 7488 7488 #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x00000009 7489 + #define HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x1000 7490 + #define HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc 7489 7491 #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003f0000L 7490 7492 #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x00000010 7491 7493 #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L