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Merge tag 'drm-intel-next-fixes-2019-04-25' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

- Use after free fix during GEM_CREATE when reporting back object size
- Icelake DP register programming order fix

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190425061312.GA2919@jlahtine-desk.ger.corp.intel.com

Dave Airlie 7c13e5cc 5a679286

+9 -11
+1 -1
drivers/gpu/drm/i915/i915_gem.c
··· 647 647 return ret; 648 648 649 649 *handle_p = handle; 650 - *size_p = obj->base.size; 650 + *size_p = size; 651 651 return 0; 652 652 } 653 653
+8 -10
drivers/gpu/drm/i915/intel_ddi.c
··· 2905 2905 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2906 2906 enum port port = dig_port->base.port; 2907 2907 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 2908 - i915_reg_t mg_regs[2] = { MG_DP_MODE(0, port), MG_DP_MODE(1, port) }; 2909 2908 u32 val; 2910 - int i; 2909 + int ln; 2911 2910 2912 2911 if (tc_port == PORT_TC_NONE) 2913 2912 return; 2914 2913 2915 - for (i = 0; i < ARRAY_SIZE(mg_regs); i++) { 2916 - val = I915_READ(mg_regs[i]); 2914 + for (ln = 0; ln < 2; ln++) { 2915 + val = I915_READ(MG_DP_MODE(ln, port)); 2917 2916 val |= MG_DP_MODE_CFG_TR2PWR_GATING | 2918 2917 MG_DP_MODE_CFG_TRPWR_GATING | 2919 2918 MG_DP_MODE_CFG_CLNPWR_GATING | 2920 2919 MG_DP_MODE_CFG_DIGPWR_GATING | 2921 2920 MG_DP_MODE_CFG_GAONPWR_GATING; 2922 - I915_WRITE(mg_regs[i], val); 2921 + I915_WRITE(MG_DP_MODE(ln, port), val); 2923 2922 } 2924 2923 2925 2924 val = I915_READ(MG_MISC_SUS0(tc_port)); ··· 2937 2938 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2938 2939 enum port port = dig_port->base.port; 2939 2940 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 2940 - i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) }; 2941 2941 u32 val; 2942 - int i; 2942 + int ln; 2943 2943 2944 2944 if (tc_port == PORT_TC_NONE) 2945 2945 return; 2946 2946 2947 - for (i = 0; i < ARRAY_SIZE(mg_regs); i++) { 2948 - val = I915_READ(mg_regs[i]); 2947 + for (ln = 0; ln < 2; ln++) { 2948 + val = I915_READ(MG_DP_MODE(ln, port)); 2949 2949 val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING | 2950 2950 MG_DP_MODE_CFG_TRPWR_GATING | 2951 2951 MG_DP_MODE_CFG_CLNPWR_GATING | 2952 2952 MG_DP_MODE_CFG_DIGPWR_GATING | 2953 2953 MG_DP_MODE_CFG_GAONPWR_GATING); 2954 - I915_WRITE(mg_regs[i], val); 2954 + I915_WRITE(MG_DP_MODE(ln, port), val); 2955 2955 } 2956 2956 2957 2957 val = I915_READ(MG_MISC_SUS0(tc_port));