Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/amd/powerplay: fix bug sclk/mclk level can't be set on vega10.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Rex Zhu and committed by
Alex Deucher
7b52db39 5784d5cc

+34 -33
+34 -33
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
··· 4189 4189 4190 4190 switch (type) { 4191 4191 case PP_SCLK: 4192 - if (data->registry_data.sclk_dpm_key_disabled) 4193 - break; 4194 - 4195 4192 for (i = 0; i < 32; i++) { 4196 4193 if (mask & (1 << i)) 4197 4194 break; 4198 4195 } 4196 + data->smc_state_table.gfx_boot_level = i; 4199 4197 4200 - PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter( 4201 - hwmgr->smumgr, 4202 - PPSMC_MSG_SetSoftMinGfxclkByIndex, 4203 - i), 4204 - "Failed to set soft min sclk index!", 4205 - return -1); 4198 + for (i = 31; i >= 0; i--) { 4199 + if (mask & (1 << i)) 4200 + break; 4201 + } 4202 + data->smc_state_table.gfx_max_level = i; 4203 + 4204 + PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), 4205 + "Failed to upload boot level to lowest!", 4206 + return -EINVAL); 4207 + 4208 + PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), 4209 + "Failed to upload dpm max level to highest!", 4210 + return -EINVAL); 4206 4211 break; 4207 4212 4208 4213 case PP_MCLK: 4209 - if (data->registry_data.mclk_dpm_key_disabled) 4210 - break; 4211 - 4212 4214 for (i = 0; i < 32; i++) { 4213 4215 if (mask & (1 << i)) 4214 4216 break; 4215 4217 } 4216 4218 4217 - PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter( 4218 - hwmgr->smumgr, 4219 - PPSMC_MSG_SetSoftMinUclkByIndex, 4220 - i), 4221 - "Failed to set soft min mclk index!", 4222 - return -1); 4219 + for (i = 0; i < 32; i++) { 4220 + if (mask & (1 << i)) 4221 + break; 4222 + } 4223 + data->smc_state_table.mem_boot_level = i; 4224 + 4225 + for (i = 31; i >= 0; i--) { 4226 + if (mask & (1 << i)) 4227 + break; 4228 + } 4229 + data->smc_state_table.mem_max_level = i; 4230 + 4231 + PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), 4232 + "Failed to upload boot level to lowest!", 4233 + return -EINVAL); 4234 + 4235 + PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), 4236 + "Failed to upload dpm max level to highest!", 4237 + return -EINVAL); 4238 + 4223 4239 break; 4224 4240 4225 4241 case PP_PCIE: 4226 - if (data->registry_data.pcie_dpm_key_disabled) 4227 - break; 4228 - 4229 - for (i = 0; i < 32; i++) { 4230 - if (mask & (1 << i)) 4231 - break; 4232 - } 4233 - 4234 - PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter( 4235 - hwmgr->smumgr, 4236 - PPSMC_MSG_SetMinLinkDpmByIndex, 4237 - i), 4238 - "Failed to set min pcie index!", 4239 - return -1); 4240 - break; 4241 4242 default: 4242 4243 break; 4243 4244 }