tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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Merge tag 'soc-fixes-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC fixes from Arnd Bergmann:
"The main changes are once more for the NXP i.MX platform, addressing
multiple regressions in recent devicetree updates for the i.MX8MM and
i.MX6ULL SoCs, a PCIe fix for i.MX9 and a MAINTAINERS file update to
disambiguate NXP i.MX SoCs from Sony IMX image sensors.

The stm32 platform devicetree files get some compatibility fixes for
the interrupt controller node.

Another compatibility fix is done for the Arm Morello platform's cache
controller node.

The code changes are all for firmware drivers, fixing kernel-side bugs
on the Arm FF-A and SCMI drivers"

* tag 'soc-fixes-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
arm64: dts: st: Use 128kB size for aliased GIC400 register access on stm32mp23 SoCs
arm64: dts: st: Adjust interrupt-controller for stm32mp23 SoCs
arm64: dts: st: Use 128kB size for aliased GIC400 register access on stm32mp21 SoCs
arm64: dts: st: Adjust interrupt-controller for stm32mp21 SoCs
arm64: dts: st: Use 128kB size for aliased GIC400 register access on stm32mp25 SoCs
arm64: dts: st: Adjust interrupt-controller for stm32mp25 SoCs
arm64: dts: imx8mm-verdin: Link reg_usdhc2_vqmmc to usdhc2
MAINTAINERS: add exclude for dt-bindings to imx entry
ARM: dts: opos6ul: add ksz8081 phy properties
arm64: dts: imx95: Correct the range of PCIe app-reg region
arm64: dts: imx8mp: configure GPU and NPU clocks in nominal DTSI
arm64: dts: morello: Fix-up cache nodes
firmware: arm_ffa: Skip Rx buffer ownership release if not acquired
firmware: arm_scmi: Fix timeout checks on polling path
firmware: arm_scmi: Balance device refcount when destroying devices

Linus Torvalds 7b26feb4 92a09c47

+90 -40
+1
MAINTAINERS
··· 2519 2519 F: arch/arm/boot/dts/nxp/imx/ 2520 2520 F: arch/arm/boot/dts/nxp/mxs/ 2521 2521 F: arch/arm64/boot/dts/freescale/ 2522 + X: Documentation/devicetree/bindings/media/i2c/ 2522 2523 X: arch/arm64/boot/dts/freescale/fsl-* 2523 2524 X: arch/arm64/boot/dts/freescale/qoriq-* 2524 2525 X: drivers/media/i2c/
+3
arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-opos6ul.dtsi
··· 40 40 reg = <1>; 41 41 interrupt-parent = <&gpio4>; 42 42 interrupts = <16 IRQ_TYPE_LEVEL_LOW>; 43 + micrel,led-mode = <1>; 44 + clocks = <&clks IMX6UL_CLK_ENET_REF>; 45 + clock-names = "rmii-ref"; 43 46 status = "okay"; 44 47 }; 45 48 };
+11 -11
arch/arm64/boot/dts/arm/morello.dtsi
··· 44 44 next-level-cache = <&l2_0>; 45 45 clocks = <&scmi_dvfs 0>; 46 46 47 - l2_0: l2-cache-0 { 47 + l2_0: l2-cache { 48 48 compatible = "cache"; 49 49 cache-level = <2>; 50 50 /* 8 ways set associative */ ··· 53 53 cache-sets = <2048>; 54 54 cache-unified; 55 55 next-level-cache = <&l3_0>; 56 - 57 - l3_0: l3-cache { 58 - compatible = "cache"; 59 - cache-level = <3>; 60 - cache-size = <0x100000>; 61 - cache-unified; 62 - }; 63 56 }; 64 57 }; 65 58 ··· 71 78 next-level-cache = <&l2_1>; 72 79 clocks = <&scmi_dvfs 0>; 73 80 74 - l2_1: l2-cache-1 { 81 + l2_1: l2-cache { 75 82 compatible = "cache"; 76 83 cache-level = <2>; 77 84 /* 8 ways set associative */ ··· 98 105 next-level-cache = <&l2_2>; 99 106 clocks = <&scmi_dvfs 1>; 100 107 101 - l2_2: l2-cache-2 { 108 + l2_2: l2-cache { 102 109 compatible = "cache"; 103 110 cache-level = <2>; 104 111 /* 8 ways set associative */ ··· 125 132 next-level-cache = <&l2_3>; 126 133 clocks = <&scmi_dvfs 1>; 127 134 128 - l2_3: l2-cache-3 { 135 + l2_3: l2-cache { 129 136 compatible = "cache"; 130 137 cache-level = <2>; 131 138 /* 8 ways set associative */ ··· 135 142 cache-unified; 136 143 next-level-cache = <&l3_0>; 137 144 }; 145 + }; 146 + 147 + l3_0: l3-cache { 148 + compatible = "cache"; 149 + cache-level = <3>; 150 + cache-size = <0x100000>; 151 + cache-unified; 138 152 }; 139 153 }; 140 154
+20 -5
arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
··· 144 144 startup-delay-us = <20000>; 145 145 }; 146 146 147 + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { 148 + compatible = "regulator-gpio"; 149 + pinctrl-names = "default"; 150 + pinctrl-0 = <&pinctrl_usdhc2_vsel>; 151 + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; 152 + regulator-max-microvolt = <3300000>; 153 + regulator-min-microvolt = <1800000>; 154 + states = <1800000 0x1>, 155 + <3300000 0x0>; 156 + regulator-name = "PMIC_USDHC_VSELECT"; 157 + vin-supply = <&reg_nvcc_sd>; 158 + }; 159 + 147 160 reserved-memory { 148 161 #address-cells = <2>; 149 162 #size-cells = <2>; ··· 282 269 "SODIMM_19", 283 270 "", 284 271 "", 285 - "", 272 + "PMIC_USDHC_VSELECT", 286 273 "", 287 274 "", 288 275 "", ··· 798 785 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; 799 786 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; 800 787 vmmc-supply = <&reg_usdhc2_vmmc>; 788 + vqmmc-supply = <&reg_usdhc2_vqmmc>; 801 789 }; 802 790 803 791 &wdog1 { ··· 1220 1206 <MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6>; /* SODIMM 76 */ 1221 1207 }; 1222 1208 1209 + pinctrl_usdhc2_vsel: usdhc2vselgrp { 1210 + fsl,pins = 1211 + <MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x10>; /* PMIC_USDHC_VSELECT */ 1212 + }; 1213 + 1223 1214 /* 1224 1215 * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the 1225 1216 * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here. 1226 1217 */ 1227 1218 pinctrl_usdhc2: usdhc2grp { 1228 1219 fsl,pins = 1229 - <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, 1230 1220 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */ 1231 1221 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */ 1232 1222 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */ ··· 1241 1223 1242 1224 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 1243 1225 fsl,pins = 1244 - <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, 1245 1226 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>, 1246 1227 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>, 1247 1228 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>, ··· 1251 1234 1252 1235 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1253 1236 fsl,pins = 1254 - <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, 1255 1237 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>, 1256 1238 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>, 1257 1239 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>, ··· 1262 1246 /* Avoid backfeeding with removed card power */ 1263 1247 pinctrl_usdhc2_sleep: usdhc2slpgrp { 1264 1248 fsl,pins = 1265 - <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x0>, 1266 1249 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0>, 1267 1250 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0>, 1268 1251 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0>,
+26
arch/arm64/boot/dts/freescale/imx8mp-nominal.dtsi
··· 24 24 fsl,operating-mode = "nominal"; 25 25 }; 26 26 27 + &gpu2d { 28 + assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>; 29 + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 30 + assigned-clock-rates = <800000000>; 31 + }; 32 + 33 + &gpu3d { 34 + assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, 35 + <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; 36 + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 37 + <&clk IMX8MP_SYS_PLL1_800M>; 38 + assigned-clock-rates = <800000000>, <800000000>; 39 + }; 40 + 27 41 &pgc_hdmimix { 28 42 assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>, 29 43 <&clk IMX8MP_CLK_HDMI_APB>; ··· 58 44 assigned-clock-parents = <&clk IMX8MP_SYS_PLL3_OUT>, 59 45 <&clk IMX8MP_SYS_PLL3_OUT>; 60 46 assigned-clock-rates = <600000000>, <300000000>; 47 + }; 48 + 49 + &pgc_mlmix { 50 + assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>, 51 + <&clk IMX8MP_CLK_ML_AXI>, 52 + <&clk IMX8MP_CLK_ML_AHB>; 53 + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 54 + <&clk IMX8MP_SYS_PLL1_800M>, 55 + <&clk IMX8MP_SYS_PLL1_800M>; 56 + assigned-clock-rates = <800000000>, 57 + <800000000>, 58 + <300000000>; 61 59 }; 62 60 63 61 &media_blk_ctrl {
+4 -4
arch/arm64/boot/dts/freescale/imx95.dtsi
··· 1626 1626 reg = <0 0x4c300000 0 0x10000>, 1627 1627 <0 0x60100000 0 0xfe00000>, 1628 1628 <0 0x4c360000 0 0x10000>, 1629 - <0 0x4c340000 0 0x2000>; 1629 + <0 0x4c340000 0 0x4000>; 1630 1630 reg-names = "dbi", "config", "atu", "app"; 1631 1631 ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>, 1632 1632 <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>; ··· 1673 1673 reg = <0 0x4c300000 0 0x10000>, 1674 1674 <0 0x4c360000 0 0x1000>, 1675 1675 <0 0x4c320000 0 0x1000>, 1676 - <0 0x4c340000 0 0x2000>, 1676 + <0 0x4c340000 0 0x4000>, 1677 1677 <0 0x4c370000 0 0x10000>, 1678 1678 <0x9 0 1 0>; 1679 1679 reg-names = "dbi","atu", "dbi2", "app", "dma", "addr_space"; ··· 1700 1700 reg = <0 0x4c380000 0 0x10000>, 1701 1701 <8 0x80100000 0 0xfe00000>, 1702 1702 <0 0x4c3e0000 0 0x10000>, 1703 - <0 0x4c3c0000 0 0x2000>; 1703 + <0 0x4c3c0000 0 0x4000>; 1704 1704 reg-names = "dbi", "config", "atu", "app"; 1705 1705 ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>, 1706 1706 <0x82000000 0 0x10000000 0xa 0x10000000 0 0x10000000>; ··· 1749 1749 reg = <0 0x4c380000 0 0x10000>, 1750 1750 <0 0x4c3e0000 0 0x1000>, 1751 1751 <0 0x4c3a0000 0 0x1000>, 1752 - <0 0x4c3c0000 0 0x2000>, 1752 + <0 0x4c3c0000 0 0x4000>, 1753 1753 <0 0x4c3f0000 0 0x10000>, 1754 1754 <0xa 0 1 0>; 1755 1755 reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space";
+4 -4
arch/arm64/boot/dts/st/stm32mp211.dtsi
··· 116 116 }; 117 117 118 118 intc: interrupt-controller@4ac10000 { 119 - compatible = "arm,cortex-a7-gic"; 119 + compatible = "arm,gic-400"; 120 120 reg = <0x4ac10000 0x0 0x1000>, 121 - <0x4ac20000 0x0 0x2000>, 122 - <0x4ac40000 0x0 0x2000>, 123 - <0x4ac60000 0x0 0x2000>; 121 + <0x4ac20000 0x0 0x20000>, 122 + <0x4ac40000 0x0 0x20000>, 123 + <0x4ac60000 0x0 0x20000>; 124 124 #interrupt-cells = <3>; 125 125 interrupt-controller; 126 126 };
+4 -5
arch/arm64/boot/dts/st/stm32mp231.dtsi
··· 1201 1201 }; 1202 1202 1203 1203 intc: interrupt-controller@4ac10000 { 1204 - compatible = "arm,cortex-a7-gic"; 1204 + compatible = "arm,gic-400"; 1205 1205 reg = <0x4ac10000 0x1000>, 1206 - <0x4ac20000 0x2000>, 1207 - <0x4ac40000 0x2000>, 1208 - <0x4ac60000 0x2000>; 1206 + <0x4ac20000 0x20000>, 1207 + <0x4ac40000 0x20000>, 1208 + <0x4ac60000 0x20000>; 1209 1209 #interrupt-cells = <3>; 1210 - #address-cells = <1>; 1211 1210 interrupt-controller; 1212 1211 }; 1213 1212 };
+4 -5
arch/arm64/boot/dts/st/stm32mp251.dtsi
··· 115 115 }; 116 116 117 117 intc: interrupt-controller@4ac00000 { 118 - compatible = "arm,cortex-a7-gic"; 118 + compatible = "arm,gic-400"; 119 119 #interrupt-cells = <3>; 120 - #address-cells = <1>; 121 120 interrupt-controller; 122 121 reg = <0x0 0x4ac10000 0x0 0x1000>, 123 - <0x0 0x4ac20000 0x0 0x2000>, 124 - <0x0 0x4ac40000 0x0 0x2000>, 125 - <0x0 0x4ac60000 0x0 0x2000>; 122 + <0x0 0x4ac20000 0x0 0x20000>, 123 + <0x0 0x4ac40000 0x0 0x20000>, 124 + <0x0 0x4ac60000 0x0 0x20000>; 126 125 }; 127 126 128 127 psci {
+2 -1
drivers/firmware/arm_ffa/driver.c
··· 299 299 import_uuid(&buf->uuid, (u8 *)&rx_buf->uuid); 300 300 } 301 301 302 - ffa_rx_release(); 302 + if (!(flags & PARTITION_INFO_GET_RETURN_COUNT_ONLY)) 303 + ffa_rx_release(); 303 304 304 305 mutex_unlock(&drv_info->rx_lock); 305 306
+3
drivers/firmware/arm_scmi/bus.c
··· 255 255 if (!dev) 256 256 return NULL; 257 257 258 + /* Drop the refcnt bumped implicitly by device_find_child */ 259 + put_device(dev); 260 + 258 261 return to_scmi_dev(dev); 259 262 } 260 263
+8 -5
drivers/firmware/arm_scmi/driver.c
··· 1248 1248 } 1249 1249 1250 1250 static bool scmi_xfer_done_no_timeout(struct scmi_chan_info *cinfo, 1251 - struct scmi_xfer *xfer, ktime_t stop) 1251 + struct scmi_xfer *xfer, ktime_t stop, 1252 + bool *ooo) 1252 1253 { 1253 1254 struct scmi_info *info = handle_to_scmi_info(cinfo->handle); 1254 1255 ··· 1258 1257 * in case of out-of-order receptions of delayed responses 1259 1258 */ 1260 1259 return info->desc->ops->poll_done(cinfo, xfer) || 1261 - try_wait_for_completion(&xfer->done) || 1260 + (*ooo = try_wait_for_completion(&xfer->done)) || 1262 1261 ktime_after(ktime_get(), stop); 1263 1262 } 1264 1263 ··· 1275 1274 * itself to support synchronous commands replies. 1276 1275 */ 1277 1276 if (!desc->sync_cmds_completed_on_ret) { 1277 + bool ooo = false; 1278 + 1278 1279 /* 1279 1280 * Poll on xfer using transport provided .poll_done(); 1280 1281 * assumes no completion interrupt was available. 1281 1282 */ 1282 1283 ktime_t stop = ktime_add_ms(ktime_get(), timeout_ms); 1283 1284 1284 - spin_until_cond(scmi_xfer_done_no_timeout(cinfo, 1285 - xfer, stop)); 1286 - if (ktime_after(ktime_get(), stop)) { 1285 + spin_until_cond(scmi_xfer_done_no_timeout(cinfo, xfer, 1286 + stop, &ooo)); 1287 + if (!ooo && !info->desc->ops->poll_done(cinfo, xfer)) { 1287 1288 dev_err(dev, 1288 1289 "timed out in resp(caller: %pS) - polling\n", 1289 1290 (void *)_RET_IP_);