tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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media: platform: mtk-mdp3: Remove mask parameter from MM_REG_WRITE macro

There are two macros to issue a cmdq write: MM_REG_WRITE_MASK and
MM_REG_WRITE, but confusingly, both of them take a mask parameter. The
difference is that MM_REG_WRITE additionally checks whether the mask
passed in contains the register mask, in which case, the 0xffffffff mask
is passed to cmdq_pkt_write_mask(), effectively disregarding the mask
and calling cmdq_pkt_write() as an optimization.

Move that optimization to the MM_REG_WRITE_MASK macro and make
MM_REG_WRITE the variant that doesn't take a mask, directly calling to
cmdq_pkt_write().

Change the call sites to MM_REG_WRITE whenever a mask wasn't necessary
(ie 0xffffffff or a <register>_MASK was passed as mask) and in other
cases to MM_REG_WRITE_MASK.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

authored by

Nícolas F. R. A. Prado and committed by
Mauro Carvalho Chehab 7b00fcfd 6d9038dc

+239 -300
+234 -295
drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c
··· 72 72 73 73 /* Disable RSZ1 */ 74 74 if (ctx->comp->inner_id == rdma0 && prz1) 75 - MM_REG_WRITE(cmd, subsys_id, prz1->reg_base, PRZ_ENABLE, 76 - 0x0, BIT(0)); 75 + MM_REG_WRITE_MASK(cmd, subsys_id, prz1->reg_base, 76 + PRZ_ENABLE, 0x0, BIT(0)); 77 77 } 78 78 79 79 /* Reset RDMA */ 80 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_RESET, BIT(0), BIT(0)); 80 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_RESET, BIT(0), BIT(0)); 81 81 MM_REG_POLL(cmd, subsys_id, base, MDP_RDMA_MON_STA_1, BIT(8), BIT(8)); 82 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_RESET, 0x0, BIT(0)); 82 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_RESET, 0x0, BIT(0)); 83 83 return 0; 84 84 } 85 85 ··· 98 98 99 99 if (mdp_cfg && mdp_cfg->rdma_support_10bit) { 100 100 if (block10bit) 101 - MM_REG_WRITE(cmd, subsys_id, base, 102 - MDP_RDMA_RESV_DUMMY_0, 0x7, 0x7); 101 + MM_REG_WRITE_MASK(cmd, subsys_id, base, 102 + MDP_RDMA_RESV_DUMMY_0, 0x7, 0x7); 103 103 else 104 - MM_REG_WRITE(cmd, subsys_id, base, 105 - MDP_RDMA_RESV_DUMMY_0, 0x0, 0x7); 104 + MM_REG_WRITE_MASK(cmd, subsys_id, base, 105 + MDP_RDMA_RESV_DUMMY_0, 0x0, 0x7); 106 106 } 107 107 108 108 /* Setup smi control */ 109 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_GMCIF_CON, 110 - (7 << 4) + //burst type to 8 111 - (1 << 16), //enable pre-ultra 112 - 0x00030071); 109 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_GMCIF_CON, 110 + (7 << 4) + //burst type to 8 111 + (1 << 16), //enable pre-ultra 112 + 0x00030071); 113 113 114 114 /* Setup source frame info */ 115 115 if (CFG_CHECK(MT8183, p_id)) 116 116 reg = CFG_COMP(MT8183, ctx->param, rdma.src_ctrl); 117 117 else if (CFG_CHECK(MT8195, p_id)) 118 118 reg = CFG_COMP(MT8195, ctx->param, rdma.src_ctrl); 119 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_CON, reg, 120 - 0x03C8FE0F); 119 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_SRC_CON, reg, 0x03C8FE0F); 121 120 122 121 if (mdp_cfg) 123 122 if (mdp_cfg->rdma_support_10bit && en_ufo) { ··· 125 126 reg = CFG_COMP(MT8183, ctx->param, rdma.ufo_dec_y); 126 127 else if (CFG_CHECK(MT8195, p_id)) 127 128 reg = CFG_COMP(MT8195, ctx->param, rdma.ufo_dec_y); 128 - MM_REG_WRITE(cmd, subsys_id, 129 - base, MDP_RDMA_UFO_DEC_LENGTH_BASE_Y, 130 - reg, 0xFFFFFFFF); 129 + MM_REG_WRITE(cmd, subsys_id, base, 130 + MDP_RDMA_UFO_DEC_LENGTH_BASE_Y, reg); 131 131 132 132 if (CFG_CHECK(MT8183, p_id)) 133 133 reg = CFG_COMP(MT8183, ctx->param, rdma.ufo_dec_c); 134 134 else if (CFG_CHECK(MT8195, p_id)) 135 135 reg = CFG_COMP(MT8195, ctx->param, rdma.ufo_dec_c); 136 - MM_REG_WRITE(cmd, subsys_id, 137 - base, MDP_RDMA_UFO_DEC_LENGTH_BASE_C, 138 - reg, 0xFFFFFFFF); 136 + MM_REG_WRITE(cmd, subsys_id, base, 137 + MDP_RDMA_UFO_DEC_LENGTH_BASE_C, reg); 139 138 140 139 /* Set 10bit source frame pitch */ 141 140 if (block10bit) { ··· 141 144 reg = CFG_COMP(MT8183, ctx->param, rdma.mf_bkgd_in_pxl); 142 145 else if (CFG_CHECK(MT8195, p_id)) 143 146 reg = CFG_COMP(MT8195, ctx->param, rdma.mf_bkgd_in_pxl); 144 - MM_REG_WRITE(cmd, subsys_id, 145 - base, MDP_RDMA_MF_BKGD_SIZE_IN_PXL, 146 - reg, 0x001FFFFF); 147 + MM_REG_WRITE_MASK(cmd, subsys_id, base, 148 + MDP_RDMA_MF_BKGD_SIZE_IN_PXL, 149 + reg, 0x001FFFFF); 147 150 } 148 151 } 149 152 ··· 154 157 reg = CFG_COMP(MT8195, ctx->param, rdma.control); 155 158 rdma_con_mask = 0x1130; 156 159 } 157 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_CON, reg, 158 - rdma_con_mask); 160 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_CON, reg, rdma_con_mask); 159 161 160 162 /* Setup source buffer base */ 161 163 if (CFG_CHECK(MT8183, p_id)) 162 164 reg = CFG_COMP(MT8183, ctx->param, rdma.iova[0]); 163 165 else if (CFG_CHECK(MT8195, p_id)) 164 166 reg = CFG_COMP(MT8195, ctx->param, rdma.iova[0]); 165 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_0, reg, 166 - 0xFFFFFFFF); 167 + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_0, reg); 167 168 168 169 if (CFG_CHECK(MT8183, p_id)) 169 170 reg = CFG_COMP(MT8183, ctx->param, rdma.iova[1]); 170 171 else if (CFG_CHECK(MT8195, p_id)) 171 172 reg = CFG_COMP(MT8195, ctx->param, rdma.iova[1]); 172 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_1, reg, 173 - 0xFFFFFFFF); 173 + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_1, reg); 174 174 175 175 if (CFG_CHECK(MT8183, p_id)) 176 176 reg = CFG_COMP(MT8183, ctx->param, rdma.iova[2]); 177 177 else if (CFG_CHECK(MT8195, p_id)) 178 178 reg = CFG_COMP(MT8195, ctx->param, rdma.iova[2]); 179 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_2, reg, 180 - 0xFFFFFFFF); 179 + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_2, reg); 181 180 182 181 /* Setup source buffer end */ 183 182 if (CFG_CHECK(MT8183, p_id)) 184 183 reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[0]); 185 184 else if (CFG_CHECK(MT8195, p_id)) 186 185 reg = CFG_COMP(MT8195, ctx->param, rdma.iova_end[0]); 187 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_0, 188 - reg, 0xFFFFFFFF); 186 + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_0, reg); 189 187 190 188 if (CFG_CHECK(MT8183, p_id)) 191 189 reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[1]); 192 190 else if (CFG_CHECK(MT8195, p_id)) 193 191 reg = CFG_COMP(MT8195, ctx->param, rdma.iova_end[1]); 194 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_1, 195 - reg, 0xFFFFFFFF); 192 + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_1, reg); 196 193 197 194 if (CFG_CHECK(MT8183, p_id)) 198 195 reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[2]); 199 196 else if (CFG_CHECK(MT8195, p_id)) 200 197 reg = CFG_COMP(MT8195, ctx->param, rdma.iova_end[2]); 201 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_2, 202 - reg, 0xFFFFFFFF); 198 + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_2, reg); 203 199 204 200 /* Setup source frame pitch */ 205 201 if (CFG_CHECK(MT8183, p_id)) 206 202 reg = CFG_COMP(MT8183, ctx->param, rdma.mf_bkgd); 207 203 else if (CFG_CHECK(MT8195, p_id)) 208 204 reg = CFG_COMP(MT8195, ctx->param, rdma.mf_bkgd); 209 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_BKGD_SIZE_IN_BYTE, 210 - reg, 0x001FFFFF); 205 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_MF_BKGD_SIZE_IN_BYTE, 206 + reg, 0x001FFFFF); 211 207 212 208 if (CFG_CHECK(MT8183, p_id)) 213 209 reg = CFG_COMP(MT8183, ctx->param, rdma.sf_bkgd); 214 210 else if (CFG_CHECK(MT8195, p_id)) 215 211 reg = CFG_COMP(MT8195, ctx->param, rdma.sf_bkgd); 216 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SF_BKGD_SIZE_IN_BYTE, 217 - reg, 0x001FFFFF); 212 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_SF_BKGD_SIZE_IN_BYTE, 213 + reg, 0x001FFFFF); 218 214 219 215 /* Setup color transform */ 220 216 if (CFG_CHECK(MT8183, p_id)) 221 217 reg = CFG_COMP(MT8183, ctx->param, rdma.transform); 222 218 else if (CFG_CHECK(MT8195, p_id)) 223 219 reg = CFG_COMP(MT8195, ctx->param, rdma.transform); 224 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_TRANSFORM_0, 225 - reg, 0x0F110000); 220 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_TRANSFORM_0, 221 + reg, 0x0F110000); 226 222 227 223 if (!mdp_cfg || !mdp_cfg->rdma_esl_setting) 228 224 goto rdma_config_done; 229 225 230 226 if (CFG_CHECK(MT8195, p_id)) 231 227 reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con0); 232 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_0, 233 - reg, 0x0FFF00FF); 228 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_0, 229 + reg, 0x0FFF00FF); 234 230 235 231 if (CFG_CHECK(MT8195, p_id)) 236 232 reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_high_con0); 237 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_0, 238 - reg, 0x3FFFFFFF); 233 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_0, 234 + reg, 0x3FFFFFFF); 239 235 240 236 if (CFG_CHECK(MT8195, p_id)) 241 237 reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_low_con0); 242 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_0, 243 - reg, 0x3FFFFFFF); 238 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_0, 239 + reg, 0x3FFFFFFF); 244 240 245 241 if (CFG_CHECK(MT8195, p_id)) 246 242 reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con1); 247 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_1, 248 - reg, 0x0F7F007F); 243 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_1, 244 + reg, 0x0F7F007F); 249 245 250 246 if (CFG_CHECK(MT8195, p_id)) 251 247 reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_high_con1); 252 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_1, 253 - reg, 0x3FFFFFFF); 248 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_1, 249 + reg, 0x3FFFFFFF); 254 250 255 251 if (CFG_CHECK(MT8195, p_id)) 256 252 reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_low_con1); 257 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_1, 258 - reg, 0x3FFFFFFF); 253 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_1, 254 + reg, 0x3FFFFFFF); 259 255 260 256 if (CFG_CHECK(MT8195, p_id)) 261 257 reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con2); 262 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_2, 263 - reg, 0x0F3F003F); 258 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_2, 259 + reg, 0x0F3F003F); 264 260 265 261 if (CFG_CHECK(MT8195, p_id)) 266 262 reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_high_con2); 267 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_2, 268 - reg, 0x3FFFFFFF); 263 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_2, 264 + reg, 0x3FFFFFFF); 269 265 270 266 if (CFG_CHECK(MT8195, p_id)) 271 267 reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_low_con2); 272 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_2, 273 - reg, 0x3FFFFFFF); 268 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_2, 269 + reg, 0x3FFFFFFF); 274 270 275 271 if (CFG_CHECK(MT8195, p_id)) 276 272 reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con3); 277 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_3, 278 - reg, 0x0F3F003F); 273 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_3, 274 + reg, 0x0F3F003F); 279 275 280 276 rdma_config_done: 281 277 return 0; ··· 287 297 u32 reg = 0; 288 298 289 299 /* Enable RDMA */ 290 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_EN, BIT(0), BIT(0)); 300 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_EN, BIT(0), BIT(0)); 291 301 292 302 /* Set Y pixel offset */ 293 303 if (CFG_CHECK(MT8183, p_id)) 294 304 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[0]); 295 305 else if (CFG_CHECK(MT8195, p_id)) 296 306 reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset[0]); 297 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_0, 298 - reg, 0xFFFFFFFF); 307 + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_0, reg); 299 308 300 309 /* Set 10bit UFO mode */ 301 310 if (mdp_cfg) { ··· 304 315 else if (CFG_CHECK(MT8195, p_id)) 305 316 reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset_0_p); 306 317 MM_REG_WRITE(cmd, subsys_id, base, 307 - MDP_RDMA_SRC_OFFSET_0_P, 308 - reg, 0xFFFFFFFF); 318 + MDP_RDMA_SRC_OFFSET_0_P, reg); 309 319 } 310 320 } 311 321 ··· 313 325 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[1]); 314 326 else if (CFG_CHECK(MT8195, p_id)) 315 327 reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset[1]); 316 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_1, 317 - reg, 0xFFFFFFFF); 328 + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_1, reg); 318 329 319 330 /* Set V pixel offset */ 320 331 if (CFG_CHECK(MT8183, p_id)) 321 332 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[2]); 322 333 else if (CFG_CHECK(MT8195, p_id)) 323 334 reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset[2]); 324 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_2, 325 - reg, 0xFFFFFFFF); 335 + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_2, reg); 326 336 327 337 /* Set source size */ 328 338 if (CFG_CHECK(MT8183, p_id)) 329 339 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].src); 330 340 else if (CFG_CHECK(MT8195, p_id)) 331 341 reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].src); 332 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_SRC_SIZE, reg, 333 - 0x1FFF1FFF); 342 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_MF_SRC_SIZE, reg, 343 + 0x1FFF1FFF); 334 344 335 345 /* Set target size */ 336 346 if (CFG_CHECK(MT8183, p_id)) 337 347 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].clip); 338 348 else if (CFG_CHECK(MT8195, p_id)) 339 349 reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].clip); 340 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_CLIP_SIZE, 341 - reg, 0x1FFF1FFF); 350 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_MF_CLIP_SIZE, 351 + reg, 0x1FFF1FFF); 342 352 343 353 /* Set crop offset */ 344 354 if (CFG_CHECK(MT8183, p_id)) 345 355 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].clip_ofst); 346 356 else if (CFG_CHECK(MT8195, p_id)) 347 357 reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].clip_ofst); 348 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_OFFSET_1, 349 - reg, 0x003F001F); 358 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_MF_OFFSET_1, 359 + reg, 0x003F001F); 350 360 351 361 if (CFG_CHECK(MT8183, p_id)) { 352 362 csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); ··· 355 369 } 356 370 if (mdp_cfg && mdp_cfg->rdma_upsample_repeat_only) 357 371 if ((csf_r - csf_l + 1) > 320) 358 - MM_REG_WRITE(cmd, subsys_id, base, 359 - MDP_RDMA_RESV_DUMMY_0, BIT(2), BIT(2)); 372 + MM_REG_WRITE_MASK(cmd, subsys_id, base, 373 + MDP_RDMA_RESV_DUMMY_0, BIT(2), BIT(2)); 360 374 361 375 return 0; 362 376 } ··· 379 393 MM_REG_WAIT(cmd, ctx->comp->gce_event[MDP_GCE_EVENT_EOF]); 380 394 381 395 /* Disable RDMA */ 382 - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_EN, 0x0, BIT(0)); 396 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_EN, 0x0, BIT(0)); 383 397 return 0; 384 398 } 385 399 ··· 397 411 u8 subsys_id = ctx->comp->subsys_id; 398 412 399 413 /* Reset RSZ */ 400 - MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x10000, BIT(16)); 401 - MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x0, BIT(16)); 414 + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_ENABLE, 0x10000, BIT(16)); 415 + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_ENABLE, 0x0, BIT(16)); 402 416 /* Enable RSZ */ 403 - MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, BIT(0), BIT(0)); 417 + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_ENABLE, BIT(0), BIT(0)); 404 418 405 419 if (CFG_CHECK(MT8195, p_id)) { 406 420 struct device *dev; ··· 423 437 u32 reg = 0; 424 438 425 439 if (mdp_cfg && mdp_cfg->rsz_etc_control) 426 - MM_REG_WRITE(cmd, subsys_id, base, RSZ_ETC_CONTROL, 0x0, 0xFFFFFFFF); 440 + MM_REG_WRITE(cmd, subsys_id, base, RSZ_ETC_CONTROL, 0x0); 427 441 428 442 if (CFG_CHECK(MT8183, p_id)) 429 443 bypass = CFG_COMP(MT8183, ctx->param, frame.bypass); ··· 432 446 433 447 if (bypass) { 434 448 /* Disable RSZ */ 435 - MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x0, BIT(0)); 449 + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_ENABLE, 0x0, BIT(0)); 436 450 return 0; 437 451 } 438 452 ··· 440 454 reg = CFG_COMP(MT8183, ctx->param, rsz.control1); 441 455 else if (CFG_CHECK(MT8195, p_id)) 442 456 reg = CFG_COMP(MT8195, ctx->param, rsz.control1); 443 - MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_1, reg, 444 - 0x03FFFDF3); 457 + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_CONTROL_1, reg, 0x03FFFDF3); 445 458 446 459 if (CFG_CHECK(MT8183, p_id)) 447 460 reg = CFG_COMP(MT8183, ctx->param, rsz.control2); 448 461 else if (CFG_CHECK(MT8195, p_id)) 449 462 reg = CFG_COMP(MT8195, ctx->param, rsz.control2); 450 - MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_2, reg, 451 - 0x0FFFC290); 463 + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_CONTROL_2, reg, 0x0FFFC290); 452 464 453 465 if (CFG_CHECK(MT8183, p_id)) 454 466 reg = CFG_COMP(MT8183, ctx->param, rsz.coeff_step_x); 455 467 else if (CFG_CHECK(MT8195, p_id)) 456 468 reg = CFG_COMP(MT8195, ctx->param, rsz.coeff_step_x); 457 - MM_REG_WRITE(cmd, subsys_id, base, PRZ_HORIZONTAL_COEFF_STEP, 458 - reg, 0x007FFFFF); 469 + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_HORIZONTAL_COEFF_STEP, reg, 470 + 0x007FFFFF); 459 471 460 472 if (CFG_CHECK(MT8183, p_id)) 461 473 reg = CFG_COMP(MT8183, ctx->param, rsz.coeff_step_y); 462 474 else if (CFG_CHECK(MT8195, p_id)) 463 475 reg = CFG_COMP(MT8195, ctx->param, rsz.coeff_step_y); 464 - MM_REG_WRITE(cmd, subsys_id, base, PRZ_VERTICAL_COEFF_STEP, 465 - reg, 0x007FFFFF); 476 + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_VERTICAL_COEFF_STEP, reg, 477 + 0x007FFFFF); 466 478 467 479 return 0; 468 480 } ··· 479 495 reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].control2); 480 496 else if (CFG_CHECK(MT8195, p_id)) 481 497 reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].control2); 482 - MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_2, reg, 483 - 0x00003800); 498 + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_CONTROL_2, reg, 0x00003800); 484 499 485 500 if (CFG_CHECK(MT8183, p_id)) 486 501 reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].src); 487 502 else if (CFG_CHECK(MT8195, p_id)) 488 503 reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].src); 489 - MM_REG_WRITE(cmd, subsys_id, base, PRZ_INPUT_IMAGE, reg, 490 - 0xFFFFFFFF); 504 + MM_REG_WRITE(cmd, subsys_id, base, PRZ_INPUT_IMAGE, reg); 491 505 492 506 if (CFG_CHECK(MT8183, p_id)) { 493 507 csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); ··· 496 514 } 497 515 if (mdp_cfg && mdp_cfg->rsz_disable_dcm_small_sample) 498 516 if ((csf_r - csf_l + 1) <= 16) 499 - MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_1, 500 - BIT(27), BIT(27)); 517 + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_CONTROL_1, 518 + BIT(27), BIT(27)); 501 519 502 520 if (CFG_CHECK(MT8183, p_id)) 503 521 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.left); 504 522 else if (CFG_CHECK(MT8195, p_id)) 505 523 reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.left); 506 - MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_HORIZONTAL_INTEGER_OFFSET, 507 - reg, 0xFFFF); 524 + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_LUMA_HORIZONTAL_INTEGER_OFFSET, 525 + reg, 0xFFFF); 508 526 509 527 if (CFG_CHECK(MT8183, p_id)) 510 528 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.left_subpix); 511 529 else if (CFG_CHECK(MT8195, p_id)) 512 530 reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.left_subpix); 513 - MM_REG_WRITE(cmd, subsys_id, 514 - base, PRZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET, 515 - reg, 0x1FFFFF); 531 + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET, 532 + reg, 0x1FFFFF); 516 533 517 534 if (CFG_CHECK(MT8183, p_id)) 518 535 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.top); 519 536 else if (CFG_CHECK(MT8195, p_id)) 520 537 reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.top); 521 - MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_VERTICAL_INTEGER_OFFSET, 522 - reg, 0xFFFF); 538 + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_LUMA_VERTICAL_INTEGER_OFFSET, 539 + reg, 0xFFFF); 523 540 524 541 if (CFG_CHECK(MT8183, p_id)) 525 542 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.top_subpix); 526 543 else if (CFG_CHECK(MT8195, p_id)) 527 544 reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.top_subpix); 528 - MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET, 529 - reg, 0x1FFFFF); 545 + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET, 546 + reg, 0x1FFFFF); 530 547 531 548 if (CFG_CHECK(MT8183, p_id)) 532 549 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].chroma.left); 533 550 else if (CFG_CHECK(MT8195, p_id)) 534 551 reg = CFG_COMP(MT8195, ctx->param, subfrms[index].chroma.left); 535 - MM_REG_WRITE(cmd, subsys_id, 536 - base, PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET, 537 - reg, 0xFFFF); 552 + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET, 553 + reg, 0xFFFF); 538 554 539 555 if (CFG_CHECK(MT8183, p_id)) 540 556 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].chroma.left_subpix); 541 557 else if (CFG_CHECK(MT8195, p_id)) 542 558 reg = CFG_COMP(MT8195, ctx->param, subfrms[index].chroma.left_subpix); 543 - MM_REG_WRITE(cmd, subsys_id, 544 - base, PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET, 545 - reg, 0x1FFFFF); 559 + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET, 560 + reg, 0x1FFFFF); 546 561 547 562 if (CFG_CHECK(MT8183, p_id)) 548 563 reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].clip); 549 564 else if (CFG_CHECK(MT8195, p_id)) 550 565 reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].clip); 551 - MM_REG_WRITE(cmd, subsys_id, base, PRZ_OUTPUT_IMAGE, reg, 552 - 0xFFFFFFFF); 566 + MM_REG_WRITE(cmd, subsys_id, base, PRZ_OUTPUT_IMAGE, reg); 553 567 554 568 if (CFG_CHECK(MT8195, p_id)) { 555 569 struct device *dev; ··· 574 596 if (CFG_CHECK(MT8195, p_id)) 575 597 reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].merge_cfg); 576 598 MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, 577 - MDP_MERGE_CFG_0, reg, 0xFFFFFFFF); 599 + MDP_MERGE_CFG_0, reg); 578 600 MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, 579 - MDP_MERGE_CFG_4, reg, 0xFFFFFFFF); 601 + MDP_MERGE_CFG_4, reg); 580 602 MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, 581 - MDP_MERGE_CFG_24, reg, 0xFFFFFFFF); 603 + MDP_MERGE_CFG_24, reg); 582 604 MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, 583 - MDP_MERGE_CFG_25, reg, 0xFFFFFFFF); 605 + MDP_MERGE_CFG_25, reg); 584 606 585 607 /* Bypass mode */ 586 608 MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, 587 - MDP_MERGE_CFG_12, BIT(0), 0xFFFFFFFF); 609 + MDP_MERGE_CFG_12, BIT(0)); 588 610 MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, 589 - MDP_MERGE_ENABLE, BIT(0), 0xFFFFFFFF); 611 + MDP_MERGE_ENABLE, BIT(0)); 590 612 } 591 613 592 614 rsz_subfrm_done: ··· 612 634 } 613 635 614 636 if ((csf_r - csf_l + 1) <= 16) 615 - MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_1, 0x0, 616 - BIT(27)); 637 + MM_REG_WRITE_MASK(cmd, subsys_id, base, PRZ_CONTROL_1, 0x0, 638 + BIT(27)); 617 639 } 618 640 619 641 return 0; ··· 633 655 u8 subsys_id = ctx->comp->subsys_id; 634 656 635 657 /* Reset WROT */ 636 - MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST, BIT(0), BIT(0)); 658 + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_SOFT_RST, BIT(0), BIT(0)); 637 659 MM_REG_POLL(cmd, subsys_id, base, VIDO_SOFT_RST_STAT, BIT(0), BIT(0)); 638 660 639 661 /* Reset setting */ 640 662 if (CFG_CHECK(MT8195, p_id)) 641 - MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL, 0x0, 0xFFFFFFFF); 663 + MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL, 0x0); 642 664 643 - MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST, 0x0, BIT(0)); 665 + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_SOFT_RST, 0x0, BIT(0)); 644 666 MM_REG_POLL(cmd, subsys_id, base, VIDO_SOFT_RST_STAT, 0x0, BIT(0)); 645 667 return 0; 646 668 } ··· 659 681 reg = CFG_COMP(MT8183, ctx->param, wrot.iova[0]); 660 682 else if (CFG_CHECK(MT8195, p_id)) 661 683 reg = CFG_COMP(MT8195, ctx->param, wrot.iova[0]); 662 - MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR, reg, 663 - 0xFFFFFFFF); 684 + MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR, reg); 664 685 665 686 if (CFG_CHECK(MT8183, p_id)) 666 687 reg = CFG_COMP(MT8183, ctx->param, wrot.iova[1]); 667 688 else if (CFG_CHECK(MT8195, p_id)) 668 689 reg = CFG_COMP(MT8195, ctx->param, wrot.iova[1]); 669 - MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_C, reg, 670 - 0xFFFFFFFF); 690 + MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_C, reg); 671 691 672 692 if (CFG_CHECK(MT8183, p_id)) 673 693 reg = CFG_COMP(MT8183, ctx->param, wrot.iova[2]); 674 694 else if (CFG_CHECK(MT8195, p_id)) 675 695 reg = CFG_COMP(MT8195, ctx->param, wrot.iova[2]); 676 - MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_V, reg, 677 - 0xFFFFFFFF); 696 + MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_V, reg); 678 697 679 698 if (mdp_cfg && mdp_cfg->wrot_support_10bit) { 680 699 if (CFG_CHECK(MT8195, p_id)) 681 700 reg = CFG_COMP(MT8195, ctx->param, wrot.scan_10bit); 682 - MM_REG_WRITE(cmd, subsys_id, base, VIDO_SCAN_10BIT, 683 - reg, 0x0000000F); 701 + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_SCAN_10BIT, 702 + reg, 0x0000000F); 684 703 685 704 if (CFG_CHECK(MT8195, p_id)) 686 705 reg = CFG_COMP(MT8195, ctx->param, wrot.pending_zero); 687 - MM_REG_WRITE(cmd, subsys_id, base, VIDO_PENDING_ZERO, 688 - reg, 0x04000000); 706 + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_PENDING_ZERO, 707 + reg, 0x04000000); 689 708 } 690 709 691 710 if (CFG_CHECK(MT8195, p_id)) { 692 711 reg = CFG_COMP(MT8195, ctx->param, wrot.bit_number); 693 - MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL_2, 694 - reg, 0x00000007); 712 + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_CTRL_2, 713 + reg, 0x00000007); 695 714 } 696 715 697 716 /* Write frame related registers */ ··· 696 721 reg = CFG_COMP(MT8183, ctx->param, wrot.control); 697 722 else if (CFG_CHECK(MT8195, p_id)) 698 723 reg = CFG_COMP(MT8195, ctx->param, wrot.control); 699 - MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL, reg, 700 - 0xF131510F); 724 + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_CTRL, reg, 0xF131510F); 701 725 702 726 /* Write pre-ultra threshold */ 703 727 if (CFG_CHECK(MT8195, p_id)) { 704 728 reg = CFG_COMP(MT8195, ctx->param, wrot.pre_ultra); 705 - MM_REG_WRITE(cmd, subsys_id, base, VIDO_DMA_PREULTRA, reg, 706 - 0x00FFFFFF); 729 + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_DMA_PREULTRA, reg, 730 + 0x00FFFFFF); 707 731 } 708 732 709 733 /* Write frame Y pitch */ ··· 710 736 reg = CFG_COMP(MT8183, ctx->param, wrot.stride[0]); 711 737 else if (CFG_CHECK(MT8195, p_id)) 712 738 reg = CFG_COMP(MT8195, ctx->param, wrot.stride[0]); 713 - MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE, reg, 714 - 0x0000FFFF); 739 + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_STRIDE, reg, 0x0000FFFF); 715 740 716 741 /* Write frame UV pitch */ 717 742 if (CFG_CHECK(MT8183, p_id)) 718 743 reg = CFG_COMP(MT8183, ctx->param, wrot.stride[1]); 719 744 else if (CFG_CHECK(MT8195, p_id)) 720 745 reg = CFG_COMP(MT8195, ctx->param, wrot.stride[1]); 721 - MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_C, reg, 722 - 0xFFFF); 746 + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_STRIDE_C, reg, 0xFFFF); 723 747 724 748 if (CFG_CHECK(MT8183, p_id)) 725 749 reg = CFG_COMP(MT8183, ctx->param, wrot.stride[2]); 726 750 else if (CFG_CHECK(MT8195, p_id)) 727 751 reg = CFG_COMP(MT8195, ctx->param, wrot.stride[2]); 728 - MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_V, reg, 729 - 0xFFFF); 752 + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_STRIDE_V, reg, 0xFFFF); 730 753 731 754 /* Write matrix control */ 732 755 if (CFG_CHECK(MT8183, p_id)) 733 756 reg = CFG_COMP(MT8183, ctx->param, wrot.mat_ctrl); 734 757 else if (CFG_CHECK(MT8195, p_id)) 735 758 reg = CFG_COMP(MT8195, ctx->param, wrot.mat_ctrl); 736 - MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAT_CTRL, reg, 0xF3); 759 + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_MAT_CTRL, reg, 0xF3); 737 760 738 761 /* Set the fixed ALPHA as 0xFF */ 739 - MM_REG_WRITE(cmd, subsys_id, base, VIDO_DITHER, 0xFF000000, 740 - 0xFF000000); 762 + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_DITHER, 0xFF000000, 763 + 0xFF000000); 741 764 742 765 /* Set VIDO_EOL_SEL */ 743 - MM_REG_WRITE(cmd, subsys_id, base, VIDO_RSV_1, BIT(31), BIT(31)); 766 + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_RSV_1, BIT(31), BIT(31)); 744 767 745 768 /* Set VIDO_FIFO_TEST */ 746 769 if (CFG_CHECK(MT8183, p_id)) ··· 746 775 reg = CFG_COMP(MT8195, ctx->param, wrot.fifo_test); 747 776 748 777 if (reg != 0) 749 - MM_REG_WRITE(cmd, subsys_id, base, VIDO_FIFO_TEST, 750 - reg, 0xFFF); 778 + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_FIFO_TEST, reg, 779 + 0xFFF); 751 780 752 781 /* Filter enable */ 753 782 if (mdp_cfg && mdp_cfg->wrot_filter_constraint) { ··· 755 784 reg = CFG_COMP(MT8183, ctx->param, wrot.filter); 756 785 else if (CFG_CHECK(MT8195, p_id)) 757 786 reg = CFG_COMP(MT8195, ctx->param, wrot.filter); 758 - MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, 759 - reg, 0x77); 787 + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, reg, 788 + 0x77); 760 789 761 790 /* Turn off WROT DMA DCM */ 762 791 if (CFG_CHECK(MT8195, p_id)) 763 - MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN, 764 - (0x1 << 23) + (0x1 << 20), 0x900000); 792 + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_ROT_EN, 793 + (0x1 << 23) + (0x1 << 20), 0x900000); 765 794 } 766 795 767 796 return 0; ··· 779 808 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[0]); 780 809 else if (CFG_CHECK(MT8195, p_id)) 781 810 reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].offset[0]); 782 - MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR, 783 - reg, 0x0FFFFFFF); 811 + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_OFST_ADDR, reg, 0x0FFFFFFF); 784 812 785 813 /* Write U pixel offset */ 786 814 if (CFG_CHECK(MT8183, p_id)) 787 815 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[1]); 788 816 else if (CFG_CHECK(MT8195, p_id)) 789 817 reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].offset[1]); 790 - MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR_C, 791 - reg, 0x0FFFFFFF); 818 + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_OFST_ADDR_C, reg, 0x0FFFFFFF); 792 819 793 820 /* Write V pixel offset */ 794 821 if (CFG_CHECK(MT8183, p_id)) 795 822 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[2]); 796 823 else if (CFG_CHECK(MT8195, p_id)) 797 824 reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].offset[2]); 798 - MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR_V, 799 - reg, 0x0FFFFFFF); 825 + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_OFST_ADDR_V, reg, 826 + 0x0FFFFFFF); 800 827 801 828 /* Write source size */ 802 829 if (CFG_CHECK(MT8183, p_id)) 803 830 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].src); 804 831 else if (CFG_CHECK(MT8195, p_id)) 805 832 reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].src); 806 - MM_REG_WRITE(cmd, subsys_id, base, VIDO_IN_SIZE, reg, 807 - 0x1FFF1FFF); 833 + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_IN_SIZE, reg, 0x1FFF1FFF); 808 834 809 835 /* Write target size */ 810 836 if (CFG_CHECK(MT8183, p_id)) 811 837 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].clip); 812 838 else if (CFG_CHECK(MT8195, p_id)) 813 839 reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].clip); 814 - MM_REG_WRITE(cmd, subsys_id, base, VIDO_TAR_SIZE, reg, 815 - 0x1FFF1FFF); 840 + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_TAR_SIZE, reg, 0x1FFF1FFF); 816 841 817 842 if (CFG_CHECK(MT8183, p_id)) 818 843 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].clip_ofst); 819 844 else if (CFG_CHECK(MT8195, p_id)) 820 845 reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].clip_ofst); 821 - MM_REG_WRITE(cmd, subsys_id, base, VIDO_CROP_OFST, reg, 822 - 0x1FFF1FFF); 846 + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_CROP_OFST, reg, 0x1FFF1FFF); 823 847 824 848 if (CFG_CHECK(MT8183, p_id)) 825 849 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].main_buf); 826 850 else if (CFG_CHECK(MT8195, p_id)) 827 851 reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].main_buf); 828 - MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, 829 - reg, 0x1FFF7F00); 852 + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, reg, 853 + 0x1FFF7F00); 830 854 831 855 /* Enable WROT */ 832 - MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN, BIT(0), BIT(0)); 856 + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_ROT_EN, BIT(0), BIT(0)); 833 857 834 858 return 0; 835 859 } ··· 847 881 MM_REG_WAIT(cmd, ctx->comp->gce_event[MDP_GCE_EVENT_EOF]); 848 882 849 883 if (mdp_cfg && mdp_cfg->wrot_filter_constraint) 850 - MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, 0x0, 851 - 0x77); 884 + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, 0x0, 885 + 0x77); 852 886 853 887 /* Disable WROT */ 854 - MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN, 0x0, BIT(0)); 888 + MM_REG_WRITE_MASK(cmd, subsys_id, base, VIDO_ROT_EN, 0x0, BIT(0)); 855 889 856 890 return 0; 857 891 } ··· 870 904 u8 subsys_id = ctx->comp->subsys_id; 871 905 872 906 /* Reset WDMA */ 873 - MM_REG_WRITE(cmd, subsys_id, base, WDMA_RST, BIT(0), BIT(0)); 907 + MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_RST, BIT(0), BIT(0)); 874 908 MM_REG_POLL(cmd, subsys_id, base, WDMA_FLOW_CTRL_DBG, BIT(0), BIT(0)); 875 - MM_REG_WRITE(cmd, subsys_id, base, WDMA_RST, 0x0, BIT(0)); 909 + MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_RST, 0x0, BIT(0)); 876 910 return 0; 877 911 } 878 912 ··· 884 918 u8 subsys_id = ctx->comp->subsys_id; 885 919 u32 reg = 0; 886 920 887 - MM_REG_WRITE(cmd, subsys_id, base, WDMA_BUF_CON2, 0x10101050, 888 - 0xFFFFFFFF); 921 + MM_REG_WRITE(cmd, subsys_id, base, WDMA_BUF_CON2, 0x10101050); 889 922 890 923 /* Setup frame information */ 891 924 if (CFG_CHECK(MT8183, p_id)) 892 925 reg = CFG_COMP(MT8183, ctx->param, wdma.wdma_cfg); 893 - MM_REG_WRITE(cmd, subsys_id, base, WDMA_CFG, reg, 894 - 0x0F01B8F0); 926 + MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_CFG, reg, 0x0F01B8F0); 895 927 /* Setup frame base address */ 896 928 if (CFG_CHECK(MT8183, p_id)) 897 929 reg = CFG_COMP(MT8183, ctx->param, wdma.iova[0]); 898 - MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_ADDR, reg, 899 - 0xFFFFFFFF); 930 + MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_ADDR, reg); 900 931 if (CFG_CHECK(MT8183, p_id)) 901 932 reg = CFG_COMP(MT8183, ctx->param, wdma.iova[1]); 902 - MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_U_ADDR, reg, 903 - 0xFFFFFFFF); 933 + MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_U_ADDR, reg); 904 934 if (CFG_CHECK(MT8183, p_id)) 905 935 reg = CFG_COMP(MT8183, ctx->param, wdma.iova[2]); 906 - MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_V_ADDR, reg, 907 - 0xFFFFFFFF); 936 + MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_V_ADDR, reg); 908 937 /* Setup Y pitch */ 909 938 if (CFG_CHECK(MT8183, p_id)) 910 939 reg = CFG_COMP(MT8183, ctx->param, wdma.w_in_byte); 911 - MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_W_IN_BYTE, 912 - reg, 0x0000FFFF); 940 + MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_DST_W_IN_BYTE, reg, 941 + 0x0000FFFF); 913 942 /* Setup UV pitch */ 914 943 if (CFG_CHECK(MT8183, p_id)) 915 944 reg = CFG_COMP(MT8183, ctx->param, wdma.uv_stride); 916 - MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_UV_PITCH, 917 - reg, 0x0000FFFF); 945 + MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_DST_UV_PITCH, reg, 946 + 0x0000FFFF); 918 947 /* Set the fixed ALPHA as 0xFF */ 919 - MM_REG_WRITE(cmd, subsys_id, base, WDMA_ALPHA, 0x800000FF, 920 - 0x800000FF); 948 + MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_ALPHA, 0x800000FF, 949 + 0x800000FF); 921 950 922 951 return 0; 923 952 } ··· 927 966 /* Write Y pixel offset */ 928 967 if (CFG_CHECK(MT8183, p_id)) 929 968 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].offset[0]); 930 - MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_ADDR_OFFSET, 931 - reg, 0x0FFFFFFF); 969 + MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_DST_ADDR_OFFSET, reg, 970 + 0x0FFFFFFF); 932 971 /* Write U pixel offset */ 933 972 if (CFG_CHECK(MT8183, p_id)) 934 973 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].offset[1]); 935 - MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_U_ADDR_OFFSET, 936 - reg, 0x0FFFFFFF); 974 + MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_DST_U_ADDR_OFFSET, reg, 975 + 0x0FFFFFFF); 937 976 /* Write V pixel offset */ 938 977 if (CFG_CHECK(MT8183, p_id)) 939 978 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].offset[2]); 940 - MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_V_ADDR_OFFSET, 941 - reg, 0x0FFFFFFF); 979 + MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_DST_V_ADDR_OFFSET, reg, 980 + 0x0FFFFFFF); 942 981 /* Write source size */ 943 982 if (CFG_CHECK(MT8183, p_id)) 944 983 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].src); 945 - MM_REG_WRITE(cmd, subsys_id, base, WDMA_SRC_SIZE, reg, 946 - 0x3FFF3FFF); 984 + MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_SRC_SIZE, reg, 0x3FFF3FFF); 947 985 /* Write target size */ 948 986 if (CFG_CHECK(MT8183, p_id)) 949 987 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].clip); 950 - MM_REG_WRITE(cmd, subsys_id, base, WDMA_CLIP_SIZE, reg, 951 - 0x3FFF3FFF); 988 + MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_CLIP_SIZE, reg, 0x3FFF3FFF); 952 989 /* Write clip offset */ 953 990 if (CFG_CHECK(MT8183, p_id)) 954 991 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].clip_ofst); 955 - MM_REG_WRITE(cmd, subsys_id, base, WDMA_CLIP_COORD, reg, 956 - 0x3FFF3FFF); 992 + MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_CLIP_COORD, reg, 0x3FFF3FFF); 957 993 958 994 /* Enable WDMA */ 959 - MM_REG_WRITE(cmd, subsys_id, base, WDMA_EN, BIT(0), BIT(0)); 995 + MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_EN, BIT(0), BIT(0)); 960 996 961 997 return 0; 962 998 } ··· 965 1007 966 1008 MM_REG_WAIT(cmd, ctx->comp->gce_event[MDP_GCE_EVENT_EOF]); 967 1009 /* Disable WDMA */ 968 - MM_REG_WRITE(cmd, subsys_id, base, WDMA_EN, 0x0, BIT(0)); 1010 + MM_REG_WRITE_MASK(cmd, subsys_id, base, WDMA_EN, 0x0, BIT(0)); 969 1011 return 0; 970 1012 } 971 1013 ··· 991 1033 992 1034 /* Reset histogram */ 993 1035 for (i = 0; i <= hist_num; i++) 994 - MM_REG_WRITE_MASK(cmd, subsys_id, base, 995 - (MDP_LUMA_HIST_INIT + (i << 2)), 996 - 0, 0xFFFFFFFF); 1036 + MM_REG_WRITE(cmd, subsys_id, base, 1037 + (MDP_LUMA_HIST_INIT + (i << 2)), 0); 997 1038 998 1039 if (mdp_cfg->tdshp_constrain) 999 1040 MM_REG_WRITE(cmd, subsys_id, base, 1000 - MDP_DC_TWO_D_W1_RESULT_INIT, 0, 0xFFFFFFFF); 1041 + MDP_DC_TWO_D_W1_RESULT_INIT, 0); 1001 1042 1002 1043 if (mdp_cfg->tdshp_contour) 1003 1044 for (i = 0; i < hist_num; i++) 1004 - MM_REG_WRITE_MASK(cmd, subsys_id, base, 1005 - (MDP_CONTOUR_HIST_INIT + (i << 2)), 1006 - 0, 0xFFFFFFFF); 1045 + MM_REG_WRITE(cmd, subsys_id, base, 1046 + (MDP_CONTOUR_HIST_INIT + (i << 2)), 0); 1007 1047 1008 1048 return 0; 1009 1049 } ··· 1011 1055 phys_addr_t base = ctx->comp->reg_base; 1012 1056 u16 subsys_id = ctx->comp->subsys_id; 1013 1057 1014 - MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_CTRL, BIT(0), BIT(0)); 1058 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_TDSHP_CTRL, BIT(0), BIT(0)); 1015 1059 /* Enable FIFO */ 1016 - MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_CFG, BIT(1), BIT(1)); 1060 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_TDSHP_CFG, BIT(1), BIT(1)); 1017 1061 1018 1062 return reset_luma_hist(ctx, cmd); 1019 1063 } ··· 1028 1072 1029 1073 if (CFG_CHECK(MT8195, p_id)) 1030 1074 reg = CFG_COMP(MT8195, ctx->param, tdshp.cfg); 1031 - MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_CFG, reg, BIT(0)); 1075 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_TDSHP_CFG, reg, BIT(0)); 1032 1076 1033 1077 return 0; 1034 1078 } ··· 1042 1086 1043 1087 if (CFG_CHECK(MT8195, p_id)) 1044 1088 reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].src); 1045 - MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_INPUT_SIZE, 1046 - reg, MDP_TDSHP_INPUT_SIZE_MASK); 1089 + MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_INPUT_SIZE, reg); 1047 1090 1048 1091 if (CFG_CHECK(MT8195, p_id)) 1049 1092 reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].clip_ofst); 1050 - MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_OUTPUT_OFFSET, 1051 - reg, 0x00FF00FF); 1093 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_TDSHP_OUTPUT_OFFSET, reg, 1094 + 0x00FF00FF); 1052 1095 1053 1096 if (CFG_CHECK(MT8195, p_id)) 1054 1097 reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].clip); 1055 - MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_OUTPUT_SIZE, 1056 - reg, MDP_TDSHP_OUTPUT_SIZE_MASK); 1098 + MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_OUTPUT_SIZE, reg); 1057 1099 1058 1100 if (CFG_CHECK(MT8195, p_id)) 1059 1101 reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].hist_cfg_0); 1060 - MM_REG_WRITE(cmd, subsys_id, base, MDP_HIST_CFG_00, reg, 0xFFFFFFFF); 1102 + MM_REG_WRITE(cmd, subsys_id, base, MDP_HIST_CFG_00, reg); 1061 1103 1062 1104 if (CFG_CHECK(MT8195, p_id)) 1063 1105 reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].hist_cfg_1); 1064 - MM_REG_WRITE(cmd, subsys_id, base, MDP_HIST_CFG_01, reg, 0xFFFFFFFF); 1106 + MM_REG_WRITE(cmd, subsys_id, base, MDP_HIST_CFG_01, reg); 1065 1107 1066 1108 return 0; 1067 1109 } ··· 1076 1122 phys_addr_t base = ctx->comp->reg_base; 1077 1123 u16 subsys_id = ctx->comp->subsys_id; 1078 1124 1079 - MM_REG_WRITE(cmd, subsys_id, base, 1080 - MDP_COLOR_START, 0x1, BIT(1) | BIT(0)); 1081 - MM_REG_WRITE(cmd, subsys_id, base, 1082 - MDP_COLOR_WIN_X_MAIN, 0xFFFF0000, 0xFFFFFFFF); 1083 - MM_REG_WRITE(cmd, subsys_id, base, 1084 - MDP_COLOR_WIN_Y_MAIN, 0xFFFF0000, 0xFFFFFFFF); 1125 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_COLOR_START, 0x1, 1126 + BIT(1) | BIT(0)); 1127 + MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_WIN_X_MAIN, 0xFFFF0000); 1128 + MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_WIN_Y_MAIN, 0xFFFF0000); 1085 1129 1086 1130 /* Reset color matrix */ 1087 - MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_CM1_EN, 0x0, BIT(0)); 1088 - MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_CM2_EN, 0x0, BIT(0)); 1131 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_COLOR_CM1_EN, 0x0, BIT(0)); 1132 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_COLOR_CM2_EN, 0x0, BIT(0)); 1089 1133 1090 1134 /* Enable interrupt */ 1091 - MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_INTEN, 0x7, 0x7); 1135 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_COLOR_INTEN, 0x7, 0x7); 1092 1136 1093 - MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_OUT_SEL, 0x333, 0x333); 1137 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_COLOR_OUT_SEL, 0x333, 0x333); 1094 1138 1095 1139 return 0; 1096 1140 } ··· 1103 1151 1104 1152 if (CFG_CHECK(MT8195, p_id)) 1105 1153 reg = CFG_COMP(MT8195, ctx->param, color.start); 1106 - MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_START, 1107 - reg, MDP_COLOR_START_MASK); 1154 + MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_START, reg); 1108 1155 1109 1156 return 0; 1110 1157 } ··· 1117 1166 1118 1167 if (CFG_CHECK(MT8195, p_id)) 1119 1168 reg = CFG_COMP(MT8195, ctx->param, color.subfrms[index].in_hsize); 1120 - MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_INTERNAL_IP_WIDTH, 1121 - reg, 0x00003FFF); 1169 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_COLOR_INTERNAL_IP_WIDTH, 1170 + reg, 0x00003FFF); 1122 1171 1123 1172 if (CFG_CHECK(MT8195, p_id)) 1124 1173 reg = CFG_COMP(MT8195, ctx->param, color.subfrms[index].in_vsize); 1125 - MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_INTERNAL_IP_HEIGHT, 1126 - reg, 0x00003FFF); 1174 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_COLOR_INTERNAL_IP_HEIGHT, 1175 + reg, 0x00003FFF); 1127 1176 1128 1177 return 0; 1129 1178 } ··· 1141 1190 u8 subsys_id = ctx->comp->subsys_id; 1142 1191 1143 1192 /* CCORR enable */ 1144 - MM_REG_WRITE(cmd, subsys_id, base, MDP_CCORR_EN, BIT(0), BIT(0)); 1193 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_CCORR_EN, BIT(0), BIT(0)); 1145 1194 /* Relay mode */ 1146 - MM_REG_WRITE(cmd, subsys_id, base, MDP_CCORR_CFG, BIT(0), BIT(0)); 1195 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_CCORR_CFG, BIT(0), BIT(0)); 1147 1196 return 0; 1148 1197 } 1149 1198 ··· 1165 1214 1166 1215 hsize = csf_r - csf_l + 1; 1167 1216 vsize = csf_b - csf_t + 1; 1168 - MM_REG_WRITE(cmd, subsys_id, base, MDP_CCORR_SIZE, 1169 - (hsize << 16) + (vsize << 0), 0x1FFF1FFF); 1217 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_CCORR_SIZE, 1218 + (hsize << 16) + (vsize << 0), 0x1FFF1FFF); 1170 1219 return 0; 1171 1220 } 1172 1221 ··· 1182 1231 u16 subsys_id = ctx->comp->subsys_id; 1183 1232 1184 1233 /* Always set MDP_AAL enable to 1 */ 1185 - MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_EN, BIT(0), BIT(0)); 1234 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_AAL_EN, BIT(0), BIT(0)); 1186 1235 1187 1236 return 0; 1188 1237 } ··· 1197 1246 1198 1247 if (CFG_CHECK(MT8195, p_id)) 1199 1248 reg = CFG_COMP(MT8195, ctx->param, aal.cfg_main); 1200 - MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_CFG_MAIN, reg, BIT(7)); 1249 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_AAL_CFG_MAIN, reg, BIT(7)); 1201 1250 1202 1251 if (CFG_CHECK(MT8195, p_id)) 1203 1252 reg = CFG_COMP(MT8195, ctx->param, aal.cfg); 1204 - MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_CFG, reg, BIT(0)); 1253 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_AAL_CFG, reg, BIT(0)); 1205 1254 1206 1255 return 0; 1207 1256 } ··· 1215 1264 1216 1265 if (CFG_CHECK(MT8195, p_id)) 1217 1266 reg = CFG_COMP(MT8195, ctx->param, aal.subfrms[index].src); 1218 - MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_SIZE, 1219 - reg, MDP_AAL_SIZE_MASK); 1267 + MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_SIZE, reg); 1220 1268 1221 1269 if (CFG_CHECK(MT8195, p_id)) 1222 1270 reg = CFG_COMP(MT8195, ctx->param, aal.subfrms[index].clip_ofst); 1223 - MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_OUTPUT_OFFSET, 1224 - reg, 0x00FF00FF); 1271 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_AAL_OUTPUT_OFFSET, reg, 1272 + 0x00FF00FF); 1225 1273 1226 1274 if (CFG_CHECK(MT8195, p_id)) 1227 1275 reg = CFG_COMP(MT8195, ctx->param, aal.subfrms[index].clip); 1228 - MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_OUTPUT_SIZE, 1229 - reg, MDP_AAL_OUTPUT_SIZE_MASK); 1276 + MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_OUTPUT_SIZE, reg); 1230 1277 1231 1278 return 0; 1232 1279 } ··· 1242 1293 u16 subsys_id = ctx->comp->subsys_id; 1243 1294 1244 1295 /* Always set MDP_HDR enable to 1 */ 1245 - MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TOP, BIT(0), BIT(0)); 1296 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_HDR_TOP, BIT(0), BIT(0)); 1246 1297 1247 1298 return 0; 1248 1299 } ··· 1257 1308 1258 1309 if (CFG_CHECK(MT8195, p_id)) 1259 1310 reg = CFG_COMP(MT8195, ctx->param, hdr.top); 1260 - MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TOP, reg, BIT(29) | BIT(28)); 1311 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_HDR_TOP, reg, BIT(29) | BIT(28)); 1261 1312 1262 1313 if (CFG_CHECK(MT8195, p_id)) 1263 1314 reg = CFG_COMP(MT8195, ctx->param, hdr.relay); 1264 - MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_RELAY, reg, BIT(0)); 1315 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_HDR_RELAY, reg, BIT(0)); 1265 1316 1266 1317 return 0; 1267 1318 } ··· 1275 1326 1276 1327 if (CFG_CHECK(MT8195, p_id)) 1277 1328 reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].win_size); 1278 - MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TILE_POS, 1279 - reg, MDP_HDR_TILE_POS_MASK); 1329 + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TILE_POS, reg); 1280 1330 1281 1331 if (CFG_CHECK(MT8195, p_id)) 1282 1332 reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].src); 1283 - MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_SIZE_0, reg, 0x1FFF1FFF); 1333 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_HDR_SIZE_0, reg, 0x1FFF1FFF); 1284 1334 1285 1335 if (CFG_CHECK(MT8195, p_id)) 1286 1336 reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].clip_ofst0); 1287 - MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_SIZE_1, reg, 0x1FFF1FFF); 1337 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_HDR_SIZE_1, reg, 0x1FFF1FFF); 1288 1338 1289 1339 if (CFG_CHECK(MT8195, p_id)) 1290 1340 reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].clip_ofst1); 1291 - MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_SIZE_2, reg, 0x1FFF1FFF); 1341 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_HDR_SIZE_2, reg, 0x1FFF1FFF); 1292 1342 1293 1343 if (CFG_CHECK(MT8195, p_id)) 1294 1344 reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hist_ctrl_0); 1295 - MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_HIST_CTRL_0, reg, 0x00003FFF); 1345 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_HDR_HIST_CTRL_0, reg, 0x00003FFF); 1296 1346 1297 1347 if (CFG_CHECK(MT8195, p_id)) 1298 1348 reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hist_ctrl_1); 1299 - MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_HIST_CTRL_1, reg, 0x00003FFF); 1349 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_HDR_HIST_CTRL_1, reg, 0x00003FFF); 1300 1350 1301 1351 if (CFG_CHECK(MT8195, p_id)) 1302 1352 reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hdr_top); 1303 - MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TOP, reg, BIT(6) | BIT(5)); 1353 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_HDR_TOP, reg, BIT(6) | BIT(5)); 1304 1354 1305 1355 /* Enable histogram */ 1306 1356 if (CFG_CHECK(MT8195, p_id)) 1307 1357 reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hist_addr); 1308 - MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_HIST_ADDR, reg, BIT(9)); 1358 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_HDR_HIST_ADDR, reg, BIT(9)); 1309 1359 1310 1360 return 0; 1311 1361 } ··· 1321 1373 phys_addr_t base = ctx->comp->reg_base; 1322 1374 u16 subsys_id = ctx->comp->subsys_id; 1323 1375 1324 - MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TRIGGER, BIT(2), BIT(2)); 1325 - MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TRIGGER, 0x0, BIT(2)); 1376 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_FG_TRIGGER, BIT(2), BIT(2)); 1377 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_FG_TRIGGER, 0x0, BIT(2)); 1326 1378 1327 1379 return 0; 1328 1380 } ··· 1337 1389 1338 1390 if (CFG_CHECK(MT8195, p_id)) 1339 1391 reg = CFG_COMP(MT8195, ctx->param, fg.ctrl_0); 1340 - MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_FG_CTRL_0, reg, BIT(0)); 1392 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_FG_FG_CTRL_0, reg, BIT(0)); 1341 1393 1342 1394 if (CFG_CHECK(MT8195, p_id)) 1343 1395 reg = CFG_COMP(MT8195, ctx->param, fg.ck_en); 1344 - MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_FG_CK_EN, reg, 0x7); 1396 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_FG_FG_CK_EN, reg, 0x7); 1345 1397 1346 1398 return 0; 1347 1399 } ··· 1355 1407 1356 1408 if (CFG_CHECK(MT8195, p_id)) 1357 1409 reg = CFG_COMP(MT8195, ctx->param, fg.subfrms[index].info_0); 1358 - MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TILE_INFO_0, reg, 0xFFFFFFFF); 1410 + MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TILE_INFO_0, reg); 1359 1411 1360 1412 if (CFG_CHECK(MT8195, p_id)) 1361 1413 reg = CFG_COMP(MT8195, ctx->param, fg.subfrms[index].info_1); 1362 - MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TILE_INFO_1, reg, 0xFFFFFFFF); 1414 + MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TILE_INFO_1, reg); 1363 1415 1364 1416 return 0; 1365 1417 } ··· 1376 1428 phys_addr_t base = ctx->comp->reg_base; 1377 1429 u16 subsys_id = ctx->comp->subsys_id; 1378 1430 1379 - MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_EN, 1380 - BIT(0), MDP_OVL_EN_MASK); 1431 + MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_EN, BIT(0)); 1381 1432 1382 1433 /* Set to relay mode */ 1383 - MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_SRC_CON, 1384 - BIT(9), MDP_OVL_SRC_CON_MASK); 1385 - MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_DP_CON, 1386 - BIT(0), MDP_OVL_DP_CON_MASK); 1434 + MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_SRC_CON, BIT(9)); 1435 + MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_DP_CON, BIT(0)); 1387 1436 1388 1437 return 0; 1389 1438 } ··· 1395 1450 1396 1451 if (CFG_CHECK(MT8195, p_id)) 1397 1452 reg = CFG_COMP(MT8195, ctx->param, ovl.L0_con); 1398 - MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_L0_CON, reg, BIT(29) | BIT(28)); 1453 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_OVL_L0_CON, reg, BIT(29) | BIT(28)); 1399 1454 1400 1455 if (CFG_CHECK(MT8195, p_id)) 1401 1456 reg = CFG_COMP(MT8195, ctx->param, ovl.src_con); 1402 - MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_SRC_CON, reg, BIT(0)); 1457 + MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_OVL_SRC_CON, reg, BIT(0)); 1403 1458 1404 1459 return 0; 1405 1460 } ··· 1413 1468 1414 1469 if (CFG_CHECK(MT8195, p_id)) 1415 1470 reg = CFG_COMP(MT8195, ctx->param, ovl.subfrms[index].L0_src_size); 1416 - MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_L0_SRC_SIZE, 1417 - reg, MDP_OVL_L0_SRC_SIZE_MASK); 1471 + MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_L0_SRC_SIZE, reg); 1418 1472 1419 1473 /* Setup output size */ 1420 1474 if (CFG_CHECK(MT8195, p_id)) 1421 1475 reg = CFG_COMP(MT8195, ctx->param, ovl.subfrms[index].roi_size); 1422 - MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_ROI_SIZE, 1423 - reg, MDP_OVL_ROI_SIZE_MASK); 1476 + MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_ROI_SIZE, reg); 1424 1477 1425 1478 return 0; 1426 1479 } ··· 1435 1492 phys_addr_t base = ctx->comp->reg_base; 1436 1493 u16 subsys_id = ctx->comp->subsys_id; 1437 1494 1438 - MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_CON, 1439 - BIT(1), MDP_PAD_CON_MASK); 1495 + MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_CON, BIT(1)); 1440 1496 /* Reset */ 1441 - MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_W_SIZE, 1442 - 0, MDP_PAD_W_SIZE_MASK); 1443 - MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_H_SIZE, 1444 - 0, MDP_PAD_H_SIZE_MASK); 1497 + MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_W_SIZE, 0); 1498 + MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_H_SIZE, 0); 1445 1499 1446 1500 return 0; 1447 1501 } ··· 1452 1512 1453 1513 if (CFG_CHECK(MT8195, p_id)) 1454 1514 reg = CFG_COMP(MT8195, ctx->param, pad.subfrms[index].pic_size); 1455 - MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_PIC_SIZE, 1456 - reg, MDP_PAD_PIC_SIZE_MASK); 1515 + MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_PIC_SIZE, reg); 1457 1516 1458 1517 return 0; 1459 1518 }
+5 -5
drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h
··· 10 10 #include "mtk-mdp3-cmdq.h" 11 11 12 12 #define MM_REG_WRITE_MASK(cmd, id, base, ofst, val, mask) \ 13 - cmdq_pkt_write_mask(&((cmd)->pkt), id, \ 14 - (base) + (ofst), (val), (mask)) 15 - 16 - #define MM_REG_WRITE(cmd, id, base, ofst, val, mask) \ 17 13 do { \ 18 14 typeof(mask) (m) = (mask); \ 19 - MM_REG_WRITE_MASK(cmd, id, base, ofst, val, \ 15 + cmdq_pkt_write_mask(&((cmd)->pkt), id, (base) + (ofst), \ 16 + (val), \ 20 17 (((m) & (ofst##_MASK)) == (ofst##_MASK)) ? \ 21 18 (0xffffffff) : (m)); \ 22 19 } while (0) 20 + 21 + #define MM_REG_WRITE(cmd, id, base, ofst, val) \ 22 + cmdq_pkt_write(&((cmd)->pkt), id, (base) + (ofst), (val)) 23 23 24 24 #define MM_REG_WAIT(cmd, evt) \ 25 25 do { \