tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'spear/pinctrl' into next/pinctrl
* spear/pinctrl:
pinctrl: (cosmetic) fix two entries in DocBook comments
pinctrl: add more info to error msgs in pin_request
CLKDEV: provide helpers for common clock framework
pinctrl: add pinctrl-mxs support
pinctrl: pinctrl-imx: add imx6q pinctrl driver
pinctrl: pinctrl-imx: add imx pinctrl core driver
dt: add of_get_child_count helper function
pinctrl: support gpio request deferred probing
pinctrl: add pinctrl_provide_dummies interface for platforms to use
pinctrl: enhance reporting of errors when loading from DT
pinctrl: add kerneldoc for pinctrl_ops device tree functions
pinctrl: propagate map validation errors
pinctrl: fix dangling comment
pinctrl: fix signed vs unsigned conditionals inside pinmux_map_to_setting
ARM: 7392/1: CLKDEV: Optimize clk_find()
ARM: 7376/1: clkdev: Implement managed clk_get()
This just adds more dependencies that are required in order not to
break the spear pinctrl support.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+7360
-58
+95
Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
+95
Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
···
1
+
* Freescale IOMUX Controller (IOMUXC) for i.MX
2
+
3
+
The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC
4
+
to share one PAD to several functional blocks. The sharing is done by
5
+
multiplexing the PAD input/output signals. For each PAD there are up to
6
+
8 muxing options (called ALT modes). Since different modules require
7
+
different PAD settings (like pull up, keeper, etc) the IOMUXC controls
8
+
also the PAD settings parameters.
9
+
10
+
Please refer to pinctrl-bindings.txt in this directory for details of the
11
+
common pinctrl bindings used by client devices, including the meaning of the
12
+
phrase "pin configuration node".
13
+
14
+
Freescale IMX pin configuration node is a node of a group of pins which can be
15
+
used for a specific device or function. This node represents both mux and config
16
+
of the pins in that group. The 'mux' selects the function mode(also named mux
17
+
mode) this pin can work on and the 'config' configures various pad settings
18
+
such as pull-up, open drain, drive strength, etc.
19
+
20
+
Required properties for iomux controller:
21
+
- compatible: "fsl,<soc>-iomuxc"
22
+
Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
23
+
24
+
Required properties for pin configuration node:
25
+
- fsl,pins: two integers array, represents a group of pins mux and config
26
+
setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
27
+
pin working on a specific function, CONFIG is the pad setting value like
28
+
pull-up on this pin. Please refer to fsl,<soc>-pinctrl.txt for the valid
29
+
pins and functions of each SoC.
30
+
31
+
Bits used for CONFIG:
32
+
NO_PAD_CTL(1 << 31): indicate this pin does not need config.
33
+
34
+
SION(1 << 30): Software Input On Field.
35
+
Force the selected mux mode input path no matter of MUX_MODE functionality.
36
+
By default the input path is determined by functionality of the selected
37
+
mux mode (regular).
38
+
39
+
Other bits are used for PAD setting.
40
+
Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part
41
+
of bits definitions.
42
+
43
+
NOTE:
44
+
Some requirements for using fsl,imx-pinctrl binding:
45
+
1. We have pin function node defined under iomux controller node to represent
46
+
what pinmux functions this SoC supports.
47
+
2. The pin configuration node intends to work on a specific function should
48
+
to be defined under that specific function node.
49
+
The function node's name should represent well about what function
50
+
this group of pins in this pin configuration node are working on.
51
+
3. The driver can use the function node's name and pin configuration node's
52
+
name describe the pin function and group hierarchy.
53
+
For example, Linux IMX pinctrl driver takes the function node's name
54
+
as the function name and pin configuration node's name as group name to
55
+
create the map table.
56
+
4. Each pin configuration node should have a phandle, devices can set pins
57
+
configurations by referring to the phandle of that pin configuration node.
58
+
59
+
Examples:
60
+
usdhc@0219c000 { /* uSDHC4 */
61
+
fsl,card-wired;
62
+
vmmc-supply = <®_3p3v>;
63
+
status = "okay";
64
+
pinctrl-names = "default";
65
+
pinctrl-0 = <&pinctrl_usdhc4_1>;
66
+
};
67
+
68
+
iomuxc@020e0000 {
69
+
compatible = "fsl,imx6q-iomuxc";
70
+
reg = <0x020e0000 0x4000>;
71
+
72
+
/* shared pinctrl settings */
73
+
usdhc4 {
74
+
pinctrl_usdhc4_1: usdhc4grp-1 {
75
+
fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
76
+
1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
77
+
1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
78
+
1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
79
+
1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
80
+
1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
81
+
1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
82
+
1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
83
+
1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
84
+
1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
85
+
};
86
+
};
87
+
....
88
+
};
89
+
Refer to the IOMUXC controller chapter in imx6q datasheet,
90
+
0x17059 means enable hysteresis, 47KOhm Pull Up, 50Mhz speed,
91
+
80Ohm driver strength and Fast Slew Rate.
92
+
User should refer to each SoC spec to set the correct value.
93
+
94
+
TODO: when dtc macro support is available, we can change above raw data
95
+
to dt macro which can get better readability in dts file.
+1628
Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt
+1628
Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt
···
1
+
* Freescale IMX6Q IOMUX Controller
2
+
3
+
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
4
+
and usage.
5
+
6
+
Required properties:
7
+
- compatible: "fsl,imx6q-iomuxc"
8
+
- fsl,pins: two integers array, represents a group of pins mux and config
9
+
setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
10
+
pin working on a specific function, CONFIG is the pad setting value like
11
+
pull-up for this pin. Please refer to imx6q datasheet for the valid pad
12
+
config settings.
13
+
14
+
CONFIG bits definition:
15
+
PAD_CTL_HYS (1 << 16)
16
+
PAD_CTL_PUS_100K_DOWN (0 << 14)
17
+
PAD_CTL_PUS_47K_UP (1 << 14)
18
+
PAD_CTL_PUS_100K_UP (2 << 14)
19
+
PAD_CTL_PUS_22K_UP (3 << 14)
20
+
PAD_CTL_PUE (1 << 13)
21
+
PAD_CTL_PKE (1 << 12)
22
+
PAD_CTL_ODE (1 << 11)
23
+
PAD_CTL_SPEED_LOW (1 << 6)
24
+
PAD_CTL_SPEED_MED (2 << 6)
25
+
PAD_CTL_SPEED_HIGH (3 << 6)
26
+
PAD_CTL_DSE_DISABLE (0 << 3)
27
+
PAD_CTL_DSE_240ohm (1 << 3)
28
+
PAD_CTL_DSE_120ohm (2 << 3)
29
+
PAD_CTL_DSE_80ohm (3 << 3)
30
+
PAD_CTL_DSE_60ohm (4 << 3)
31
+
PAD_CTL_DSE_48ohm (5 << 3)
32
+
PAD_CTL_DSE_40ohm (6 << 3)
33
+
PAD_CTL_DSE_34ohm (7 << 3)
34
+
PAD_CTL_SRE_FAST (1 << 0)
35
+
PAD_CTL_SRE_SLOW (0 << 0)
36
+
37
+
See below for available PIN_FUNC_ID for imx6q:
38
+
MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 0
39
+
MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 1
40
+
MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 2
41
+
MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS 3
42
+
MX6Q_PAD_SD2_DAT1__KPP_COL_7 4
43
+
MX6Q_PAD_SD2_DAT1__GPIO_1_14 5
44
+
MX6Q_PAD_SD2_DAT1__CCM_WAIT 6
45
+
MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0 7
46
+
MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 8
47
+
MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 9
48
+
MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 10
49
+
MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD 11
50
+
MX6Q_PAD_SD2_DAT2__KPP_ROW_6 12
51
+
MX6Q_PAD_SD2_DAT2__GPIO_1_13 13
52
+
MX6Q_PAD_SD2_DAT2__CCM_STOP 14
53
+
MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1 15
54
+
MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 16
55
+
MX6Q_PAD_SD2_DAT0__ECSPI5_MISO 17
56
+
MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD 18
57
+
MX6Q_PAD_SD2_DAT0__KPP_ROW_7 19
58
+
MX6Q_PAD_SD2_DAT0__GPIO_1_15 20
59
+
MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT 21
60
+
MX6Q_PAD_SD2_DAT0__TESTO_2 22
61
+
MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA 23
62
+
MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC 24
63
+
MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK 25
64
+
MX6Q_PAD_RGMII_TXC__GPIO_6_19 26
65
+
MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 27
66
+
MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT 28
67
+
MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY 29
68
+
MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 30
69
+
MX6Q_PAD_RGMII_TD0__GPIO_6_20 31
70
+
MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 32
71
+
MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG 33
72
+
MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 34
73
+
MX6Q_PAD_RGMII_TD1__GPIO_6_21 35
74
+
MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 36
75
+
MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP 37
76
+
MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA 38
77
+
MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 39
78
+
MX6Q_PAD_RGMII_TD2__GPIO_6_22 40
79
+
MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 41
80
+
MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP 42
81
+
MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK 43
82
+
MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 44
83
+
MX6Q_PAD_RGMII_TD3__GPIO_6_23 45
84
+
MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 46
85
+
MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA 47
86
+
MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 48
87
+
MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 49
88
+
MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 50
89
+
MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY 51
90
+
MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 52
91
+
MX6Q_PAD_RGMII_RD0__GPIO_6_25 53
92
+
MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 54
93
+
MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE 55
94
+
MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 56
95
+
MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 57
96
+
MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 58
97
+
MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT 59
98
+
MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL 60
99
+
MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 61
100
+
MX6Q_PAD_RGMII_RD1__GPIO_6_27 62
101
+
MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 63
102
+
MX6Q_PAD_RGMII_RD1__SJC_FAIL 64
103
+
MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA 65
104
+
MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 66
105
+
MX6Q_PAD_RGMII_RD2__GPIO_6_28 67
106
+
MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 68
107
+
MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK 69
108
+
MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 70
109
+
MX6Q_PAD_RGMII_RD3__GPIO_6_29 71
110
+
MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 72
111
+
MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE 73
112
+
MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC 74
113
+
MX6Q_PAD_RGMII_RXC__GPIO_6_30 75
114
+
MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 76
115
+
MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 77
116
+
MX6Q_PAD_EIM_A25__ECSPI4_SS1 78
117
+
MX6Q_PAD_EIM_A25__ECSPI2_RDY 79
118
+
MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 80
119
+
MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS 81
120
+
MX6Q_PAD_EIM_A25__GPIO_5_2 82
121
+
MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE 83
122
+
MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0 84
123
+
MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 85
124
+
MX6Q_PAD_EIM_EB2__ECSPI1_SS0 86
125
+
MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK 87
126
+
MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 88
127
+
MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL 89
128
+
MX6Q_PAD_EIM_EB2__GPIO_2_30 90
129
+
MX6Q_PAD_EIM_EB2__I2C2_SCL 91
130
+
MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 92
131
+
MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 93
132
+
MX6Q_PAD_EIM_D16__ECSPI1_SCLK 94
133
+
MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 95
134
+
MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 96
135
+
MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA 97
136
+
MX6Q_PAD_EIM_D16__GPIO_3_16 98
137
+
MX6Q_PAD_EIM_D16__I2C2_SDA 99
138
+
MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 100
139
+
MX6Q_PAD_EIM_D17__ECSPI1_MISO 101
140
+
MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 102
141
+
MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK 103
142
+
MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT 104
143
+
MX6Q_PAD_EIM_D17__GPIO_3_17 105
144
+
MX6Q_PAD_EIM_D17__I2C3_SCL 106
145
+
MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1 107
146
+
MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 108
147
+
MX6Q_PAD_EIM_D18__ECSPI1_MOSI 109
148
+
MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 110
149
+
MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 111
150
+
MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS 112
151
+
MX6Q_PAD_EIM_D18__GPIO_3_18 113
152
+
MX6Q_PAD_EIM_D18__I2C3_SDA 114
153
+
MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2 115
154
+
MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 116
155
+
MX6Q_PAD_EIM_D19__ECSPI1_SS1 117
156
+
MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 118
157
+
MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 119
158
+
MX6Q_PAD_EIM_D19__UART1_CTS 120
159
+
MX6Q_PAD_EIM_D19__GPIO_3_19 121
160
+
MX6Q_PAD_EIM_D19__EPIT1_EPITO 122
161
+
MX6Q_PAD_EIM_D19__PL301_PER1_HRESP 123
162
+
MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 124
163
+
MX6Q_PAD_EIM_D20__ECSPI4_SS0 125
164
+
MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 126
165
+
MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 127
166
+
MX6Q_PAD_EIM_D20__UART1_RTS 128
167
+
MX6Q_PAD_EIM_D20__GPIO_3_20 129
168
+
MX6Q_PAD_EIM_D20__EPIT2_EPITO 130
169
+
MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 131
170
+
MX6Q_PAD_EIM_D21__ECSPI4_SCLK 132
171
+
MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 133
172
+
MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 134
173
+
MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC 135
174
+
MX6Q_PAD_EIM_D21__GPIO_3_21 136
175
+
MX6Q_PAD_EIM_D21__I2C1_SCL 137
176
+
MX6Q_PAD_EIM_D21__SPDIF_IN1 138
177
+
MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 139
178
+
MX6Q_PAD_EIM_D22__ECSPI4_MISO 140
179
+
MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 141
180
+
MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 142
181
+
MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR 143
182
+
MX6Q_PAD_EIM_D22__GPIO_3_22 144
183
+
MX6Q_PAD_EIM_D22__SPDIF_OUT1 145
184
+
MX6Q_PAD_EIM_D22__PL301_PER1_HWRITE 146
185
+
MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 147
186
+
MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS 148
187
+
MX6Q_PAD_EIM_D23__UART3_CTS 149
188
+
MX6Q_PAD_EIM_D23__UART1_DCD 150
189
+
MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN 151
190
+
MX6Q_PAD_EIM_D23__GPIO_3_23 152
191
+
MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 153
192
+
MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 154
193
+
MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 155
194
+
MX6Q_PAD_EIM_EB3__ECSPI4_RDY 156
195
+
MX6Q_PAD_EIM_EB3__UART3_RTS 157
196
+
MX6Q_PAD_EIM_EB3__UART1_RI 158
197
+
MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC 159
198
+
MX6Q_PAD_EIM_EB3__GPIO_2_31 160
199
+
MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 161
200
+
MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 162
201
+
MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 163
202
+
MX6Q_PAD_EIM_D24__ECSPI4_SS2 164
203
+
MX6Q_PAD_EIM_D24__UART3_TXD 165
204
+
MX6Q_PAD_EIM_D24__ECSPI1_SS2 166
205
+
MX6Q_PAD_EIM_D24__ECSPI2_SS2 167
206
+
MX6Q_PAD_EIM_D24__GPIO_3_24 168
207
+
MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS 169
208
+
MX6Q_PAD_EIM_D24__UART1_DTR 170
209
+
MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 171
210
+
MX6Q_PAD_EIM_D25__ECSPI4_SS3 172
211
+
MX6Q_PAD_EIM_D25__UART3_RXD 173
212
+
MX6Q_PAD_EIM_D25__ECSPI1_SS3 174
213
+
MX6Q_PAD_EIM_D25__ECSPI2_SS3 175
214
+
MX6Q_PAD_EIM_D25__GPIO_3_25 176
215
+
MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC 177
216
+
MX6Q_PAD_EIM_D25__UART1_DSR 178
217
+
MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 179
218
+
MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 180
219
+
MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 181
220
+
MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 182
221
+
MX6Q_PAD_EIM_D26__UART2_TXD 183
222
+
MX6Q_PAD_EIM_D26__GPIO_3_26 184
223
+
MX6Q_PAD_EIM_D26__IPU1_SISG_2 185
224
+
MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 186
225
+
MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 187
226
+
MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 188
227
+
MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 189
228
+
MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 190
229
+
MX6Q_PAD_EIM_D27__UART2_RXD 191
230
+
MX6Q_PAD_EIM_D27__GPIO_3_27 192
231
+
MX6Q_PAD_EIM_D27__IPU1_SISG_3 193
232
+
MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 194
233
+
MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 195
234
+
MX6Q_PAD_EIM_D28__I2C1_SDA 196
235
+
MX6Q_PAD_EIM_D28__ECSPI4_MOSI 197
236
+
MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 198
237
+
MX6Q_PAD_EIM_D28__UART2_CTS 199
238
+
MX6Q_PAD_EIM_D28__GPIO_3_28 200
239
+
MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG 201
240
+
MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 202
241
+
MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 203
242
+
MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 204
243
+
MX6Q_PAD_EIM_D29__ECSPI4_SS0 205
244
+
MX6Q_PAD_EIM_D29__UART2_RTS 206
245
+
MX6Q_PAD_EIM_D29__GPIO_3_29 207
246
+
MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC 208
247
+
MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 209
248
+
MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 210
249
+
MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 211
250
+
MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 212
251
+
MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 213
252
+
MX6Q_PAD_EIM_D30__UART3_CTS 214
253
+
MX6Q_PAD_EIM_D30__GPIO_3_30 215
254
+
MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC 216
255
+
MX6Q_PAD_EIM_D30__PL301_PER1_HPROT_0 217
256
+
MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 218
257
+
MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 219
258
+
MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 220
259
+
MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 221
260
+
MX6Q_PAD_EIM_D31__UART3_RTS 222
261
+
MX6Q_PAD_EIM_D31__GPIO_3_31 223
262
+
MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR 224
263
+
MX6Q_PAD_EIM_D31__PL301_PER1_HPROT_1 225
264
+
MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 226
265
+
MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 227
266
+
MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 228
267
+
MX6Q_PAD_EIM_A24__IPU2_SISG_2 229
268
+
MX6Q_PAD_EIM_A24__IPU1_SISG_2 230
269
+
MX6Q_PAD_EIM_A24__GPIO_5_4 231
270
+
MX6Q_PAD_EIM_A24__PL301_PER1_HPROT_2 232
271
+
MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 233
272
+
MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 234
273
+
MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 235
274
+
MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 236
275
+
MX6Q_PAD_EIM_A23__IPU2_SISG_3 237
276
+
MX6Q_PAD_EIM_A23__IPU1_SISG_3 238
277
+
MX6Q_PAD_EIM_A23__GPIO_6_6 239
278
+
MX6Q_PAD_EIM_A23__PL301_PER1_HPROT_3 240
279
+
MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 241
280
+
MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 242
281
+
MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 243
282
+
MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 244
283
+
MX6Q_PAD_EIM_A22__GPIO_2_16 245
284
+
MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 246
285
+
MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 247
286
+
MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 248
287
+
MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 249
288
+
MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 250
289
+
MX6Q_PAD_EIM_A21__RESERVED_RESERVED 251
290
+
MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 252
291
+
MX6Q_PAD_EIM_A21__GPIO_2_17 253
292
+
MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 254
293
+
MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 255
294
+
MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 256
295
+
MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 257
296
+
MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 258
297
+
MX6Q_PAD_EIM_A20__RESERVED_RESERVED 259
298
+
MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 260
299
+
MX6Q_PAD_EIM_A20__GPIO_2_18 261
300
+
MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 262
301
+
MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 263
302
+
MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 264
303
+
MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 265
304
+
MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 266
305
+
MX6Q_PAD_EIM_A19__RESERVED_RESERVED 267
306
+
MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 268
307
+
MX6Q_PAD_EIM_A19__GPIO_2_19 269
308
+
MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 270
309
+
MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 271
310
+
MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 272
311
+
MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 273
312
+
MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 274
313
+
MX6Q_PAD_EIM_A18__RESERVED_RESERVED 275
314
+
MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 276
315
+
MX6Q_PAD_EIM_A18__GPIO_2_20 277
316
+
MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 278
317
+
MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 279
318
+
MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 280
319
+
MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 281
320
+
MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 282
321
+
MX6Q_PAD_EIM_A17__RESERVED_RESERVED 283
322
+
MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 284
323
+
MX6Q_PAD_EIM_A17__GPIO_2_21 285
324
+
MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 286
325
+
MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 287
326
+
MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 288
327
+
MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK 289
328
+
MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK 290
329
+
MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 291
330
+
MX6Q_PAD_EIM_A16__GPIO_2_22 292
331
+
MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 293
332
+
MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 294
333
+
MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 295
334
+
MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 296
335
+
MX6Q_PAD_EIM_CS0__ECSPI2_SCLK 297
336
+
MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 298
337
+
MX6Q_PAD_EIM_CS0__GPIO_2_23 299
338
+
MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 300
339
+
MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 301
340
+
MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 302
341
+
MX6Q_PAD_EIM_CS1__ECSPI2_MOSI 303
342
+
MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 304
343
+
MX6Q_PAD_EIM_CS1__GPIO_2_24 305
344
+
MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 306
345
+
MX6Q_PAD_EIM_OE__WEIM_WEIM_OE 307
346
+
MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 308
347
+
MX6Q_PAD_EIM_OE__ECSPI2_MISO 309
348
+
MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 310
349
+
MX6Q_PAD_EIM_OE__GPIO_2_25 311
350
+
MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 312
351
+
MX6Q_PAD_EIM_RW__WEIM_WEIM_RW 313
352
+
MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 314
353
+
MX6Q_PAD_EIM_RW__ECSPI2_SS0 315
354
+
MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 316
355
+
MX6Q_PAD_EIM_RW__GPIO_2_26 317
356
+
MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 318
357
+
MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 319
358
+
MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA 320
359
+
MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 321
360
+
MX6Q_PAD_EIM_LBA__ECSPI2_SS1 322
361
+
MX6Q_PAD_EIM_LBA__GPIO_2_27 323
362
+
MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 324
363
+
MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 325
364
+
MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 326
365
+
MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 327
366
+
MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 328
367
+
MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 329
368
+
MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY 330
369
+
MX6Q_PAD_EIM_EB0__GPIO_2_28 331
370
+
MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 332
371
+
MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 333
372
+
MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 334
373
+
MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 335
374
+
MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 336
375
+
MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 337
376
+
MX6Q_PAD_EIM_EB1__GPIO_2_29 338
377
+
MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 339
378
+
MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 340
379
+
MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 341
380
+
MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 342
381
+
MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 343
382
+
MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 344
383
+
MX6Q_PAD_EIM_DA0__GPIO_3_0 345
384
+
MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 346
385
+
MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 347
386
+
MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 348
387
+
MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 349
388
+
MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 350
389
+
MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 351
390
+
MX6Q_PAD_EIM_DA1__USBPHY1_TX_LS_MODE 352
391
+
MX6Q_PAD_EIM_DA1__GPIO_3_1 353
392
+
MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 354
393
+
MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 355
394
+
MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 356
395
+
MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 357
396
+
MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 358
397
+
MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 359
398
+
MX6Q_PAD_EIM_DA2__USBPHY1_TX_HS_MODE 360
399
+
MX6Q_PAD_EIM_DA2__GPIO_3_2 361
400
+
MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 362
401
+
MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 363
402
+
MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 364
403
+
MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 365
404
+
MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 366
405
+
MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 367
406
+
MX6Q_PAD_EIM_DA3__USBPHY1_TX_HIZ 368
407
+
MX6Q_PAD_EIM_DA3__GPIO_3_3 369
408
+
MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 370
409
+
MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 371
410
+
MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 372
411
+
MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 373
412
+
MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 374
413
+
MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 375
414
+
MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN 376
415
+
MX6Q_PAD_EIM_DA4__GPIO_3_4 377
416
+
MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 378
417
+
MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 379
418
+
MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 380
419
+
MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 381
420
+
MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 382
421
+
MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 383
422
+
MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP 384
423
+
MX6Q_PAD_EIM_DA5__GPIO_3_5 385
424
+
MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 386
425
+
MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 387
426
+
MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 388
427
+
MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 389
428
+
MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 390
429
+
MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 391
430
+
MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN 392
431
+
MX6Q_PAD_EIM_DA6__GPIO_3_6 393
432
+
MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 394
433
+
MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 395
434
+
MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 396
435
+
MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 397
436
+
MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 398
437
+
MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 399
438
+
MX6Q_PAD_EIM_DA7__GPIO_3_7 400
439
+
MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 401
440
+
MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 402
441
+
MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 403
442
+
MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 404
443
+
MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 405
444
+
MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 406
445
+
MX6Q_PAD_EIM_DA8__GPIO_3_8 407
446
+
MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 408
447
+
MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 409
448
+
MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 410
449
+
MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 411
450
+
MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 412
451
+
MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 413
452
+
MX6Q_PAD_EIM_DA9__GPIO_3_9 414
453
+
MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 415
454
+
MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 416
455
+
MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 417
456
+
MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 418
457
+
MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 419
458
+
MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 420
459
+
MX6Q_PAD_EIM_DA10__GPIO_3_10 421
460
+
MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 422
461
+
MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 423
462
+
MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 424
463
+
MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 425
464
+
MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC 426
465
+
MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 427
466
+
MX6Q_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 428
467
+
MX6Q_PAD_EIM_DA11__GPIO_3_11 429
468
+
MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 430
469
+
MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 431
470
+
MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 432
471
+
MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 433
472
+
MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC 434
473
+
MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 435
474
+
MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 436
475
+
MX6Q_PAD_EIM_DA12__GPIO_3_12 437
476
+
MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 438
477
+
MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 439
478
+
MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 440
479
+
MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS 441
480
+
MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK 442
481
+
MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 443
482
+
MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 444
483
+
MX6Q_PAD_EIM_DA13__GPIO_3_13 445
484
+
MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 446
485
+
MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 447
486
+
MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 448
487
+
MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS 449
488
+
MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK 450
489
+
MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 451
490
+
MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 452
491
+
MX6Q_PAD_EIM_DA14__GPIO_3_14 453
492
+
MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 454
493
+
MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 455
494
+
MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 456
495
+
MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 457
496
+
MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 458
497
+
MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 459
498
+
MX6Q_PAD_EIM_DA15__GPIO_3_15 460
499
+
MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 461
500
+
MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 462
501
+
MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT 463
502
+
MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B 464
503
+
MX6Q_PAD_EIM_WAIT__GPIO_5_0 465
504
+
MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 466
505
+
MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 467
506
+
MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK 468
507
+
MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 469
508
+
MX6Q_PAD_EIM_BCLK__GPIO_6_31 470
509
+
MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 471
510
+
MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DSP_CLK 472
511
+
MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DSP_CLK 473
512
+
MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 474
513
+
MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 475
514
+
MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 476
515
+
MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 477
516
+
MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 478
517
+
MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 479
518
+
MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 480
519
+
MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 481
520
+
MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 482
521
+
MX6Q_PAD_DI0_PIN15__GPIO_4_17 483
522
+
MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 484
523
+
MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 485
524
+
MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 486
525
+
MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 487
526
+
MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 488
527
+
MX6Q_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 489
528
+
MX6Q_PAD_DI0_PIN2__GPIO_4_18 490
529
+
MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2 491
530
+
MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9 492
531
+
MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 493
532
+
MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 494
533
+
MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 495
534
+
MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 496
535
+
MX6Q_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 497
536
+
MX6Q_PAD_DI0_PIN3__GPIO_4_19 498
537
+
MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 499
538
+
MX6Q_PAD_DI0_PIN3__PL301_PER1_HADDR_10 500
539
+
MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 501
540
+
MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 502
541
+
MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 503
542
+
MX6Q_PAD_DI0_PIN4__USDHC1_WP 504
543
+
MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD 505
544
+
MX6Q_PAD_DI0_PIN4__GPIO_4_20 506
545
+
MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 507
546
+
MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11 508
547
+
MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 509
548
+
MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 510
549
+
MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 511
550
+
MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 512
551
+
MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN 513
552
+
MX6Q_PAD_DISP0_DAT0__GPIO_4_21 514
553
+
MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 515
554
+
MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 516
555
+
MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 517
556
+
MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 518
557
+
MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 519
558
+
MX6Q_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL 520
559
+
MX6Q_PAD_DISP0_DAT1__GPIO_4_22 521
560
+
MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6 522
561
+
MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12 523
562
+
MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 524
563
+
MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 525
564
+
MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 526
565
+
MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 527
566
+
MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE 528
567
+
MX6Q_PAD_DISP0_DAT2__GPIO_4_23 529
568
+
MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7 530
569
+
MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13 531
570
+
MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 532
571
+
MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 533
572
+
MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 534
573
+
MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 535
574
+
MX6Q_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR 536
575
+
MX6Q_PAD_DISP0_DAT3__GPIO_4_24 537
576
+
MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 538
577
+
MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14 539
578
+
MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 540
579
+
MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 541
580
+
MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 542
581
+
MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 543
582
+
MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB 544
583
+
MX6Q_PAD_DISP0_DAT4__GPIO_4_25 545
584
+
MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 546
585
+
MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15 547
586
+
MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 548
587
+
MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 549
588
+
MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 550
589
+
MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS 551
590
+
MX6Q_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS 552
591
+
MX6Q_PAD_DISP0_DAT5__GPIO_4_26 553
592
+
MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10 554
593
+
MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16 555
594
+
MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 556
595
+
MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 557
596
+
MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 558
597
+
MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC 559
598
+
MX6Q_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT 560
599
+
MX6Q_PAD_DISP0_DAT6__GPIO_4_27 561
600
+
MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11 562
601
+
MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17 563
602
+
MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 564
603
+
MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 565
604
+
MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY 566
605
+
MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 567
606
+
MX6Q_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 568
607
+
MX6Q_PAD_DISP0_DAT7__GPIO_4_28 569
608
+
MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12 570
609
+
MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18 571
610
+
MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 572
611
+
MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 573
612
+
MX6Q_PAD_DISP0_DAT8__PWM1_PWMO 574
613
+
MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B 575
614
+
MX6Q_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 576
615
+
MX6Q_PAD_DISP0_DAT8__GPIO_4_29 577
616
+
MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13 578
617
+
MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19 579
618
+
MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 580
619
+
MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 581
620
+
MX6Q_PAD_DISP0_DAT9__PWM2_PWMO 582
621
+
MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B 583
622
+
MX6Q_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 584
623
+
MX6Q_PAD_DISP0_DAT9__GPIO_4_30 585
624
+
MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14 586
625
+
MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20 587
626
+
MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 588
627
+
MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 589
628
+
MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6 590
629
+
MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 591
630
+
MX6Q_PAD_DISP0_DAT10__GPIO_4_31 592
631
+
MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15 593
632
+
MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21 594
633
+
MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 595
634
+
MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 596
635
+
MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 597
636
+
MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 598
637
+
MX6Q_PAD_DISP0_DAT11__GPIO_5_5 599
638
+
MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16 600
639
+
MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22 601
640
+
MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 602
641
+
MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 603
642
+
MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED 604
643
+
MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 605
644
+
MX6Q_PAD_DISP0_DAT12__GPIO_5_6 606
645
+
MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17 607
646
+
MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23 608
647
+
MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 609
648
+
MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 610
649
+
MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS 611
650
+
MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 612
651
+
MX6Q_PAD_DISP0_DAT13__GPIO_5_7 613
652
+
MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18 614
653
+
MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24 615
654
+
MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 616
655
+
MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 617
656
+
MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC 618
657
+
MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 619
658
+
MX6Q_PAD_DISP0_DAT14__GPIO_5_8 620
659
+
MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19 621
660
+
MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 622
661
+
MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 623
662
+
MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 624
663
+
MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 625
664
+
MX6Q_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 626
665
+
MX6Q_PAD_DISP0_DAT15__GPIO_5_9 627
666
+
MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20 628
667
+
MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25 629
668
+
MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 630
669
+
MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 631
670
+
MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI 632
671
+
MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 633
672
+
MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 634
673
+
MX6Q_PAD_DISP0_DAT16__GPIO_5_10 635
674
+
MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21 636
675
+
MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26 637
676
+
MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 638
677
+
MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 639
678
+
MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO 640
679
+
MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 641
680
+
MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 642
681
+
MX6Q_PAD_DISP0_DAT17__GPIO_5_11 643
682
+
MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22 644
683
+
MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27 645
684
+
MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 646
685
+
MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 647
686
+
MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 648
687
+
MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 649
688
+
MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS 650
689
+
MX6Q_PAD_DISP0_DAT18__GPIO_5_12 651
690
+
MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23 652
691
+
MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 653
692
+
MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 654
693
+
MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 655
694
+
MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK 656
695
+
MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 657
696
+
MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC 658
697
+
MX6Q_PAD_DISP0_DAT19__GPIO_5_13 659
698
+
MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24 660
699
+
MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 661
700
+
MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 662
701
+
MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 663
702
+
MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK 664
703
+
MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC 665
704
+
MX6Q_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 666
705
+
MX6Q_PAD_DISP0_DAT20__GPIO_5_14 667
706
+
MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25 668
707
+
MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28 669
708
+
MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 670
709
+
MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 671
710
+
MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI 672
711
+
MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD 673
712
+
MX6Q_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 674
713
+
MX6Q_PAD_DISP0_DAT21__GPIO_5_15 675
714
+
MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26 676
715
+
MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29 677
716
+
MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 678
717
+
MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 679
718
+
MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO 680
719
+
MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS 681
720
+
MX6Q_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 682
721
+
MX6Q_PAD_DISP0_DAT22__GPIO_5_16 683
722
+
MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27 684
723
+
MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30 685
724
+
MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 686
725
+
MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 687
726
+
MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 688
727
+
MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD 689
728
+
MX6Q_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 690
729
+
MX6Q_PAD_DISP0_DAT23__GPIO_5_17 691
730
+
MX6Q_PAD_DISP0_DAT23__MMDC_DEBUG_28 692
731
+
MX6Q_PAD_DISP0_DAT23__PL301_PER1_HADR31 693
732
+
MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED 694
733
+
MX6Q_PAD_ENET_MDIO__ENET_MDIO 695
734
+
MX6Q_PAD_ENET_MDIO__ESAI1_SCKR 696
735
+
MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 697
736
+
MX6Q_PAD_ENET_MDIO__ENET_1588_EVT1_OUT 698
737
+
MX6Q_PAD_ENET_MDIO__GPIO_1_22 699
738
+
MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK 700
739
+
MX6Q_PAD_ENET_REF_CLK__RESERVED_RSRVED 701
740
+
MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 702
741
+
MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR 703
742
+
MX6Q_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 704
743
+
MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 705
744
+
MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK 706
745
+
MX6Q_PAD_ENET_REF_CLK__USBPHY1_RX_SQH 707
746
+
MX6Q_PAD_ENET_RX_ER__ENET_RX_ER 708
747
+
MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR 709
748
+
MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 710
749
+
MX6Q_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT 711
750
+
MX6Q_PAD_ENET_RX_ER__GPIO_1_24 712
751
+
MX6Q_PAD_ENET_RX_ER__PHY_TDI 713
752
+
MX6Q_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD 714
753
+
MX6Q_PAD_ENET_CRS_DV__RESERVED_RSRVED 715
754
+
MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN 716
755
+
MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT 717
756
+
MX6Q_PAD_ENET_CRS_DV__SPDIF_EXTCLK 718
757
+
MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 719
758
+
MX6Q_PAD_ENET_CRS_DV__PHY_TDO 720
759
+
MX6Q_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD 721
760
+
MX6Q_PAD_ENET_RXD1__MLB_MLBSIG 722
761
+
MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 723
762
+
MX6Q_PAD_ENET_RXD1__ESAI1_FST 724
763
+
MX6Q_PAD_ENET_RXD1__ENET_1588_EVT3_OUT 725
764
+
MX6Q_PAD_ENET_RXD1__GPIO_1_26 726
765
+
MX6Q_PAD_ENET_RXD1__PHY_TCK 727
766
+
MX6Q_PAD_ENET_RXD1__USBPHY1_RX_DISCON 728
767
+
MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT 729
768
+
MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 730
769
+
MX6Q_PAD_ENET_RXD0__ESAI1_HCKT 731
770
+
MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 732
771
+
MX6Q_PAD_ENET_RXD0__GPIO_1_27 733
772
+
MX6Q_PAD_ENET_RXD0__PHY_TMS 734
773
+
MX6Q_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV 735
774
+
MX6Q_PAD_ENET_TX_EN__RESERVED_RSRVED 736
775
+
MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 737
776
+
MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 738
777
+
MX6Q_PAD_ENET_TX_EN__GPIO_1_28 739
778
+
MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI 740
779
+
MX6Q_PAD_ENET_TX_EN__USBPHY2_RX_SQH 741
780
+
MX6Q_PAD_ENET_TXD1__MLB_MLBCLK 742
781
+
MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 743
782
+
MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 744
783
+
MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 745
784
+
MX6Q_PAD_ENET_TXD1__GPIO_1_29 746
785
+
MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO 747
786
+
MX6Q_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD 748
787
+
MX6Q_PAD_ENET_TXD0__RESERVED_RSRVED 749
788
+
MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 750
789
+
MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 751
790
+
MX6Q_PAD_ENET_TXD0__GPIO_1_30 752
791
+
MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK 753
792
+
MX6Q_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD 754
793
+
MX6Q_PAD_ENET_MDC__MLB_MLBDAT 755
794
+
MX6Q_PAD_ENET_MDC__ENET_MDC 756
795
+
MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 757
796
+
MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN 758
797
+
MX6Q_PAD_ENET_MDC__GPIO_1_31 759
798
+
MX6Q_PAD_ENET_MDC__SATA_PHY_TMS 760
799
+
MX6Q_PAD_ENET_MDC__USBPHY2_RX_DISCON 761
800
+
MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 762
801
+
MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 763
802
+
MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 764
803
+
MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 765
804
+
MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 766
805
+
MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 767
806
+
MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 768
807
+
MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 769
808
+
MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 770
809
+
MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 771
810
+
MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 772
811
+
MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 773
812
+
MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 774
813
+
MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 775
814
+
MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 776
815
+
MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 777
816
+
MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 778
817
+
MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 779
818
+
MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 780
819
+
MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 781
820
+
MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 782
821
+
MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 783
822
+
MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 784
823
+
MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 785
824
+
MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 786
825
+
MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 787
826
+
MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 788
827
+
MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 789
828
+
MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 790
829
+
MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 791
830
+
MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 792
831
+
MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 793
832
+
MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 794
833
+
MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 795
834
+
MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 796
835
+
MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 797
836
+
MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 798
837
+
MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 799
838
+
MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 800
839
+
MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 801
840
+
MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 802
841
+
MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 803
842
+
MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 804
843
+
MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 805
844
+
MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 806
845
+
MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 807
846
+
MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 808
847
+
MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 809
848
+
MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 810
849
+
MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 811
850
+
MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 812
851
+
MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 813
852
+
MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 814
853
+
MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 815
854
+
MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 816
855
+
MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 817
856
+
MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS 818
857
+
MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 819
858
+
MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 820
859
+
MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS 821
860
+
MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET 822
861
+
MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 823
862
+
MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 824
863
+
MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 825
864
+
MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 826
865
+
MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 827
866
+
MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 828
867
+
MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 829
868
+
MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 830
869
+
MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 831
870
+
MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE 832
871
+
MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 833
872
+
MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 834
873
+
MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 835
874
+
MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 836
875
+
MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 837
876
+
MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 838
877
+
MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 839
878
+
MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 840
879
+
MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 841
880
+
MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 842
881
+
MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 843
882
+
MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 844
883
+
MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 845
884
+
MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 846
885
+
MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 847
886
+
MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 848
887
+
MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 849
888
+
MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 850
889
+
MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 851
890
+
MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 852
891
+
MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 853
892
+
MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 854
893
+
MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 855
894
+
MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 856
895
+
MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 857
896
+
MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 858
897
+
MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 859
898
+
MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 860
899
+
MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 861
900
+
MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 862
901
+
MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 863
902
+
MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 864
903
+
MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 865
904
+
MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 866
905
+
MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 867
906
+
MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 868
907
+
MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 869
908
+
MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 870
909
+
MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 871
910
+
MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 872
911
+
MX6Q_PAD_KEY_COL0__ECSPI1_SCLK 873
912
+
MX6Q_PAD_KEY_COL0__ENET_RDATA_3 874
913
+
MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC 875
914
+
MX6Q_PAD_KEY_COL0__KPP_COL_0 876
915
+
MX6Q_PAD_KEY_COL0__UART4_TXD 877
916
+
MX6Q_PAD_KEY_COL0__GPIO_4_6 878
917
+
MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT 879
918
+
MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST 880
919
+
MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI 881
920
+
MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 882
921
+
MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 883
922
+
MX6Q_PAD_KEY_ROW0__KPP_ROW_0 884
923
+
MX6Q_PAD_KEY_ROW0__UART4_RXD 885
924
+
MX6Q_PAD_KEY_ROW0__GPIO_4_7 886
925
+
MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT 887
926
+
MX6Q_PAD_KEY_ROW0__PL301_PER1_HADR_0 888
927
+
MX6Q_PAD_KEY_COL1__ECSPI1_MISO 889
928
+
MX6Q_PAD_KEY_COL1__ENET_MDIO 890
929
+
MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 891
930
+
MX6Q_PAD_KEY_COL1__KPP_COL_1 892
931
+
MX6Q_PAD_KEY_COL1__UART5_TXD 893
932
+
MX6Q_PAD_KEY_COL1__GPIO_4_8 894
933
+
MX6Q_PAD_KEY_COL1__USDHC1_VSELECT 895
934
+
MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1 896
935
+
MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 897
936
+
MX6Q_PAD_KEY_ROW1__ENET_COL 898
937
+
MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 899
938
+
MX6Q_PAD_KEY_ROW1__KPP_ROW_1 900
939
+
MX6Q_PAD_KEY_ROW1__UART5_RXD 901
940
+
MX6Q_PAD_KEY_ROW1__GPIO_4_9 902
941
+
MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT 903
942
+
MX6Q_PAD_KEY_ROW1__PL301_PER1_HADDR_2 904
943
+
MX6Q_PAD_KEY_COL2__ECSPI1_SS1 905
944
+
MX6Q_PAD_KEY_COL2__ENET_RDATA_2 906
945
+
MX6Q_PAD_KEY_COL2__CAN1_TXCAN 907
946
+
MX6Q_PAD_KEY_COL2__KPP_COL_2 908
947
+
MX6Q_PAD_KEY_COL2__ENET_MDC 909
948
+
MX6Q_PAD_KEY_COL2__GPIO_4_10 910
949
+
MX6Q_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP 911
950
+
MX6Q_PAD_KEY_COL2__PL301_PER1_HADDR_3 912
951
+
MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 913
952
+
MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 914
953
+
MX6Q_PAD_KEY_ROW2__CAN1_RXCAN 915
954
+
MX6Q_PAD_KEY_ROW2__KPP_ROW_2 916
955
+
MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT 917
956
+
MX6Q_PAD_KEY_ROW2__GPIO_4_11 918
957
+
MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 919
958
+
MX6Q_PAD_KEY_ROW2__PL301_PER1_HADR_4 920
959
+
MX6Q_PAD_KEY_COL3__ECSPI1_SS3 921
960
+
MX6Q_PAD_KEY_COL3__ENET_CRS 922
961
+
MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL 923
962
+
MX6Q_PAD_KEY_COL3__KPP_COL_3 924
963
+
MX6Q_PAD_KEY_COL3__I2C2_SCL 925
964
+
MX6Q_PAD_KEY_COL3__GPIO_4_12 926
965
+
MX6Q_PAD_KEY_COL3__SPDIF_IN1 927
966
+
MX6Q_PAD_KEY_COL3__PL301_PER1_HADR_5 928
967
+
MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT 929
968
+
MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK 930
969
+
MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 931
970
+
MX6Q_PAD_KEY_ROW3__KPP_ROW_3 932
971
+
MX6Q_PAD_KEY_ROW3__I2C2_SDA 933
972
+
MX6Q_PAD_KEY_ROW3__GPIO_4_13 934
973
+
MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT 935
974
+
MX6Q_PAD_KEY_ROW3__PL301_PER1_HADR_6 936
975
+
MX6Q_PAD_KEY_COL4__CAN2_TXCAN 937
976
+
MX6Q_PAD_KEY_COL4__IPU1_SISG_4 938
977
+
MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC 939
978
+
MX6Q_PAD_KEY_COL4__KPP_COL_4 940
979
+
MX6Q_PAD_KEY_COL4__UART5_RTS 941
980
+
MX6Q_PAD_KEY_COL4__GPIO_4_14 942
981
+
MX6Q_PAD_KEY_COL4__MMDC_DEBUG_49 943
982
+
MX6Q_PAD_KEY_COL4__PL301_PER1_HADDR_7 944
983
+
MX6Q_PAD_KEY_ROW4__CAN2_RXCAN 945
984
+
MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 946
985
+
MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR 947
986
+
MX6Q_PAD_KEY_ROW4__KPP_ROW_4 948
987
+
MX6Q_PAD_KEY_ROW4__UART5_CTS 949
988
+
MX6Q_PAD_KEY_ROW4__GPIO_4_15 950
989
+
MX6Q_PAD_KEY_ROW4__MMDC_DEBUG_50 951
990
+
MX6Q_PAD_KEY_ROW4__PL301_PER1_HADR_8 952
991
+
MX6Q_PAD_GPIO_0__CCM_CLKO 953
992
+
MX6Q_PAD_GPIO_0__KPP_COL_5 954
993
+
MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK 955
994
+
MX6Q_PAD_GPIO_0__EPIT1_EPITO 956
995
+
MX6Q_PAD_GPIO_0__GPIO_1_0 957
996
+
MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR 958
997
+
MX6Q_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 959
998
+
MX6Q_PAD_GPIO_1__ESAI1_SCKR 960
999
+
MX6Q_PAD_GPIO_1__WDOG2_WDOG_B 961
1000
+
MX6Q_PAD_GPIO_1__KPP_ROW_5 962
1001
+
MX6Q_PAD_GPIO_1__PWM2_PWMO 963
1002
+
MX6Q_PAD_GPIO_1__GPIO_1_1 964
1003
+
MX6Q_PAD_GPIO_1__USDHC1_CD 965
1004
+
MX6Q_PAD_GPIO_1__SRC_TESTER_ACK 966
1005
+
MX6Q_PAD_GPIO_9__ESAI1_FSR 967
1006
+
MX6Q_PAD_GPIO_9__WDOG1_WDOG_B 968
1007
+
MX6Q_PAD_GPIO_9__KPP_COL_6 969
1008
+
MX6Q_PAD_GPIO_9__CCM_REF_EN_B 970
1009
+
MX6Q_PAD_GPIO_9__PWM1_PWMO 971
1010
+
MX6Q_PAD_GPIO_9__GPIO_1_9 972
1011
+
MX6Q_PAD_GPIO_9__USDHC1_WP 973
1012
+
MX6Q_PAD_GPIO_9__SRC_EARLY_RST 974
1013
+
MX6Q_PAD_GPIO_3__ESAI1_HCKR 975
1014
+
MX6Q_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 976
1015
+
MX6Q_PAD_GPIO_3__I2C3_SCL 977
1016
+
MX6Q_PAD_GPIO_3__ANATOP_24M_OUT 978
1017
+
MX6Q_PAD_GPIO_3__CCM_CLKO2 979
1018
+
MX6Q_PAD_GPIO_3__GPIO_1_3 980
1019
+
MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC 981
1020
+
MX6Q_PAD_GPIO_3__MLB_MLBCLK 982
1021
+
MX6Q_PAD_GPIO_6__ESAI1_SCKT 983
1022
+
MX6Q_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 984
1023
+
MX6Q_PAD_GPIO_6__I2C3_SDA 985
1024
+
MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 986
1025
+
MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB 987
1026
+
MX6Q_PAD_GPIO_6__GPIO_1_6 988
1027
+
MX6Q_PAD_GPIO_6__USDHC2_LCTL 989
1028
+
MX6Q_PAD_GPIO_6__MLB_MLBSIG 990
1029
+
MX6Q_PAD_GPIO_2__ESAI1_FST 991
1030
+
MX6Q_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 992
1031
+
MX6Q_PAD_GPIO_2__KPP_ROW_6 993
1032
+
MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 994
1033
+
MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 995
1034
+
MX6Q_PAD_GPIO_2__GPIO_1_2 996
1035
+
MX6Q_PAD_GPIO_2__USDHC2_WP 997
1036
+
MX6Q_PAD_GPIO_2__MLB_MLBDAT 998
1037
+
MX6Q_PAD_GPIO_4__ESAI1_HCKT 999
1038
+
MX6Q_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 1000
1039
+
MX6Q_PAD_GPIO_4__KPP_COL_7 1001
1040
+
MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 1002
1041
+
MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 1003
1042
+
MX6Q_PAD_GPIO_4__GPIO_1_4 1004
1043
+
MX6Q_PAD_GPIO_4__USDHC2_CD 1005
1044
+
MX6Q_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA 1006
1045
+
MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 1007
1046
+
MX6Q_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 1008
1047
+
MX6Q_PAD_GPIO_5__KPP_ROW_7 1009
1048
+
MX6Q_PAD_GPIO_5__CCM_CLKO 1010
1049
+
MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 1011
1050
+
MX6Q_PAD_GPIO_5__GPIO_1_5 1012
1051
+
MX6Q_PAD_GPIO_5__I2C3_SCL 1013
1052
+
MX6Q_PAD_GPIO_5__CHEETAH_EVENTI 1014
1053
+
MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 1015
1054
+
MX6Q_PAD_GPIO_7__ECSPI5_RDY 1016
1055
+
MX6Q_PAD_GPIO_7__EPIT1_EPITO 1017
1056
+
MX6Q_PAD_GPIO_7__CAN1_TXCAN 1018
1057
+
MX6Q_PAD_GPIO_7__UART2_TXD 1019
1058
+
MX6Q_PAD_GPIO_7__GPIO_1_7 1020
1059
+
MX6Q_PAD_GPIO_7__SPDIF_PLOCK 1021
1060
+
MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE 1022
1061
+
MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 1023
1062
+
MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT 1024
1063
+
MX6Q_PAD_GPIO_8__EPIT2_EPITO 1025
1064
+
MX6Q_PAD_GPIO_8__CAN1_RXCAN 1026
1065
+
MX6Q_PAD_GPIO_8__UART2_RXD 1027
1066
+
MX6Q_PAD_GPIO_8__GPIO_1_8 1028
1067
+
MX6Q_PAD_GPIO_8__SPDIF_SRCLK 1029
1068
+
MX6Q_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK 1030
1069
+
MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 1031
1070
+
MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN 1032
1071
+
MX6Q_PAD_GPIO_16__ENET_ETHERNET_REF_OUT 1033
1072
+
MX6Q_PAD_GPIO_16__USDHC1_LCTL 1034
1073
+
MX6Q_PAD_GPIO_16__SPDIF_IN1 1035
1074
+
MX6Q_PAD_GPIO_16__GPIO_7_11 1036
1075
+
MX6Q_PAD_GPIO_16__I2C3_SDA 1037
1076
+
MX6Q_PAD_GPIO_16__SJC_DE_B 1038
1077
+
MX6Q_PAD_GPIO_17__ESAI1_TX0 1039
1078
+
MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN 1040
1079
+
MX6Q_PAD_GPIO_17__CCM_PMIC_RDY 1041
1080
+
MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 1042
1081
+
MX6Q_PAD_GPIO_17__SPDIF_OUT1 1043
1082
+
MX6Q_PAD_GPIO_17__GPIO_7_12 1044
1083
+
MX6Q_PAD_GPIO_17__SJC_JTAG_ACT 1045
1084
+
MX6Q_PAD_GPIO_18__ESAI1_TX1 1046
1085
+
MX6Q_PAD_GPIO_18__ENET_RX_CLK 1047
1086
+
MX6Q_PAD_GPIO_18__USDHC3_VSELECT 1048
1087
+
MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 1049
1088
+
MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK 1050
1089
+
MX6Q_PAD_GPIO_18__GPIO_7_13 1051
1090
+
MX6Q_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 1052
1091
+
MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST 1053
1092
+
MX6Q_PAD_GPIO_19__KPP_COL_5 1054
1093
+
MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT 1055
1094
+
MX6Q_PAD_GPIO_19__SPDIF_OUT1 1056
1095
+
MX6Q_PAD_GPIO_19__CCM_CLKO 1057
1096
+
MX6Q_PAD_GPIO_19__ECSPI1_RDY 1058
1097
+
MX6Q_PAD_GPIO_19__GPIO_4_5 1059
1098
+
MX6Q_PAD_GPIO_19__ENET_TX_ER 1060
1099
+
MX6Q_PAD_GPIO_19__SRC_INT_BOOT 1061
1100
+
MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 1062
1101
+
MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 1063
1102
+
MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 1064
1103
+
MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 1065
1104
+
MX6Q_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 1066
1105
+
MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO 1067
1106
+
MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 1068
1107
+
MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 1069
1108
+
MX6Q_PAD_CSI0_MCLK__CCM_CLKO 1070
1109
+
MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 1071
1110
+
MX6Q_PAD_CSI0_MCLK__GPIO_5_19 1072
1111
+
MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 1073
1112
+
MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL 1074
1113
+
MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN 1075
1114
+
MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 1076
1115
+
MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 1077
1116
+
MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 1078
1117
+
MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 1079
1118
+
MX6Q_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 1080
1119
+
MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK 1081
1120
+
MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 1082
1121
+
MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 1083
1122
+
MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 1084
1123
+
MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 1085
1124
+
MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 1086
1125
+
MX6Q_PAD_CSI0_VSYNC__MMDC_DEBUG_32 1087
1126
+
MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 1088
1127
+
MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 1089
1128
+
MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 1090
1129
+
MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK 1091
1130
+
MX6Q_PAD_CSI0_DAT4__KPP_COL_5 1092
1131
+
MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 1093
1132
+
MX6Q_PAD_CSI0_DAT4__GPIO_5_22 1094
1133
+
MX6Q_PAD_CSI0_DAT4__MMDC_DEBUG_43 1095
1134
+
MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 1096
1135
+
MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 1097
1136
+
MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 1098
1137
+
MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI 1099
1138
+
MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 1100
1139
+
MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 1101
1140
+
MX6Q_PAD_CSI0_DAT5__GPIO_5_23 1102
1141
+
MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 1103
1142
+
MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 1104
1143
+
MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 1105
1144
+
MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 1106
1145
+
MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO 1107
1146
+
MX6Q_PAD_CSI0_DAT6__KPP_COL_6 1108
1147
+
MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 1109
1148
+
MX6Q_PAD_CSI0_DAT6__GPIO_5_24 1110
1149
+
MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 1111
1150
+
MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 1112
1151
+
MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 1113
1152
+
MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 1114
1153
+
MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 1115
1154
+
MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 1116
1155
+
MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 1117
1156
+
MX6Q_PAD_CSI0_DAT7__GPIO_5_25 1118
1157
+
MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 1119
1158
+
MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 1120
1159
+
MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 1121
1160
+
MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 1122
1161
+
MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK 1123
1162
+
MX6Q_PAD_CSI0_DAT8__KPP_COL_7 1124
1163
+
MX6Q_PAD_CSI0_DAT8__I2C1_SDA 1125
1164
+
MX6Q_PAD_CSI0_DAT8__GPIO_5_26 1126
1165
+
MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 1127
1166
+
MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 1128
1167
+
MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 1129
1168
+
MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 1130
1169
+
MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI 1131
1170
+
MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 1132
1171
+
MX6Q_PAD_CSI0_DAT9__I2C1_SCL 1133
1172
+
MX6Q_PAD_CSI0_DAT9__GPIO_5_27 1134
1173
+
MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 1135
1174
+
MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 1136
1175
+
MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 1137
1176
+
MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC 1138
1177
+
MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO 1139
1178
+
MX6Q_PAD_CSI0_DAT10__UART1_TXD 1140
1179
+
MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 1141
1180
+
MX6Q_PAD_CSI0_DAT10__GPIO_5_28 1142
1181
+
MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 1143
1182
+
MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 1144
1183
+
MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 1145
1184
+
MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS 1146
1185
+
MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 1147
1186
+
MX6Q_PAD_CSI0_DAT11__UART1_RXD 1148
1187
+
MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 1149
1188
+
MX6Q_PAD_CSI0_DAT11__GPIO_5_29 1150
1189
+
MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 1151
1190
+
MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 1152
1191
+
MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 1153
1192
+
MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 1154
1193
+
MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 1155
1194
+
MX6Q_PAD_CSI0_DAT12__UART4_TXD 1156
1195
+
MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 1157
1196
+
MX6Q_PAD_CSI0_DAT12__GPIO_5_30 1158
1197
+
MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 1159
1198
+
MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 1160
1199
+
MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 1161
1200
+
MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 1162
1201
+
MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 1163
1202
+
MX6Q_PAD_CSI0_DAT13__UART4_RXD 1164
1203
+
MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 1165
1204
+
MX6Q_PAD_CSI0_DAT13__GPIO_5_31 1166
1205
+
MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 1167
1206
+
MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 1168
1207
+
MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 1169
1208
+
MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 1170
1209
+
MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 1171
1210
+
MX6Q_PAD_CSI0_DAT14__UART5_TXD 1172
1211
+
MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 1173
1212
+
MX6Q_PAD_CSI0_DAT14__GPIO_6_0 1174
1213
+
MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 1175
1214
+
MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 1176
1215
+
MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 1177
1216
+
MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 1178
1217
+
MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 1179
1218
+
MX6Q_PAD_CSI0_DAT15__UART5_RXD 1180
1219
+
MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 1181
1220
+
MX6Q_PAD_CSI0_DAT15__GPIO_6_1 1182
1221
+
MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 1183
1222
+
MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 1184
1223
+
MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 1185
1224
+
MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 1186
1225
+
MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 1187
1226
+
MX6Q_PAD_CSI0_DAT16__UART4_RTS 1188
1227
+
MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 1189
1228
+
MX6Q_PAD_CSI0_DAT16__GPIO_6_2 1190
1229
+
MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 1191
1230
+
MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 1192
1231
+
MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 1193
1232
+
MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 1194
1233
+
MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 1195
1234
+
MX6Q_PAD_CSI0_DAT17__UART4_CTS 1196
1235
+
MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 1197
1236
+
MX6Q_PAD_CSI0_DAT17__GPIO_6_3 1198
1237
+
MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 1199
1238
+
MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 1200
1239
+
MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 1201
1240
+
MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 1202
1241
+
MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 1203
1242
+
MX6Q_PAD_CSI0_DAT18__UART5_RTS 1204
1243
+
MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 1205
1244
+
MX6Q_PAD_CSI0_DAT18__GPIO_6_4 1206
1245
+
MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 1207
1246
+
MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 1208
1247
+
MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 1209
1248
+
MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 1210
1249
+
MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 1211
1250
+
MX6Q_PAD_CSI0_DAT19__UART5_CTS 1212
1251
+
MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 1213
1252
+
MX6Q_PAD_CSI0_DAT19__GPIO_6_5 1214
1253
+
MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 1215
1254
+
MX6Q_PAD_CSI0_DAT19__ANATOP_TESTO_9 1216
1255
+
MX6Q_PAD_JTAG_TMS__SJC_TMS 1217
1256
+
MX6Q_PAD_JTAG_MOD__SJC_MOD 1218
1257
+
MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB 1219
1258
+
MX6Q_PAD_JTAG_TDI__SJC_TDI 1220
1259
+
MX6Q_PAD_JTAG_TCK__SJC_TCK 1221
1260
+
MX6Q_PAD_JTAG_TDO__SJC_TDO 1222
1261
+
MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 1223
1262
+
MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 1224
1263
+
MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 1225
1264
+
MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 1226
1265
+
MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 1227
1266
+
MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 1228
1267
+
MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 1229
1268
+
MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 1230
1269
+
MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 1231
1270
+
MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 1232
1271
+
MX6Q_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 1233
1272
+
MX6Q_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM 1234
1273
+
MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ 1235
1274
+
MX6Q_PAD_POR_B__SRC_POR_B 1236
1275
+
MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 1237
1276
+
MX6Q_PAD_RESET_IN_B__SRC_RESET_B 1238
1277
+
MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 1239
1278
+
MX6Q_PAD_TEST_MODE__TCU_TEST_MODE 1240
1279
+
MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 1241
1280
+
MX6Q_PAD_SD3_DAT7__UART1_TXD 1242
1281
+
MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 1243
1282
+
MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 1244
1283
+
MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 1245
1284
+
MX6Q_PAD_SD3_DAT7__GPIO_6_17 1246
1285
+
MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 1247
1286
+
MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV 1248
1287
+
MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 1249
1288
+
MX6Q_PAD_SD3_DAT6__UART1_RXD 1250
1289
+
MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 1251
1290
+
MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 1252
1291
+
MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 1253
1292
+
MX6Q_PAD_SD3_DAT6__GPIO_6_18 1254
1293
+
MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 1255
1294
+
MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10 1256
1295
+
MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 1257
1296
+
MX6Q_PAD_SD3_DAT5__UART2_TXD 1258
1297
+
MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 1259
1298
+
MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 1260
1299
+
MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 1261
1300
+
MX6Q_PAD_SD3_DAT5__GPIO_7_0 1262
1301
+
MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 1263
1302
+
MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11 1264
1303
+
MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 1265
1304
+
MX6Q_PAD_SD3_DAT4__UART2_RXD 1266
1305
+
MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 1267
1306
+
MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 1268
1307
+
MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 1269
1308
+
MX6Q_PAD_SD3_DAT4__GPIO_7_1 1270
1309
+
MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 1271
1310
+
MX6Q_PAD_SD3_DAT4__ANATOP_TESTO_12 1272
1311
+
MX6Q_PAD_SD3_CMD__USDHC3_CMD 1273
1312
+
MX6Q_PAD_SD3_CMD__UART2_CTS 1274
1313
+
MX6Q_PAD_SD3_CMD__CAN1_TXCAN 1275
1314
+
MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 1276
1315
+
MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 1277
1316
+
MX6Q_PAD_SD3_CMD__GPIO_7_2 1278
1317
+
MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 1279
1318
+
MX6Q_PAD_SD3_CMD__ANATOP_TESTO_13 1280
1319
+
MX6Q_PAD_SD3_CLK__USDHC3_CLK 1281
1320
+
MX6Q_PAD_SD3_CLK__UART2_RTS 1282
1321
+
MX6Q_PAD_SD3_CLK__CAN1_RXCAN 1283
1322
+
MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 1284
1323
+
MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 1285
1324
+
MX6Q_PAD_SD3_CLK__GPIO_7_3 1286
1325
+
MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 1287
1326
+
MX6Q_PAD_SD3_CLK__ANATOP_TESTO_14 1288
1327
+
MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 1289
1328
+
MX6Q_PAD_SD3_DAT0__UART1_CTS 1290
1329
+
MX6Q_PAD_SD3_DAT0__CAN2_TXCAN 1291
1330
+
MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 1292
1331
+
MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 1293
1332
+
MX6Q_PAD_SD3_DAT0__GPIO_7_4 1294
1333
+
MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 1295
1334
+
MX6Q_PAD_SD3_DAT0__ANATOP_TESTO_15 1296
1335
+
MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 1297
1336
+
MX6Q_PAD_SD3_DAT1__UART1_RTS 1298
1337
+
MX6Q_PAD_SD3_DAT1__CAN2_RXCAN 1299
1338
+
MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 1300
1339
+
MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 1301
1340
+
MX6Q_PAD_SD3_DAT1__GPIO_7_5 1302
1341
+
MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 1303
1342
+
MX6Q_PAD_SD3_DAT1__ANATOP_TESTI_0 1304
1343
+
MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 1305
1344
+
MX6Q_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 1306
1345
+
MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 1307
1346
+
MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 1308
1347
+
MX6Q_PAD_SD3_DAT2__GPIO_7_6 1309
1348
+
MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 1310
1349
+
MX6Q_PAD_SD3_DAT2__ANATOP_TESTI_1 1311
1350
+
MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 1312
1351
+
MX6Q_PAD_SD3_DAT3__UART3_CTS 1313
1352
+
MX6Q_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 1314
1353
+
MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 1315
1354
+
MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 1316
1355
+
MX6Q_PAD_SD3_DAT3__GPIO_7_7 1317
1356
+
MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 1318
1357
+
MX6Q_PAD_SD3_DAT3__ANATOP_TESTI_2 1319
1358
+
MX6Q_PAD_SD3_RST__USDHC3_RST 1320
1359
+
MX6Q_PAD_SD3_RST__UART3_RTS 1321
1360
+
MX6Q_PAD_SD3_RST__PCIE_CTRL_MUX_30 1322
1361
+
MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 1323
1362
+
MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 1324
1363
+
MX6Q_PAD_SD3_RST__GPIO_7_8 1325
1364
+
MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 1326
1365
+
MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 1327
1366
+
MX6Q_PAD_NANDF_CLE__RAWNAND_CLE 1328
1367
+
MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 1329
1368
+
MX6Q_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 1330
1369
+
MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 1331
1370
+
MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 1332
1371
+
MX6Q_PAD_NANDF_CLE__GPIO_6_7 1333
1372
+
MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 1334
1373
+
MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 1335
1374
+
MX6Q_PAD_NANDF_ALE__RAWNAND_ALE 1336
1375
+
MX6Q_PAD_NANDF_ALE__USDHC4_RST 1337
1376
+
MX6Q_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 1338
1377
+
MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 1339
1378
+
MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 1340
1379
+
MX6Q_PAD_NANDF_ALE__GPIO_6_8 1341
1380
+
MX6Q_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 1342
1381
+
MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 1343
1382
+
MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN 1344
1383
+
MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 1345
1384
+
MX6Q_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 1346
1385
+
MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 1347
1386
+
MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 1348
1387
+
MX6Q_PAD_NANDF_WP_B__GPIO_6_9 1349
1388
+
MX6Q_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 1350
1389
+
MX6Q_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 1351
1390
+
MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 1352
1391
+
MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 1353
1392
+
MX6Q_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 1354
1393
+
MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 1355
1394
+
MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 1356
1395
+
MX6Q_PAD_NANDF_RB0__GPIO_6_10 1357
1396
+
MX6Q_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 1358
1397
+
MX6Q_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 1359
1398
+
MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N 1360
1399
+
MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 1361
1400
+
MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 1362
1401
+
MX6Q_PAD_NANDF_CS0__GPIO_6_11 1363
1402
+
MX6Q_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 1364
1403
+
MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N 1365
1404
+
MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT 1366
1405
+
MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT 1367
1406
+
MX6Q_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 1368
1407
+
MX6Q_PAD_NANDF_CS1__GPIO_6_14 1369
1408
+
MX6Q_PAD_NANDF_CS1__PL301_PER1_HRDYOUT 1370
1409
+
MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N 1371
1410
+
MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 1372
1411
+
MX6Q_PAD_NANDF_CS2__ESAI1_TX0 1373
1412
+
MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE 1374
1413
+
MX6Q_PAD_NANDF_CS2__CCM_CLKO2 1375
1414
+
MX6Q_PAD_NANDF_CS2__GPIO_6_15 1376
1415
+
MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 1377
1416
+
MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N 1378
1417
+
MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 1379
1418
+
MX6Q_PAD_NANDF_CS3__ESAI1_TX1 1380
1419
+
MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 1381
1420
+
MX6Q_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 1382
1421
+
MX6Q_PAD_NANDF_CS3__GPIO_6_16 1383
1422
+
MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 1384
1423
+
MX6Q_PAD_NANDF_CS3__TPSMP_CLK 1385
1424
+
MX6Q_PAD_SD4_CMD__USDHC4_CMD 1386
1425
+
MX6Q_PAD_SD4_CMD__RAWNAND_RDN 1387
1426
+
MX6Q_PAD_SD4_CMD__UART3_TXD 1388
1427
+
MX6Q_PAD_SD4_CMD__PCIE_CTRL_MUX_5 1389
1428
+
MX6Q_PAD_SD4_CMD__GPIO_7_9 1390
1429
+
MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR 1391
1430
+
MX6Q_PAD_SD4_CLK__USDHC4_CLK 1392
1431
+
MX6Q_PAD_SD4_CLK__RAWNAND_WRN 1393
1432
+
MX6Q_PAD_SD4_CLK__UART3_RXD 1394
1433
+
MX6Q_PAD_SD4_CLK__PCIE_CTRL_MUX_6 1395
1434
+
MX6Q_PAD_SD4_CLK__GPIO_7_10 1396
1435
+
MX6Q_PAD_NANDF_D0__RAWNAND_D0 1397
1436
+
MX6Q_PAD_NANDF_D0__USDHC1_DAT4 1398
1437
+
MX6Q_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 1399
1438
+
MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 1400
1439
+
MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 1401
1440
+
MX6Q_PAD_NANDF_D0__GPIO_2_0 1402
1441
+
MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 1403
1442
+
MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 1404
1443
+
MX6Q_PAD_NANDF_D1__RAWNAND_D1 1405
1444
+
MX6Q_PAD_NANDF_D1__USDHC1_DAT5 1406
1445
+
MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 1407
1446
+
MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 1408
1447
+
MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 1409
1448
+
MX6Q_PAD_NANDF_D1__GPIO_2_1 1410
1449
+
MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 1411
1450
+
MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 1412
1451
+
MX6Q_PAD_NANDF_D2__RAWNAND_D2 1413
1452
+
MX6Q_PAD_NANDF_D2__USDHC1_DAT6 1414
1453
+
MX6Q_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 1415
1454
+
MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 1416
1455
+
MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 1417
1456
+
MX6Q_PAD_NANDF_D2__GPIO_2_2 1418
1457
+
MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 1419
1458
+
MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 1420
1459
+
MX6Q_PAD_NANDF_D3__RAWNAND_D3 1421
1460
+
MX6Q_PAD_NANDF_D3__USDHC1_DAT7 1422
1461
+
MX6Q_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 1423
1462
+
MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 1424
1463
+
MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 1425
1464
+
MX6Q_PAD_NANDF_D3__GPIO_2_3 1426
1465
+
MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 1427
1466
+
MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 1428
1467
+
MX6Q_PAD_NANDF_D4__RAWNAND_D4 1429
1468
+
MX6Q_PAD_NANDF_D4__USDHC2_DAT4 1430
1469
+
MX6Q_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 1431
1470
+
MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 1432
1471
+
MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 1433
1472
+
MX6Q_PAD_NANDF_D4__GPIO_2_4 1434
1473
+
MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 1435
1474
+
MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 1436
1475
+
MX6Q_PAD_NANDF_D5__RAWNAND_D5 1437
1476
+
MX6Q_PAD_NANDF_D5__USDHC2_DAT5 1438
1477
+
MX6Q_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 1439
1478
+
MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 1440
1479
+
MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 1441
1480
+
MX6Q_PAD_NANDF_D5__GPIO_2_5 1442
1481
+
MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 1443
1482
+
MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 1444
1483
+
MX6Q_PAD_NANDF_D6__RAWNAND_D6 1445
1484
+
MX6Q_PAD_NANDF_D6__USDHC2_DAT6 1446
1485
+
MX6Q_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 1447
1486
+
MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 1448
1487
+
MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 1449
1488
+
MX6Q_PAD_NANDF_D6__GPIO_2_6 1450
1489
+
MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 1451
1490
+
MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 1452
1491
+
MX6Q_PAD_NANDF_D7__RAWNAND_D7 1453
1492
+
MX6Q_PAD_NANDF_D7__USDHC2_DAT7 1454
1493
+
MX6Q_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 1455
1494
+
MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 1456
1495
+
MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 1457
1496
+
MX6Q_PAD_NANDF_D7__GPIO_2_7 1458
1497
+
MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 1459
1498
+
MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 1460
1499
+
MX6Q_PAD_SD4_DAT0__RAWNAND_D8 1461
1500
+
MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 1462
1501
+
MX6Q_PAD_SD4_DAT0__RAWNAND_DQS 1463
1502
+
MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 1464
1503
+
MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 1465
1504
+
MX6Q_PAD_SD4_DAT0__GPIO_2_8 1466
1505
+
MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 1467
1506
+
MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 1468
1507
+
MX6Q_PAD_SD4_DAT1__RAWNAND_D9 1469
1508
+
MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 1470
1509
+
MX6Q_PAD_SD4_DAT1__PWM3_PWMO 1471
1510
+
MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 1472
1511
+
MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 1473
1512
+
MX6Q_PAD_SD4_DAT1__GPIO_2_9 1474
1513
+
MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 1475
1514
+
MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 1476
1515
+
MX6Q_PAD_SD4_DAT2__RAWNAND_D10 1477
1516
+
MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 1478
1517
+
MX6Q_PAD_SD4_DAT2__PWM4_PWMO 1479
1518
+
MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 1480
1519
+
MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 1481
1520
+
MX6Q_PAD_SD4_DAT2__GPIO_2_10 1482
1521
+
MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 1483
1522
+
MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 1484
1523
+
MX6Q_PAD_SD4_DAT3__RAWNAND_D11 1485
1524
+
MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 1486
1525
+
MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 1487
1526
+
MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 1488
1527
+
MX6Q_PAD_SD4_DAT3__GPIO_2_11 1489
1528
+
MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 1490
1529
+
MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 1491
1530
+
MX6Q_PAD_SD4_DAT4__RAWNAND_D12 1492
1531
+
MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 1493
1532
+
MX6Q_PAD_SD4_DAT4__UART2_RXD 1494
1533
+
MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 1495
1534
+
MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 1496
1535
+
MX6Q_PAD_SD4_DAT4__GPIO_2_12 1497
1536
+
MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 1498
1537
+
MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 1499
1538
+
MX6Q_PAD_SD4_DAT5__RAWNAND_D13 1500
1539
+
MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 1501
1540
+
MX6Q_PAD_SD4_DAT5__UART2_RTS 1502
1541
+
MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 1503
1542
+
MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 1504
1543
+
MX6Q_PAD_SD4_DAT5__GPIO_2_13 1505
1544
+
MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 1506
1545
+
MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 1507
1546
+
MX6Q_PAD_SD4_DAT6__RAWNAND_D14 1508
1547
+
MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 1509
1548
+
MX6Q_PAD_SD4_DAT6__UART2_CTS 1510
1549
+
MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 1511
1550
+
MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 1512
1551
+
MX6Q_PAD_SD4_DAT6__GPIO_2_14 1513
1552
+
MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 1514
1553
+
MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 1515
1554
+
MX6Q_PAD_SD4_DAT7__RAWNAND_D15 1516
1555
+
MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 1517
1556
+
MX6Q_PAD_SD4_DAT7__UART2_TXD 1518
1557
+
MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 1519
1558
+
MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 1520
1559
+
MX6Q_PAD_SD4_DAT7__GPIO_2_15 1521
1560
+
MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 1522
1561
+
MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 1523
1562
+
MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 1524
1563
+
MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 1525
1564
+
MX6Q_PAD_SD1_DAT1__PWM3_PWMO 1526
1565
+
MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 1527
1566
+
MX6Q_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 1528
1567
+
MX6Q_PAD_SD1_DAT1__GPIO_1_17 1529
1568
+
MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 1530
1569
+
MX6Q_PAD_SD1_DAT1__ANATOP_TESTO_8 1531
1570
+
MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 1532
1571
+
MX6Q_PAD_SD1_DAT0__ECSPI5_MISO 1533
1572
+
MX6Q_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS 1534
1573
+
MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 1535
1574
+
MX6Q_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 1536
1575
+
MX6Q_PAD_SD1_DAT0__GPIO_1_16 1537
1576
+
MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 1538
1577
+
MX6Q_PAD_SD1_DAT0__ANATOP_TESTO_7 1539
1578
+
MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 1540
1579
+
MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 1541
1580
+
MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 1542
1581
+
MX6Q_PAD_SD1_DAT3__PWM1_PWMO 1543
1582
+
MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B 1544
1583
+
MX6Q_PAD_SD1_DAT3__GPIO_1_21 1545
1584
+
MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB 1546
1585
+
MX6Q_PAD_SD1_DAT3__ANATOP_TESTO_6 1547
1586
+
MX6Q_PAD_SD1_CMD__USDHC1_CMD 1548
1587
+
MX6Q_PAD_SD1_CMD__ECSPI5_MOSI 1549
1588
+
MX6Q_PAD_SD1_CMD__PWM4_PWMO 1550
1589
+
MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 1551
1590
+
MX6Q_PAD_SD1_CMD__GPIO_1_18 1552
1591
+
MX6Q_PAD_SD1_CMD__ANATOP_TESTO_5 1553
1592
+
MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 1554
1593
+
MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 1555
1594
+
MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 1556
1595
+
MX6Q_PAD_SD1_DAT2__PWM2_PWMO 1557
1596
+
MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B 1558
1597
+
MX6Q_PAD_SD1_DAT2__GPIO_1_19 1559
1598
+
MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB 1560
1599
+
MX6Q_PAD_SD1_DAT2__ANATOP_TESTO_4 1561
1600
+
MX6Q_PAD_SD1_CLK__USDHC1_CLK 1562
1601
+
MX6Q_PAD_SD1_CLK__ECSPI5_SCLK 1563
1602
+
MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT 1564
1603
+
MX6Q_PAD_SD1_CLK__GPT_CLKIN 1565
1604
+
MX6Q_PAD_SD1_CLK__GPIO_1_20 1566
1605
+
MX6Q_PAD_SD1_CLK__PHY_DTB_0 1567
1606
+
MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 1568
1607
+
MX6Q_PAD_SD2_CLK__USDHC2_CLK 1569
1608
+
MX6Q_PAD_SD2_CLK__ECSPI5_SCLK 1570
1609
+
MX6Q_PAD_SD2_CLK__KPP_COL_5 1571
1610
+
MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS 1572
1611
+
MX6Q_PAD_SD2_CLK__PCIE_CTRL_MUX_9 1573
1612
+
MX6Q_PAD_SD2_CLK__GPIO_1_10 1574
1613
+
MX6Q_PAD_SD2_CLK__PHY_DTB_1 1575
1614
+
MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 1576
1615
+
MX6Q_PAD_SD2_CMD__USDHC2_CMD 1577
1616
+
MX6Q_PAD_SD2_CMD__ECSPI5_MOSI 1578
1617
+
MX6Q_PAD_SD2_CMD__KPP_ROW_5 1579
1618
+
MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC 1580
1619
+
MX6Q_PAD_SD2_CMD__PCIE_CTRL_MUX_10 1581
1620
+
MX6Q_PAD_SD2_CMD__GPIO_1_11 1582
1621
+
MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 1583
1622
+
MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 1584
1623
+
MX6Q_PAD_SD2_DAT3__KPP_COL_6 1585
1624
+
MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC 1586
1625
+
MX6Q_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 1587
1626
+
MX6Q_PAD_SD2_DAT3__GPIO_1_12 1588
1627
+
MX6Q_PAD_SD2_DAT3__SJC_DONE 1589
1628
+
MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 1590
+918
Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt
+918
Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt
···
1
+
* Freescale MXS Pin Controller
2
+
3
+
The pins controlled by mxs pin controller are organized in banks, each bank
4
+
has 32 pins. Each pin has 4 multiplexing functions, and generally, the 4th
5
+
function is GPIO. The configuration on the pins includes drive strength,
6
+
voltage and pull-up.
7
+
8
+
Required properties:
9
+
- compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
10
+
- reg: Should contain the register physical address and length for the
11
+
pin controller.
12
+
13
+
Please refer to pinctrl-bindings.txt in this directory for details of the
14
+
common pinctrl bindings used by client devices.
15
+
16
+
The node of mxs pin controller acts as a container for an arbitrary number of
17
+
subnodes. Each of these subnodes represents some desired configuration for
18
+
a group of pins, and only affects those parameters that are explicitly listed.
19
+
In other words, a subnode that describes a drive strength parameter implies no
20
+
information about pull-up. For this reason, even seemingly boolean values are
21
+
actually tristates in this binding: unspecified, off, or on. Unspecified is
22
+
represented as an absent property, and off/on are represented as integer
23
+
values 0 and 1.
24
+
25
+
Those subnodes under mxs pin controller node will fall into two categories.
26
+
One is to set up a group of pins for a function, both mux selection and pin
27
+
configurations, and it's called group node in the binding document. The other
28
+
one is to adjust the pin configuration for some particular pins that need a
29
+
different configuration than what is defined in group node. The binding
30
+
document calls this type of node config node.
31
+
32
+
On mxs, there is no hardware pin group. The pin group in this binding only
33
+
means a group of pins put together for particular peripheral to work in
34
+
particular function, like SSP0 functioning as mmc0-8bit. That said, the
35
+
group node should include all the pins needed for one function rather than
36
+
having these pins defined in several group nodes. It also means each of
37
+
"pinctrl-*" phandle in client device node should only have one group node
38
+
pointed in there, while the phandle can have multiple config node referenced
39
+
there to adjust configurations for some pins in the group.
40
+
41
+
Required subnode-properties:
42
+
- fsl,pinmux-ids: An integer array. Each integer in the array specify a pin
43
+
with given mux function, with bank, pin and mux packed as below.
44
+
45
+
[15..12] : bank number
46
+
[11..4] : pin number
47
+
[3..0] : mux selection
48
+
49
+
This integer with mux selection packed is used as an entity by both group
50
+
and config nodes to identify a pin. The mux selection in the integer takes
51
+
effects only on group node, and will get ignored by driver with config node,
52
+
since config node is only meant to set up pin configurations.
53
+
54
+
Valid values for these integers are listed below.
55
+
56
+
- reg: Should be the index of the group nodes for same function. This property
57
+
is required only for group nodes, and should not be present in any config
58
+
nodes.
59
+
60
+
Optional subnode-properties:
61
+
- fsl,drive-strength: Integer.
62
+
0: 4 mA
63
+
1: 8 mA
64
+
2: 12 mA
65
+
3: 16 mA
66
+
- fsl,voltage: Integer.
67
+
0: 1.8 V
68
+
1: 3.3 V
69
+
- fsl,pull-up: Integer.
70
+
0: Disable the internal pull-up
71
+
1: Enable the internal pull-up
72
+
73
+
Examples:
74
+
75
+
pinctrl@80018000 {
76
+
#address-cells = <1>;
77
+
#size-cells = <0>;
78
+
compatible = "fsl,imx28-pinctrl";
79
+
reg = <0x80018000 2000>;
80
+
81
+
mmc0_8bit_pins_a: mmc0-8bit@0 {
82
+
reg = <0>;
83
+
fsl,pinmux-ids = <
84
+
0x2000 0x2010 0x2020 0x2030
85
+
0x2040 0x2050 0x2060 0x2070
86
+
0x2080 0x2090 0x20a0>;
87
+
fsl,drive-strength = <1>;
88
+
fsl,voltage = <1>;
89
+
fsl,pull-up = <1>;
90
+
};
91
+
92
+
mmc_cd_cfg: mmc-cd-cfg {
93
+
fsl,pinmux-ids = <0x2090>;
94
+
fsl,pull-up = <0>;
95
+
};
96
+
97
+
mmc_sck_cfg: mmc-sck-cfg {
98
+
fsl,pinmux-ids = <0x20a0>;
99
+
fsl,drive-strength = <2>;
100
+
fsl,pull-up = <0>;
101
+
};
102
+
};
103
+
104
+
In this example, group node mmc0-8bit defines a group of pins for mxs SSP0
105
+
to function as a 8-bit mmc device, with 8mA, 3.3V and pull-up configurations
106
+
applied on all these pins. And config nodes mmc-cd-cfg and mmc-sck-cfg are
107
+
adjusting the configuration for pins card-detection and clock from what group
108
+
node mmc0-8bit defines. Only the configuration properties to be adjusted need
109
+
to be listed in the config nodes.
110
+
111
+
Valid values for i.MX28 pinmux-id:
112
+
113
+
pinmux id
114
+
------ --
115
+
MX28_PAD_GPMI_D00__GPMI_D0 0x0000
116
+
MX28_PAD_GPMI_D01__GPMI_D1 0x0010
117
+
MX28_PAD_GPMI_D02__GPMI_D2 0x0020
118
+
MX28_PAD_GPMI_D03__GPMI_D3 0x0030
119
+
MX28_PAD_GPMI_D04__GPMI_D4 0x0040
120
+
MX28_PAD_GPMI_D05__GPMI_D5 0x0050
121
+
MX28_PAD_GPMI_D06__GPMI_D6 0x0060
122
+
MX28_PAD_GPMI_D07__GPMI_D7 0x0070
123
+
MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100
124
+
MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110
125
+
MX28_PAD_GPMI_CE2N__GPMI_CE2N 0x0120
126
+
MX28_PAD_GPMI_CE3N__GPMI_CE3N 0x0130
127
+
MX28_PAD_GPMI_RDY0__GPMI_READY0 0x0140
128
+
MX28_PAD_GPMI_RDY1__GPMI_READY1 0x0150
129
+
MX28_PAD_GPMI_RDY2__GPMI_READY2 0x0160
130
+
MX28_PAD_GPMI_RDY3__GPMI_READY3 0x0170
131
+
MX28_PAD_GPMI_RDN__GPMI_RDN 0x0180
132
+
MX28_PAD_GPMI_WRN__GPMI_WRN 0x0190
133
+
MX28_PAD_GPMI_ALE__GPMI_ALE 0x01a0
134
+
MX28_PAD_GPMI_CLE__GPMI_CLE 0x01b0
135
+
MX28_PAD_GPMI_RESETN__GPMI_RESETN 0x01c0
136
+
MX28_PAD_LCD_D00__LCD_D0 0x1000
137
+
MX28_PAD_LCD_D01__LCD_D1 0x1010
138
+
MX28_PAD_LCD_D02__LCD_D2 0x1020
139
+
MX28_PAD_LCD_D03__LCD_D3 0x1030
140
+
MX28_PAD_LCD_D04__LCD_D4 0x1040
141
+
MX28_PAD_LCD_D05__LCD_D5 0x1050
142
+
MX28_PAD_LCD_D06__LCD_D6 0x1060
143
+
MX28_PAD_LCD_D07__LCD_D7 0x1070
144
+
MX28_PAD_LCD_D08__LCD_D8 0x1080
145
+
MX28_PAD_LCD_D09__LCD_D9 0x1090
146
+
MX28_PAD_LCD_D10__LCD_D10 0x10a0
147
+
MX28_PAD_LCD_D11__LCD_D11 0x10b0
148
+
MX28_PAD_LCD_D12__LCD_D12 0x10c0
149
+
MX28_PAD_LCD_D13__LCD_D13 0x10d0
150
+
MX28_PAD_LCD_D14__LCD_D14 0x10e0
151
+
MX28_PAD_LCD_D15__LCD_D15 0x10f0
152
+
MX28_PAD_LCD_D16__LCD_D16 0x1100
153
+
MX28_PAD_LCD_D17__LCD_D17 0x1110
154
+
MX28_PAD_LCD_D18__LCD_D18 0x1120
155
+
MX28_PAD_LCD_D19__LCD_D19 0x1130
156
+
MX28_PAD_LCD_D20__LCD_D20 0x1140
157
+
MX28_PAD_LCD_D21__LCD_D21 0x1150
158
+
MX28_PAD_LCD_D22__LCD_D22 0x1160
159
+
MX28_PAD_LCD_D23__LCD_D23 0x1170
160
+
MX28_PAD_LCD_RD_E__LCD_RD_E 0x1180
161
+
MX28_PAD_LCD_WR_RWN__LCD_WR_RWN 0x1190
162
+
MX28_PAD_LCD_RS__LCD_RS 0x11a0
163
+
MX28_PAD_LCD_CS__LCD_CS 0x11b0
164
+
MX28_PAD_LCD_VSYNC__LCD_VSYNC 0x11c0
165
+
MX28_PAD_LCD_HSYNC__LCD_HSYNC 0x11d0
166
+
MX28_PAD_LCD_DOTCLK__LCD_DOTCLK 0x11e0
167
+
MX28_PAD_LCD_ENABLE__LCD_ENABLE 0x11f0
168
+
MX28_PAD_SSP0_DATA0__SSP0_D0 0x2000
169
+
MX28_PAD_SSP0_DATA1__SSP0_D1 0x2010
170
+
MX28_PAD_SSP0_DATA2__SSP0_D2 0x2020
171
+
MX28_PAD_SSP0_DATA3__SSP0_D3 0x2030
172
+
MX28_PAD_SSP0_DATA4__SSP0_D4 0x2040
173
+
MX28_PAD_SSP0_DATA5__SSP0_D5 0x2050
174
+
MX28_PAD_SSP0_DATA6__SSP0_D6 0x2060
175
+
MX28_PAD_SSP0_DATA7__SSP0_D7 0x2070
176
+
MX28_PAD_SSP0_CMD__SSP0_CMD 0x2080
177
+
MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT 0x2090
178
+
MX28_PAD_SSP0_SCK__SSP0_SCK 0x20a0
179
+
MX28_PAD_SSP1_SCK__SSP1_SCK 0x20c0
180
+
MX28_PAD_SSP1_CMD__SSP1_CMD 0x20d0
181
+
MX28_PAD_SSP1_DATA0__SSP1_D0 0x20e0
182
+
MX28_PAD_SSP1_DATA3__SSP1_D3 0x20f0
183
+
MX28_PAD_SSP2_SCK__SSP2_SCK 0x2100
184
+
MX28_PAD_SSP2_MOSI__SSP2_CMD 0x2110
185
+
MX28_PAD_SSP2_MISO__SSP2_D0 0x2120
186
+
MX28_PAD_SSP2_SS0__SSP2_D3 0x2130
187
+
MX28_PAD_SSP2_SS1__SSP2_D4 0x2140
188
+
MX28_PAD_SSP2_SS2__SSP2_D5 0x2150
189
+
MX28_PAD_SSP3_SCK__SSP3_SCK 0x2180
190
+
MX28_PAD_SSP3_MOSI__SSP3_CMD 0x2190
191
+
MX28_PAD_SSP3_MISO__SSP3_D0 0x21a0
192
+
MX28_PAD_SSP3_SS0__SSP3_D3 0x21b0
193
+
MX28_PAD_AUART0_RX__AUART0_RX 0x3000
194
+
MX28_PAD_AUART0_TX__AUART0_TX 0x3010
195
+
MX28_PAD_AUART0_CTS__AUART0_CTS 0x3020
196
+
MX28_PAD_AUART0_RTS__AUART0_RTS 0x3030
197
+
MX28_PAD_AUART1_RX__AUART1_RX 0x3040
198
+
MX28_PAD_AUART1_TX__AUART1_TX 0x3050
199
+
MX28_PAD_AUART1_CTS__AUART1_CTS 0x3060
200
+
MX28_PAD_AUART1_RTS__AUART1_RTS 0x3070
201
+
MX28_PAD_AUART2_RX__AUART2_RX 0x3080
202
+
MX28_PAD_AUART2_TX__AUART2_TX 0x3090
203
+
MX28_PAD_AUART2_CTS__AUART2_CTS 0x30a0
204
+
MX28_PAD_AUART2_RTS__AUART2_RTS 0x30b0
205
+
MX28_PAD_AUART3_RX__AUART3_RX 0x30c0
206
+
MX28_PAD_AUART3_TX__AUART3_TX 0x30d0
207
+
MX28_PAD_AUART3_CTS__AUART3_CTS 0x30e0
208
+
MX28_PAD_AUART3_RTS__AUART3_RTS 0x30f0
209
+
MX28_PAD_PWM0__PWM_0 0x3100
210
+
MX28_PAD_PWM1__PWM_1 0x3110
211
+
MX28_PAD_PWM2__PWM_2 0x3120
212
+
MX28_PAD_SAIF0_MCLK__SAIF0_MCLK 0x3140
213
+
MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK 0x3150
214
+
MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK 0x3160
215
+
MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 0x3170
216
+
MX28_PAD_I2C0_SCL__I2C0_SCL 0x3180
217
+
MX28_PAD_I2C0_SDA__I2C0_SDA 0x3190
218
+
MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 0x31a0
219
+
MX28_PAD_SPDIF__SPDIF_TX 0x31b0
220
+
MX28_PAD_PWM3__PWM_3 0x31c0
221
+
MX28_PAD_PWM4__PWM_4 0x31d0
222
+
MX28_PAD_LCD_RESET__LCD_RESET 0x31e0
223
+
MX28_PAD_ENET0_MDC__ENET0_MDC 0x4000
224
+
MX28_PAD_ENET0_MDIO__ENET0_MDIO 0x4010
225
+
MX28_PAD_ENET0_RX_EN__ENET0_RX_EN 0x4020
226
+
MX28_PAD_ENET0_RXD0__ENET0_RXD0 0x4030
227
+
MX28_PAD_ENET0_RXD1__ENET0_RXD1 0x4040
228
+
MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK 0x4050
229
+
MX28_PAD_ENET0_TX_EN__ENET0_TX_EN 0x4060
230
+
MX28_PAD_ENET0_TXD0__ENET0_TXD0 0x4070
231
+
MX28_PAD_ENET0_TXD1__ENET0_TXD1 0x4080
232
+
MX28_PAD_ENET0_RXD2__ENET0_RXD2 0x4090
233
+
MX28_PAD_ENET0_RXD3__ENET0_RXD3 0x40a0
234
+
MX28_PAD_ENET0_TXD2__ENET0_TXD2 0x40b0
235
+
MX28_PAD_ENET0_TXD3__ENET0_TXD3 0x40c0
236
+
MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK 0x40d0
237
+
MX28_PAD_ENET0_COL__ENET0_COL 0x40e0
238
+
MX28_PAD_ENET0_CRS__ENET0_CRS 0x40f0
239
+
MX28_PAD_ENET_CLK__CLKCTRL_ENET 0x4100
240
+
MX28_PAD_JTAG_RTCK__JTAG_RTCK 0x4140
241
+
MX28_PAD_EMI_D00__EMI_DATA0 0x5000
242
+
MX28_PAD_EMI_D01__EMI_DATA1 0x5010
243
+
MX28_PAD_EMI_D02__EMI_DATA2 0x5020
244
+
MX28_PAD_EMI_D03__EMI_DATA3 0x5030
245
+
MX28_PAD_EMI_D04__EMI_DATA4 0x5040
246
+
MX28_PAD_EMI_D05__EMI_DATA5 0x5050
247
+
MX28_PAD_EMI_D06__EMI_DATA6 0x5060
248
+
MX28_PAD_EMI_D07__EMI_DATA7 0x5070
249
+
MX28_PAD_EMI_D08__EMI_DATA8 0x5080
250
+
MX28_PAD_EMI_D09__EMI_DATA9 0x5090
251
+
MX28_PAD_EMI_D10__EMI_DATA10 0x50a0
252
+
MX28_PAD_EMI_D11__EMI_DATA11 0x50b0
253
+
MX28_PAD_EMI_D12__EMI_DATA12 0x50c0
254
+
MX28_PAD_EMI_D13__EMI_DATA13 0x50d0
255
+
MX28_PAD_EMI_D14__EMI_DATA14 0x50e0
256
+
MX28_PAD_EMI_D15__EMI_DATA15 0x50f0
257
+
MX28_PAD_EMI_ODT0__EMI_ODT0 0x5100
258
+
MX28_PAD_EMI_DQM0__EMI_DQM0 0x5110
259
+
MX28_PAD_EMI_ODT1__EMI_ODT1 0x5120
260
+
MX28_PAD_EMI_DQM1__EMI_DQM1 0x5130
261
+
MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK 0x5140
262
+
MX28_PAD_EMI_CLK__EMI_CLK 0x5150
263
+
MX28_PAD_EMI_DQS0__EMI_DQS0 0x5160
264
+
MX28_PAD_EMI_DQS1__EMI_DQS1 0x5170
265
+
MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN 0x51a0
266
+
MX28_PAD_EMI_A00__EMI_ADDR0 0x6000
267
+
MX28_PAD_EMI_A01__EMI_ADDR1 0x6010
268
+
MX28_PAD_EMI_A02__EMI_ADDR2 0x6020
269
+
MX28_PAD_EMI_A03__EMI_ADDR3 0x6030
270
+
MX28_PAD_EMI_A04__EMI_ADDR4 0x6040
271
+
MX28_PAD_EMI_A05__EMI_ADDR5 0x6050
272
+
MX28_PAD_EMI_A06__EMI_ADDR6 0x6060
273
+
MX28_PAD_EMI_A07__EMI_ADDR7 0x6070
274
+
MX28_PAD_EMI_A08__EMI_ADDR8 0x6080
275
+
MX28_PAD_EMI_A09__EMI_ADDR9 0x6090
276
+
MX28_PAD_EMI_A10__EMI_ADDR10 0x60a0
277
+
MX28_PAD_EMI_A11__EMI_ADDR11 0x60b0
278
+
MX28_PAD_EMI_A12__EMI_ADDR12 0x60c0
279
+
MX28_PAD_EMI_A13__EMI_ADDR13 0x60d0
280
+
MX28_PAD_EMI_A14__EMI_ADDR14 0x60e0
281
+
MX28_PAD_EMI_BA0__EMI_BA0 0x6100
282
+
MX28_PAD_EMI_BA1__EMI_BA1 0x6110
283
+
MX28_PAD_EMI_BA2__EMI_BA2 0x6120
284
+
MX28_PAD_EMI_CASN__EMI_CASN 0x6130
285
+
MX28_PAD_EMI_RASN__EMI_RASN 0x6140
286
+
MX28_PAD_EMI_WEN__EMI_WEN 0x6150
287
+
MX28_PAD_EMI_CE0N__EMI_CE0N 0x6160
288
+
MX28_PAD_EMI_CE1N__EMI_CE1N 0x6170
289
+
MX28_PAD_EMI_CKE__EMI_CKE 0x6180
290
+
MX28_PAD_GPMI_D00__SSP1_D0 0x0001
291
+
MX28_PAD_GPMI_D01__SSP1_D1 0x0011
292
+
MX28_PAD_GPMI_D02__SSP1_D2 0x0021
293
+
MX28_PAD_GPMI_D03__SSP1_D3 0x0031
294
+
MX28_PAD_GPMI_D04__SSP1_D4 0x0041
295
+
MX28_PAD_GPMI_D05__SSP1_D5 0x0051
296
+
MX28_PAD_GPMI_D06__SSP1_D6 0x0061
297
+
MX28_PAD_GPMI_D07__SSP1_D7 0x0071
298
+
MX28_PAD_GPMI_CE0N__SSP3_D0 0x0101
299
+
MX28_PAD_GPMI_CE1N__SSP3_D3 0x0111
300
+
MX28_PAD_GPMI_CE2N__CAN1_TX 0x0121
301
+
MX28_PAD_GPMI_CE3N__CAN1_RX 0x0131
302
+
MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT 0x0141
303
+
MX28_PAD_GPMI_RDY1__SSP1_CMD 0x0151
304
+
MX28_PAD_GPMI_RDY2__CAN0_TX 0x0161
305
+
MX28_PAD_GPMI_RDY3__CAN0_RX 0x0171
306
+
MX28_PAD_GPMI_RDN__SSP3_SCK 0x0181
307
+
MX28_PAD_GPMI_WRN__SSP1_SCK 0x0191
308
+
MX28_PAD_GPMI_ALE__SSP3_D1 0x01a1
309
+
MX28_PAD_GPMI_CLE__SSP3_D2 0x01b1
310
+
MX28_PAD_GPMI_RESETN__SSP3_CMD 0x01c1
311
+
MX28_PAD_LCD_D03__ETM_DA8 0x1031
312
+
MX28_PAD_LCD_D04__ETM_DA9 0x1041
313
+
MX28_PAD_LCD_D08__ETM_DA3 0x1081
314
+
MX28_PAD_LCD_D09__ETM_DA4 0x1091
315
+
MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT 0x1141
316
+
MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN 0x1151
317
+
MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT 0x1161
318
+
MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN 0x1171
319
+
MX28_PAD_LCD_RD_E__LCD_VSYNC 0x1181
320
+
MX28_PAD_LCD_WR_RWN__LCD_HSYNC 0x1191
321
+
MX28_PAD_LCD_RS__LCD_DOTCLK 0x11a1
322
+
MX28_PAD_LCD_CS__LCD_ENABLE 0x11b1
323
+
MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 0x11c1
324
+
MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 0x11d1
325
+
MX28_PAD_LCD_DOTCLK__SAIF1_MCLK 0x11e1
326
+
MX28_PAD_SSP0_DATA4__SSP2_D0 0x2041
327
+
MX28_PAD_SSP0_DATA5__SSP2_D3 0x2051
328
+
MX28_PAD_SSP0_DATA6__SSP2_CMD 0x2061
329
+
MX28_PAD_SSP0_DATA7__SSP2_SCK 0x2071
330
+
MX28_PAD_SSP1_SCK__SSP2_D1 0x20c1
331
+
MX28_PAD_SSP1_CMD__SSP2_D2 0x20d1
332
+
MX28_PAD_SSP1_DATA0__SSP2_D6 0x20e1
333
+
MX28_PAD_SSP1_DATA3__SSP2_D7 0x20f1
334
+
MX28_PAD_SSP2_SCK__AUART2_RX 0x2101
335
+
MX28_PAD_SSP2_MOSI__AUART2_TX 0x2111
336
+
MX28_PAD_SSP2_MISO__AUART3_RX 0x2121
337
+
MX28_PAD_SSP2_SS0__AUART3_TX 0x2131
338
+
MX28_PAD_SSP2_SS1__SSP2_D1 0x2141
339
+
MX28_PAD_SSP2_SS2__SSP2_D2 0x2151
340
+
MX28_PAD_SSP3_SCK__AUART4_TX 0x2181
341
+
MX28_PAD_SSP3_MOSI__AUART4_RX 0x2191
342
+
MX28_PAD_SSP3_MISO__AUART4_RTS 0x21a1
343
+
MX28_PAD_SSP3_SS0__AUART4_CTS 0x21b1
344
+
MX28_PAD_AUART0_RX__I2C0_SCL 0x3001
345
+
MX28_PAD_AUART0_TX__I2C0_SDA 0x3011
346
+
MX28_PAD_AUART0_CTS__AUART4_RX 0x3021
347
+
MX28_PAD_AUART0_RTS__AUART4_TX 0x3031
348
+
MX28_PAD_AUART1_RX__SSP2_CARD_DETECT 0x3041
349
+
MX28_PAD_AUART1_TX__SSP3_CARD_DETECT 0x3051
350
+
MX28_PAD_AUART1_CTS__USB0_OVERCURRENT 0x3061
351
+
MX28_PAD_AUART1_RTS__USB0_ID 0x3071
352
+
MX28_PAD_AUART2_RX__SSP3_D1 0x3081
353
+
MX28_PAD_AUART2_TX__SSP3_D2 0x3091
354
+
MX28_PAD_AUART2_CTS__I2C1_SCL 0x30a1
355
+
MX28_PAD_AUART2_RTS__I2C1_SDA 0x30b1
356
+
MX28_PAD_AUART3_RX__CAN0_TX 0x30c1
357
+
MX28_PAD_AUART3_TX__CAN0_RX 0x30d1
358
+
MX28_PAD_AUART3_CTS__CAN1_TX 0x30e1
359
+
MX28_PAD_AUART3_RTS__CAN1_RX 0x30f1
360
+
MX28_PAD_PWM0__I2C1_SCL 0x3101
361
+
MX28_PAD_PWM1__I2C1_SDA 0x3111
362
+
MX28_PAD_PWM2__USB0_ID 0x3121
363
+
MX28_PAD_SAIF0_MCLK__PWM_3 0x3141
364
+
MX28_PAD_SAIF0_LRCLK__PWM_4 0x3151
365
+
MX28_PAD_SAIF0_BITCLK__PWM_5 0x3161
366
+
MX28_PAD_SAIF0_SDATA0__PWM_6 0x3171
367
+
MX28_PAD_I2C0_SCL__TIMROT_ROTARYA 0x3181
368
+
MX28_PAD_I2C0_SDA__TIMROT_ROTARYB 0x3191
369
+
MX28_PAD_SAIF1_SDATA0__PWM_7 0x31a1
370
+
MX28_PAD_LCD_RESET__LCD_VSYNC 0x31e1
371
+
MX28_PAD_ENET0_MDC__GPMI_CE4N 0x4001
372
+
MX28_PAD_ENET0_MDIO__GPMI_CE5N 0x4011
373
+
MX28_PAD_ENET0_RX_EN__GPMI_CE6N 0x4021
374
+
MX28_PAD_ENET0_RXD0__GPMI_CE7N 0x4031
375
+
MX28_PAD_ENET0_RXD1__GPMI_READY4 0x4041
376
+
MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER 0x4051
377
+
MX28_PAD_ENET0_TX_EN__GPMI_READY5 0x4061
378
+
MX28_PAD_ENET0_TXD0__GPMI_READY6 0x4071
379
+
MX28_PAD_ENET0_TXD1__GPMI_READY7 0x4081
380
+
MX28_PAD_ENET0_RXD2__ENET1_RXD0 0x4091
381
+
MX28_PAD_ENET0_RXD3__ENET1_RXD1 0x40a1
382
+
MX28_PAD_ENET0_TXD2__ENET1_TXD0 0x40b1
383
+
MX28_PAD_ENET0_TXD3__ENET1_TXD1 0x40c1
384
+
MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER 0x40d1
385
+
MX28_PAD_ENET0_COL__ENET1_TX_EN 0x40e1
386
+
MX28_PAD_ENET0_CRS__ENET1_RX_EN 0x40f1
387
+
MX28_PAD_GPMI_CE2N__ENET0_RX_ER 0x0122
388
+
MX28_PAD_GPMI_CE3N__SAIF1_MCLK 0x0132
389
+
MX28_PAD_GPMI_RDY0__USB0_ID 0x0142
390
+
MX28_PAD_GPMI_RDY2__ENET0_TX_ER 0x0162
391
+
MX28_PAD_GPMI_RDY3__HSADC_TRIGGER 0x0172
392
+
MX28_PAD_GPMI_ALE__SSP3_D4 0x01a2
393
+
MX28_PAD_GPMI_CLE__SSP3_D5 0x01b2
394
+
MX28_PAD_LCD_D00__ETM_DA0 0x1002
395
+
MX28_PAD_LCD_D01__ETM_DA1 0x1012
396
+
MX28_PAD_LCD_D02__ETM_DA2 0x1022
397
+
MX28_PAD_LCD_D03__ETM_DA3 0x1032
398
+
MX28_PAD_LCD_D04__ETM_DA4 0x1042
399
+
MX28_PAD_LCD_D05__ETM_DA5 0x1052
400
+
MX28_PAD_LCD_D06__ETM_DA6 0x1062
401
+
MX28_PAD_LCD_D07__ETM_DA7 0x1072
402
+
MX28_PAD_LCD_D08__ETM_DA8 0x1082
403
+
MX28_PAD_LCD_D09__ETM_DA9 0x1092
404
+
MX28_PAD_LCD_D10__ETM_DA10 0x10a2
405
+
MX28_PAD_LCD_D11__ETM_DA11 0x10b2
406
+
MX28_PAD_LCD_D12__ETM_DA12 0x10c2
407
+
MX28_PAD_LCD_D13__ETM_DA13 0x10d2
408
+
MX28_PAD_LCD_D14__ETM_DA14 0x10e2
409
+
MX28_PAD_LCD_D15__ETM_DA15 0x10f2
410
+
MX28_PAD_LCD_D16__ETM_DA7 0x1102
411
+
MX28_PAD_LCD_D17__ETM_DA6 0x1112
412
+
MX28_PAD_LCD_D18__ETM_DA5 0x1122
413
+
MX28_PAD_LCD_D19__ETM_DA4 0x1132
414
+
MX28_PAD_LCD_D20__ETM_DA3 0x1142
415
+
MX28_PAD_LCD_D21__ETM_DA2 0x1152
416
+
MX28_PAD_LCD_D22__ETM_DA1 0x1162
417
+
MX28_PAD_LCD_D23__ETM_DA0 0x1172
418
+
MX28_PAD_LCD_RD_E__ETM_TCTL 0x1182
419
+
MX28_PAD_LCD_WR_RWN__ETM_TCLK 0x1192
420
+
MX28_PAD_LCD_HSYNC__ETM_TCTL 0x11d2
421
+
MX28_PAD_LCD_DOTCLK__ETM_TCLK 0x11e2
422
+
MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT 0x20c2
423
+
MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN 0x20d2
424
+
MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT 0x20e2
425
+
MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN 0x20f2
426
+
MX28_PAD_SSP2_SCK__SAIF0_SDATA1 0x2102
427
+
MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 0x2112
428
+
MX28_PAD_SSP2_MISO__SAIF1_SDATA1 0x2122
429
+
MX28_PAD_SSP2_SS0__SAIF1_SDATA2 0x2132
430
+
MX28_PAD_SSP2_SS1__USB1_OVERCURRENT 0x2142
431
+
MX28_PAD_SSP2_SS2__USB0_OVERCURRENT 0x2152
432
+
MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT 0x2182
433
+
MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN 0x2192
434
+
MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT 0x21a2
435
+
MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN 0x21b2
436
+
MX28_PAD_AUART0_RX__DUART_CTS 0x3002
437
+
MX28_PAD_AUART0_TX__DUART_RTS 0x3012
438
+
MX28_PAD_AUART0_CTS__DUART_RX 0x3022
439
+
MX28_PAD_AUART0_RTS__DUART_TX 0x3032
440
+
MX28_PAD_AUART1_RX__PWM_0 0x3042
441
+
MX28_PAD_AUART1_TX__PWM_1 0x3052
442
+
MX28_PAD_AUART1_CTS__TIMROT_ROTARYA 0x3062
443
+
MX28_PAD_AUART1_RTS__TIMROT_ROTARYB 0x3072
444
+
MX28_PAD_AUART2_RX__SSP3_D4 0x3082
445
+
MX28_PAD_AUART2_TX__SSP3_D5 0x3092
446
+
MX28_PAD_AUART2_CTS__SAIF1_BITCLK 0x30a2
447
+
MX28_PAD_AUART2_RTS__SAIF1_LRCLK 0x30b2
448
+
MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT 0x30c2
449
+
MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN 0x30d2
450
+
MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT 0x30e2
451
+
MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN 0x30f2
452
+
MX28_PAD_PWM0__DUART_RX 0x3102
453
+
MX28_PAD_PWM1__DUART_TX 0x3112
454
+
MX28_PAD_PWM2__USB1_OVERCURRENT 0x3122
455
+
MX28_PAD_SAIF0_MCLK__AUART4_CTS 0x3142
456
+
MX28_PAD_SAIF0_LRCLK__AUART4_RTS 0x3152
457
+
MX28_PAD_SAIF0_BITCLK__AUART4_RX 0x3162
458
+
MX28_PAD_SAIF0_SDATA0__AUART4_TX 0x3172
459
+
MX28_PAD_I2C0_SCL__DUART_RX 0x3182
460
+
MX28_PAD_I2C0_SDA__DUART_TX 0x3192
461
+
MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 0x31a2
462
+
MX28_PAD_SPDIF__ENET1_RX_ER 0x31b2
463
+
MX28_PAD_ENET0_MDC__SAIF0_SDATA1 0x4002
464
+
MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 0x4012
465
+
MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 0x4022
466
+
MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 0x4032
467
+
MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT 0x4052
468
+
MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT 0x4092
469
+
MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN 0x40a2
470
+
MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT 0x40b2
471
+
MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN 0x40c2
472
+
MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN 0x40d2
473
+
MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT 0x40e2
474
+
MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN 0x40f2
475
+
MX28_PAD_GPMI_D00__GPIO_0_0 0x0003
476
+
MX28_PAD_GPMI_D01__GPIO_0_1 0x0013
477
+
MX28_PAD_GPMI_D02__GPIO_0_2 0x0023
478
+
MX28_PAD_GPMI_D03__GPIO_0_3 0x0033
479
+
MX28_PAD_GPMI_D04__GPIO_0_4 0x0043
480
+
MX28_PAD_GPMI_D05__GPIO_0_5 0x0053
481
+
MX28_PAD_GPMI_D06__GPIO_0_6 0x0063
482
+
MX28_PAD_GPMI_D07__GPIO_0_7 0x0073
483
+
MX28_PAD_GPMI_CE0N__GPIO_0_16 0x0103
484
+
MX28_PAD_GPMI_CE1N__GPIO_0_17 0x0113
485
+
MX28_PAD_GPMI_CE2N__GPIO_0_18 0x0123
486
+
MX28_PAD_GPMI_CE3N__GPIO_0_19 0x0133
487
+
MX28_PAD_GPMI_RDY0__GPIO_0_20 0x0143
488
+
MX28_PAD_GPMI_RDY1__GPIO_0_21 0x0153
489
+
MX28_PAD_GPMI_RDY2__GPIO_0_22 0x0163
490
+
MX28_PAD_GPMI_RDY3__GPIO_0_23 0x0173
491
+
MX28_PAD_GPMI_RDN__GPIO_0_24 0x0183
492
+
MX28_PAD_GPMI_WRN__GPIO_0_25 0x0193
493
+
MX28_PAD_GPMI_ALE__GPIO_0_26 0x01a3
494
+
MX28_PAD_GPMI_CLE__GPIO_0_27 0x01b3
495
+
MX28_PAD_GPMI_RESETN__GPIO_0_28 0x01c3
496
+
MX28_PAD_LCD_D00__GPIO_1_0 0x1003
497
+
MX28_PAD_LCD_D01__GPIO_1_1 0x1013
498
+
MX28_PAD_LCD_D02__GPIO_1_2 0x1023
499
+
MX28_PAD_LCD_D03__GPIO_1_3 0x1033
500
+
MX28_PAD_LCD_D04__GPIO_1_4 0x1043
501
+
MX28_PAD_LCD_D05__GPIO_1_5 0x1053
502
+
MX28_PAD_LCD_D06__GPIO_1_6 0x1063
503
+
MX28_PAD_LCD_D07__GPIO_1_7 0x1073
504
+
MX28_PAD_LCD_D08__GPIO_1_8 0x1083
505
+
MX28_PAD_LCD_D09__GPIO_1_9 0x1093
506
+
MX28_PAD_LCD_D10__GPIO_1_10 0x10a3
507
+
MX28_PAD_LCD_D11__GPIO_1_11 0x10b3
508
+
MX28_PAD_LCD_D12__GPIO_1_12 0x10c3
509
+
MX28_PAD_LCD_D13__GPIO_1_13 0x10d3
510
+
MX28_PAD_LCD_D14__GPIO_1_14 0x10e3
511
+
MX28_PAD_LCD_D15__GPIO_1_15 0x10f3
512
+
MX28_PAD_LCD_D16__GPIO_1_16 0x1103
513
+
MX28_PAD_LCD_D17__GPIO_1_17 0x1113
514
+
MX28_PAD_LCD_D18__GPIO_1_18 0x1123
515
+
MX28_PAD_LCD_D19__GPIO_1_19 0x1133
516
+
MX28_PAD_LCD_D20__GPIO_1_20 0x1143
517
+
MX28_PAD_LCD_D21__GPIO_1_21 0x1153
518
+
MX28_PAD_LCD_D22__GPIO_1_22 0x1163
519
+
MX28_PAD_LCD_D23__GPIO_1_23 0x1173
520
+
MX28_PAD_LCD_RD_E__GPIO_1_24 0x1183
521
+
MX28_PAD_LCD_WR_RWN__GPIO_1_25 0x1193
522
+
MX28_PAD_LCD_RS__GPIO_1_26 0x11a3
523
+
MX28_PAD_LCD_CS__GPIO_1_27 0x11b3
524
+
MX28_PAD_LCD_VSYNC__GPIO_1_28 0x11c3
525
+
MX28_PAD_LCD_HSYNC__GPIO_1_29 0x11d3
526
+
MX28_PAD_LCD_DOTCLK__GPIO_1_30 0x11e3
527
+
MX28_PAD_LCD_ENABLE__GPIO_1_31 0x11f3
528
+
MX28_PAD_SSP0_DATA0__GPIO_2_0 0x2003
529
+
MX28_PAD_SSP0_DATA1__GPIO_2_1 0x2013
530
+
MX28_PAD_SSP0_DATA2__GPIO_2_2 0x2023
531
+
MX28_PAD_SSP0_DATA3__GPIO_2_3 0x2033
532
+
MX28_PAD_SSP0_DATA4__GPIO_2_4 0x2043
533
+
MX28_PAD_SSP0_DATA5__GPIO_2_5 0x2053
534
+
MX28_PAD_SSP0_DATA6__GPIO_2_6 0x2063
535
+
MX28_PAD_SSP0_DATA7__GPIO_2_7 0x2073
536
+
MX28_PAD_SSP0_CMD__GPIO_2_8 0x2083
537
+
MX28_PAD_SSP0_DETECT__GPIO_2_9 0x2093
538
+
MX28_PAD_SSP0_SCK__GPIO_2_10 0x20a3
539
+
MX28_PAD_SSP1_SCK__GPIO_2_12 0x20c3
540
+
MX28_PAD_SSP1_CMD__GPIO_2_13 0x20d3
541
+
MX28_PAD_SSP1_DATA0__GPIO_2_14 0x20e3
542
+
MX28_PAD_SSP1_DATA3__GPIO_2_15 0x20f3
543
+
MX28_PAD_SSP2_SCK__GPIO_2_16 0x2103
544
+
MX28_PAD_SSP2_MOSI__GPIO_2_17 0x2113
545
+
MX28_PAD_SSP2_MISO__GPIO_2_18 0x2123
546
+
MX28_PAD_SSP2_SS0__GPIO_2_19 0x2133
547
+
MX28_PAD_SSP2_SS1__GPIO_2_20 0x2143
548
+
MX28_PAD_SSP2_SS2__GPIO_2_21 0x2153
549
+
MX28_PAD_SSP3_SCK__GPIO_2_24 0x2183
550
+
MX28_PAD_SSP3_MOSI__GPIO_2_25 0x2193
551
+
MX28_PAD_SSP3_MISO__GPIO_2_26 0x21a3
552
+
MX28_PAD_SSP3_SS0__GPIO_2_27 0x21b3
553
+
MX28_PAD_AUART0_RX__GPIO_3_0 0x3003
554
+
MX28_PAD_AUART0_TX__GPIO_3_1 0x3013
555
+
MX28_PAD_AUART0_CTS__GPIO_3_2 0x3023
556
+
MX28_PAD_AUART0_RTS__GPIO_3_3 0x3033
557
+
MX28_PAD_AUART1_RX__GPIO_3_4 0x3043
558
+
MX28_PAD_AUART1_TX__GPIO_3_5 0x3053
559
+
MX28_PAD_AUART1_CTS__GPIO_3_6 0x3063
560
+
MX28_PAD_AUART1_RTS__GPIO_3_7 0x3073
561
+
MX28_PAD_AUART2_RX__GPIO_3_8 0x3083
562
+
MX28_PAD_AUART2_TX__GPIO_3_9 0x3093
563
+
MX28_PAD_AUART2_CTS__GPIO_3_10 0x30a3
564
+
MX28_PAD_AUART2_RTS__GPIO_3_11 0x30b3
565
+
MX28_PAD_AUART3_RX__GPIO_3_12 0x30c3
566
+
MX28_PAD_AUART3_TX__GPIO_3_13 0x30d3
567
+
MX28_PAD_AUART3_CTS__GPIO_3_14 0x30e3
568
+
MX28_PAD_AUART3_RTS__GPIO_3_15 0x30f3
569
+
MX28_PAD_PWM0__GPIO_3_16 0x3103
570
+
MX28_PAD_PWM1__GPIO_3_17 0x3113
571
+
MX28_PAD_PWM2__GPIO_3_18 0x3123
572
+
MX28_PAD_SAIF0_MCLK__GPIO_3_20 0x3143
573
+
MX28_PAD_SAIF0_LRCLK__GPIO_3_21 0x3153
574
+
MX28_PAD_SAIF0_BITCLK__GPIO_3_22 0x3163
575
+
MX28_PAD_SAIF0_SDATA0__GPIO_3_23 0x3173
576
+
MX28_PAD_I2C0_SCL__GPIO_3_24 0x3183
577
+
MX28_PAD_I2C0_SDA__GPIO_3_25 0x3193
578
+
MX28_PAD_SAIF1_SDATA0__GPIO_3_26 0x31a3
579
+
MX28_PAD_SPDIF__GPIO_3_27 0x31b3
580
+
MX28_PAD_PWM3__GPIO_3_28 0x31c3
581
+
MX28_PAD_PWM4__GPIO_3_29 0x31d3
582
+
MX28_PAD_LCD_RESET__GPIO_3_30 0x31e3
583
+
MX28_PAD_ENET0_MDC__GPIO_4_0 0x4003
584
+
MX28_PAD_ENET0_MDIO__GPIO_4_1 0x4013
585
+
MX28_PAD_ENET0_RX_EN__GPIO_4_2 0x4023
586
+
MX28_PAD_ENET0_RXD0__GPIO_4_3 0x4033
587
+
MX28_PAD_ENET0_RXD1__GPIO_4_4 0x4043
588
+
MX28_PAD_ENET0_TX_CLK__GPIO_4_5 0x4053
589
+
MX28_PAD_ENET0_TX_EN__GPIO_4_6 0x4063
590
+
MX28_PAD_ENET0_TXD0__GPIO_4_7 0x4073
591
+
MX28_PAD_ENET0_TXD1__GPIO_4_8 0x4083
592
+
MX28_PAD_ENET0_RXD2__GPIO_4_9 0x4093
593
+
MX28_PAD_ENET0_RXD3__GPIO_4_10 0x40a3
594
+
MX28_PAD_ENET0_TXD2__GPIO_4_11 0x40b3
595
+
MX28_PAD_ENET0_TXD3__GPIO_4_12 0x40c3
596
+
MX28_PAD_ENET0_RX_CLK__GPIO_4_13 0x40d3
597
+
MX28_PAD_ENET0_COL__GPIO_4_14 0x40e3
598
+
MX28_PAD_ENET0_CRS__GPIO_4_15 0x40f3
599
+
MX28_PAD_ENET_CLK__GPIO_4_16 0x4103
600
+
MX28_PAD_JTAG_RTCK__GPIO_4_20 0x4143
601
+
602
+
Valid values for i.MX23 pinmux-id:
603
+
604
+
pinmux id
605
+
------ --
606
+
MX23_PAD_GPMI_D00__GPMI_D00 0x0000
607
+
MX23_PAD_GPMI_D01__GPMI_D01 0x0010
608
+
MX23_PAD_GPMI_D02__GPMI_D02 0x0020
609
+
MX23_PAD_GPMI_D03__GPMI_D03 0x0030
610
+
MX23_PAD_GPMI_D04__GPMI_D04 0x0040
611
+
MX23_PAD_GPMI_D05__GPMI_D05 0x0050
612
+
MX23_PAD_GPMI_D06__GPMI_D06 0x0060
613
+
MX23_PAD_GPMI_D07__GPMI_D07 0x0070
614
+
MX23_PAD_GPMI_D08__GPMI_D08 0x0080
615
+
MX23_PAD_GPMI_D09__GPMI_D09 0x0090
616
+
MX23_PAD_GPMI_D10__GPMI_D10 0x00a0
617
+
MX23_PAD_GPMI_D11__GPMI_D11 0x00b0
618
+
MX23_PAD_GPMI_D12__GPMI_D12 0x00c0
619
+
MX23_PAD_GPMI_D13__GPMI_D13 0x00d0
620
+
MX23_PAD_GPMI_D14__GPMI_D14 0x00e0
621
+
MX23_PAD_GPMI_D15__GPMI_D15 0x00f0
622
+
MX23_PAD_GPMI_CLE__GPMI_CLE 0x0100
623
+
MX23_PAD_GPMI_ALE__GPMI_ALE 0x0110
624
+
MX23_PAD_GPMI_CE2N__GPMI_CE2N 0x0120
625
+
MX23_PAD_GPMI_RDY0__GPMI_RDY0 0x0130
626
+
MX23_PAD_GPMI_RDY1__GPMI_RDY1 0x0140
627
+
MX23_PAD_GPMI_RDY2__GPMI_RDY2 0x0150
628
+
MX23_PAD_GPMI_RDY3__GPMI_RDY3 0x0160
629
+
MX23_PAD_GPMI_WPN__GPMI_WPN 0x0170
630
+
MX23_PAD_GPMI_WRN__GPMI_WRN 0x0180
631
+
MX23_PAD_GPMI_RDN__GPMI_RDN 0x0190
632
+
MX23_PAD_AUART1_CTS__AUART1_CTS 0x01a0
633
+
MX23_PAD_AUART1_RTS__AUART1_RTS 0x01b0
634
+
MX23_PAD_AUART1_RX__AUART1_RX 0x01c0
635
+
MX23_PAD_AUART1_TX__AUART1_TX 0x01d0
636
+
MX23_PAD_I2C_SCL__I2C_SCL 0x01e0
637
+
MX23_PAD_I2C_SDA__I2C_SDA 0x01f0
638
+
MX23_PAD_LCD_D00__LCD_D00 0x1000
639
+
MX23_PAD_LCD_D01__LCD_D01 0x1010
640
+
MX23_PAD_LCD_D02__LCD_D02 0x1020
641
+
MX23_PAD_LCD_D03__LCD_D03 0x1030
642
+
MX23_PAD_LCD_D04__LCD_D04 0x1040
643
+
MX23_PAD_LCD_D05__LCD_D05 0x1050
644
+
MX23_PAD_LCD_D06__LCD_D06 0x1060
645
+
MX23_PAD_LCD_D07__LCD_D07 0x1070
646
+
MX23_PAD_LCD_D08__LCD_D08 0x1080
647
+
MX23_PAD_LCD_D09__LCD_D09 0x1090
648
+
MX23_PAD_LCD_D10__LCD_D10 0x10a0
649
+
MX23_PAD_LCD_D11__LCD_D11 0x10b0
650
+
MX23_PAD_LCD_D12__LCD_D12 0x10c0
651
+
MX23_PAD_LCD_D13__LCD_D13 0x10d0
652
+
MX23_PAD_LCD_D14__LCD_D14 0x10e0
653
+
MX23_PAD_LCD_D15__LCD_D15 0x10f0
654
+
MX23_PAD_LCD_D16__LCD_D16 0x1100
655
+
MX23_PAD_LCD_D17__LCD_D17 0x1110
656
+
MX23_PAD_LCD_RESET__LCD_RESET 0x1120
657
+
MX23_PAD_LCD_RS__LCD_RS 0x1130
658
+
MX23_PAD_LCD_WR__LCD_WR 0x1140
659
+
MX23_PAD_LCD_CS__LCD_CS 0x1150
660
+
MX23_PAD_LCD_DOTCK__LCD_DOTCK 0x1160
661
+
MX23_PAD_LCD_ENABLE__LCD_ENABLE 0x1170
662
+
MX23_PAD_LCD_HSYNC__LCD_HSYNC 0x1180
663
+
MX23_PAD_LCD_VSYNC__LCD_VSYNC 0x1190
664
+
MX23_PAD_PWM0__PWM0 0x11a0
665
+
MX23_PAD_PWM1__PWM1 0x11b0
666
+
MX23_PAD_PWM2__PWM2 0x11c0
667
+
MX23_PAD_PWM3__PWM3 0x11d0
668
+
MX23_PAD_PWM4__PWM4 0x11e0
669
+
MX23_PAD_SSP1_CMD__SSP1_CMD 0x2000
670
+
MX23_PAD_SSP1_DETECT__SSP1_DETECT 0x2010
671
+
MX23_PAD_SSP1_DATA0__SSP1_DATA0 0x2020
672
+
MX23_PAD_SSP1_DATA1__SSP1_DATA1 0x2030
673
+
MX23_PAD_SSP1_DATA2__SSP1_DATA2 0x2040
674
+
MX23_PAD_SSP1_DATA3__SSP1_DATA3 0x2050
675
+
MX23_PAD_SSP1_SCK__SSP1_SCK 0x2060
676
+
MX23_PAD_ROTARYA__ROTARYA 0x2070
677
+
MX23_PAD_ROTARYB__ROTARYB 0x2080
678
+
MX23_PAD_EMI_A00__EMI_A00 0x2090
679
+
MX23_PAD_EMI_A01__EMI_A01 0x20a0
680
+
MX23_PAD_EMI_A02__EMI_A02 0x20b0
681
+
MX23_PAD_EMI_A03__EMI_A03 0x20c0
682
+
MX23_PAD_EMI_A04__EMI_A04 0x20d0
683
+
MX23_PAD_EMI_A05__EMI_A05 0x20e0
684
+
MX23_PAD_EMI_A06__EMI_A06 0x20f0
685
+
MX23_PAD_EMI_A07__EMI_A07 0x2100
686
+
MX23_PAD_EMI_A08__EMI_A08 0x2110
687
+
MX23_PAD_EMI_A09__EMI_A09 0x2120
688
+
MX23_PAD_EMI_A10__EMI_A10 0x2130
689
+
MX23_PAD_EMI_A11__EMI_A11 0x2140
690
+
MX23_PAD_EMI_A12__EMI_A12 0x2150
691
+
MX23_PAD_EMI_BA0__EMI_BA0 0x2160
692
+
MX23_PAD_EMI_BA1__EMI_BA1 0x2170
693
+
MX23_PAD_EMI_CASN__EMI_CASN 0x2180
694
+
MX23_PAD_EMI_CE0N__EMI_CE0N 0x2190
695
+
MX23_PAD_EMI_CE1N__EMI_CE1N 0x21a0
696
+
MX23_PAD_GPMI_CE1N__GPMI_CE1N 0x21b0
697
+
MX23_PAD_GPMI_CE0N__GPMI_CE0N 0x21c0
698
+
MX23_PAD_EMI_CKE__EMI_CKE 0x21d0
699
+
MX23_PAD_EMI_RASN__EMI_RASN 0x21e0
700
+
MX23_PAD_EMI_WEN__EMI_WEN 0x21f0
701
+
MX23_PAD_EMI_D00__EMI_D00 0x3000
702
+
MX23_PAD_EMI_D01__EMI_D01 0x3010
703
+
MX23_PAD_EMI_D02__EMI_D02 0x3020
704
+
MX23_PAD_EMI_D03__EMI_D03 0x3030
705
+
MX23_PAD_EMI_D04__EMI_D04 0x3040
706
+
MX23_PAD_EMI_D05__EMI_D05 0x3050
707
+
MX23_PAD_EMI_D06__EMI_D06 0x3060
708
+
MX23_PAD_EMI_D07__EMI_D07 0x3070
709
+
MX23_PAD_EMI_D08__EMI_D08 0x3080
710
+
MX23_PAD_EMI_D09__EMI_D09 0x3090
711
+
MX23_PAD_EMI_D10__EMI_D10 0x30a0
712
+
MX23_PAD_EMI_D11__EMI_D11 0x30b0
713
+
MX23_PAD_EMI_D12__EMI_D12 0x30c0
714
+
MX23_PAD_EMI_D13__EMI_D13 0x30d0
715
+
MX23_PAD_EMI_D14__EMI_D14 0x30e0
716
+
MX23_PAD_EMI_D15__EMI_D15 0x30f0
717
+
MX23_PAD_EMI_DQM0__EMI_DQM0 0x3100
718
+
MX23_PAD_EMI_DQM1__EMI_DQM1 0x3110
719
+
MX23_PAD_EMI_DQS0__EMI_DQS0 0x3120
720
+
MX23_PAD_EMI_DQS1__EMI_DQS1 0x3130
721
+
MX23_PAD_EMI_CLK__EMI_CLK 0x3140
722
+
MX23_PAD_EMI_CLKN__EMI_CLKN 0x3150
723
+
MX23_PAD_GPMI_D00__LCD_D8 0x0001
724
+
MX23_PAD_GPMI_D01__LCD_D9 0x0011
725
+
MX23_PAD_GPMI_D02__LCD_D10 0x0021
726
+
MX23_PAD_GPMI_D03__LCD_D11 0x0031
727
+
MX23_PAD_GPMI_D04__LCD_D12 0x0041
728
+
MX23_PAD_GPMI_D05__LCD_D13 0x0051
729
+
MX23_PAD_GPMI_D06__LCD_D14 0x0061
730
+
MX23_PAD_GPMI_D07__LCD_D15 0x0071
731
+
MX23_PAD_GPMI_D08__LCD_D18 0x0081
732
+
MX23_PAD_GPMI_D09__LCD_D19 0x0091
733
+
MX23_PAD_GPMI_D10__LCD_D20 0x00a1
734
+
MX23_PAD_GPMI_D11__LCD_D21 0x00b1
735
+
MX23_PAD_GPMI_D12__LCD_D22 0x00c1
736
+
MX23_PAD_GPMI_D13__LCD_D23 0x00d1
737
+
MX23_PAD_GPMI_D14__AUART2_RX 0x00e1
738
+
MX23_PAD_GPMI_D15__AUART2_TX 0x00f1
739
+
MX23_PAD_GPMI_CLE__LCD_D16 0x0101
740
+
MX23_PAD_GPMI_ALE__LCD_D17 0x0111
741
+
MX23_PAD_GPMI_CE2N__ATA_A2 0x0121
742
+
MX23_PAD_AUART1_RTS__IR_CLK 0x01b1
743
+
MX23_PAD_AUART1_RX__IR_RX 0x01c1
744
+
MX23_PAD_AUART1_TX__IR_TX 0x01d1
745
+
MX23_PAD_I2C_SCL__GPMI_RDY2 0x01e1
746
+
MX23_PAD_I2C_SDA__GPMI_CE2N 0x01f1
747
+
MX23_PAD_LCD_D00__ETM_DA8 0x1001
748
+
MX23_PAD_LCD_D01__ETM_DA9 0x1011
749
+
MX23_PAD_LCD_D02__ETM_DA10 0x1021
750
+
MX23_PAD_LCD_D03__ETM_DA11 0x1031
751
+
MX23_PAD_LCD_D04__ETM_DA12 0x1041
752
+
MX23_PAD_LCD_D05__ETM_DA13 0x1051
753
+
MX23_PAD_LCD_D06__ETM_DA14 0x1061
754
+
MX23_PAD_LCD_D07__ETM_DA15 0x1071
755
+
MX23_PAD_LCD_D08__ETM_DA0 0x1081
756
+
MX23_PAD_LCD_D09__ETM_DA1 0x1091
757
+
MX23_PAD_LCD_D10__ETM_DA2 0x10a1
758
+
MX23_PAD_LCD_D11__ETM_DA3 0x10b1
759
+
MX23_PAD_LCD_D12__ETM_DA4 0x10c1
760
+
MX23_PAD_LCD_D13__ETM_DA5 0x10d1
761
+
MX23_PAD_LCD_D14__ETM_DA6 0x10e1
762
+
MX23_PAD_LCD_D15__ETM_DA7 0x10f1
763
+
MX23_PAD_LCD_RESET__ETM_TCTL 0x1121
764
+
MX23_PAD_LCD_RS__ETM_TCLK 0x1131
765
+
MX23_PAD_LCD_DOTCK__GPMI_RDY3 0x1161
766
+
MX23_PAD_LCD_ENABLE__I2C_SCL 0x1171
767
+
MX23_PAD_LCD_HSYNC__I2C_SDA 0x1181
768
+
MX23_PAD_LCD_VSYNC__LCD_BUSY 0x1191
769
+
MX23_PAD_PWM0__ROTARYA 0x11a1
770
+
MX23_PAD_PWM1__ROTARYB 0x11b1
771
+
MX23_PAD_PWM2__GPMI_RDY3 0x11c1
772
+
MX23_PAD_PWM3__ETM_TCTL 0x11d1
773
+
MX23_PAD_PWM4__ETM_TCLK 0x11e1
774
+
MX23_PAD_SSP1_DETECT__GPMI_CE3N 0x2011
775
+
MX23_PAD_SSP1_DATA1__I2C_SCL 0x2031
776
+
MX23_PAD_SSP1_DATA2__I2C_SDA 0x2041
777
+
MX23_PAD_ROTARYA__AUART2_RTS 0x2071
778
+
MX23_PAD_ROTARYB__AUART2_CTS 0x2081
779
+
MX23_PAD_GPMI_D00__SSP2_DATA0 0x0002
780
+
MX23_PAD_GPMI_D01__SSP2_DATA1 0x0012
781
+
MX23_PAD_GPMI_D02__SSP2_DATA2 0x0022
782
+
MX23_PAD_GPMI_D03__SSP2_DATA3 0x0032
783
+
MX23_PAD_GPMI_D04__SSP2_DATA4 0x0042
784
+
MX23_PAD_GPMI_D05__SSP2_DATA5 0x0052
785
+
MX23_PAD_GPMI_D06__SSP2_DATA6 0x0062
786
+
MX23_PAD_GPMI_D07__SSP2_DATA7 0x0072
787
+
MX23_PAD_GPMI_D08__SSP1_DATA4 0x0082
788
+
MX23_PAD_GPMI_D09__SSP1_DATA5 0x0092
789
+
MX23_PAD_GPMI_D10__SSP1_DATA6 0x00a2
790
+
MX23_PAD_GPMI_D11__SSP1_DATA7 0x00b2
791
+
MX23_PAD_GPMI_D15__GPMI_CE3N 0x00f2
792
+
MX23_PAD_GPMI_RDY0__SSP2_DETECT 0x0132
793
+
MX23_PAD_GPMI_RDY1__SSP2_CMD 0x0142
794
+
MX23_PAD_GPMI_WRN__SSP2_SCK 0x0182
795
+
MX23_PAD_AUART1_CTS__SSP1_DATA4 0x01a2
796
+
MX23_PAD_AUART1_RTS__SSP1_DATA5 0x01b2
797
+
MX23_PAD_AUART1_RX__SSP1_DATA6 0x01c2
798
+
MX23_PAD_AUART1_TX__SSP1_DATA7 0x01d2
799
+
MX23_PAD_I2C_SCL__AUART1_TX 0x01e2
800
+
MX23_PAD_I2C_SDA__AUART1_RX 0x01f2
801
+
MX23_PAD_LCD_D08__SAIF2_SDATA0 0x1082
802
+
MX23_PAD_LCD_D09__SAIF1_SDATA0 0x1092
803
+
MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK 0x10a2
804
+
MX23_PAD_LCD_D11__SAIF_LRCLK 0x10b2
805
+
MX23_PAD_LCD_D12__SAIF2_SDATA1 0x10c2
806
+
MX23_PAD_LCD_D13__SAIF2_SDATA2 0x10d2
807
+
MX23_PAD_LCD_D14__SAIF1_SDATA2 0x10e2
808
+
MX23_PAD_LCD_D15__SAIF1_SDATA1 0x10f2
809
+
MX23_PAD_LCD_D16__SAIF_ALT_BITCLK 0x1102
810
+
MX23_PAD_LCD_RESET__GPMI_CE3N 0x1122
811
+
MX23_PAD_PWM0__DUART_RX 0x11a2
812
+
MX23_PAD_PWM1__DUART_TX 0x11b2
813
+
MX23_PAD_PWM3__AUART1_CTS 0x11d2
814
+
MX23_PAD_PWM4__AUART1_RTS 0x11e2
815
+
MX23_PAD_SSP1_CMD__JTAG_TDO 0x2002
816
+
MX23_PAD_SSP1_DETECT__USB_OTG_ID 0x2012
817
+
MX23_PAD_SSP1_DATA0__JTAG_TDI 0x2022
818
+
MX23_PAD_SSP1_DATA1__JTAG_TCLK 0x2032
819
+
MX23_PAD_SSP1_DATA2__JTAG_RTCK 0x2042
820
+
MX23_PAD_SSP1_DATA3__JTAG_TMS 0x2052
821
+
MX23_PAD_SSP1_SCK__JTAG_TRST 0x2062
822
+
MX23_PAD_ROTARYA__SPDIF 0x2072
823
+
MX23_PAD_ROTARYB__GPMI_CE3N 0x2082
824
+
MX23_PAD_GPMI_D00__GPIO_0_0 0x0003
825
+
MX23_PAD_GPMI_D01__GPIO_0_1 0x0013
826
+
MX23_PAD_GPMI_D02__GPIO_0_2 0x0023
827
+
MX23_PAD_GPMI_D03__GPIO_0_3 0x0033
828
+
MX23_PAD_GPMI_D04__GPIO_0_4 0x0043
829
+
MX23_PAD_GPMI_D05__GPIO_0_5 0x0053
830
+
MX23_PAD_GPMI_D06__GPIO_0_6 0x0063
831
+
MX23_PAD_GPMI_D07__GPIO_0_7 0x0073
832
+
MX23_PAD_GPMI_D08__GPIO_0_8 0x0083
833
+
MX23_PAD_GPMI_D09__GPIO_0_9 0x0093
834
+
MX23_PAD_GPMI_D10__GPIO_0_10 0x00a3
835
+
MX23_PAD_GPMI_D11__GPIO_0_11 0x00b3
836
+
MX23_PAD_GPMI_D12__GPIO_0_12 0x00c3
837
+
MX23_PAD_GPMI_D13__GPIO_0_13 0x00d3
838
+
MX23_PAD_GPMI_D14__GPIO_0_14 0x00e3
839
+
MX23_PAD_GPMI_D15__GPIO_0_15 0x00f3
840
+
MX23_PAD_GPMI_CLE__GPIO_0_16 0x0103
841
+
MX23_PAD_GPMI_ALE__GPIO_0_17 0x0113
842
+
MX23_PAD_GPMI_CE2N__GPIO_0_18 0x0123
843
+
MX23_PAD_GPMI_RDY0__GPIO_0_19 0x0133
844
+
MX23_PAD_GPMI_RDY1__GPIO_0_20 0x0143
845
+
MX23_PAD_GPMI_RDY2__GPIO_0_21 0x0153
846
+
MX23_PAD_GPMI_RDY3__GPIO_0_22 0x0163
847
+
MX23_PAD_GPMI_WPN__GPIO_0_23 0x0173
848
+
MX23_PAD_GPMI_WRN__GPIO_0_24 0x0183
849
+
MX23_PAD_GPMI_RDN__GPIO_0_25 0x0193
850
+
MX23_PAD_AUART1_CTS__GPIO_0_26 0x01a3
851
+
MX23_PAD_AUART1_RTS__GPIO_0_27 0x01b3
852
+
MX23_PAD_AUART1_RX__GPIO_0_28 0x01c3
853
+
MX23_PAD_AUART1_TX__GPIO_0_29 0x01d3
854
+
MX23_PAD_I2C_SCL__GPIO_0_30 0x01e3
855
+
MX23_PAD_I2C_SDA__GPIO_0_31 0x01f3
856
+
MX23_PAD_LCD_D00__GPIO_1_0 0x1003
857
+
MX23_PAD_LCD_D01__GPIO_1_1 0x1013
858
+
MX23_PAD_LCD_D02__GPIO_1_2 0x1023
859
+
MX23_PAD_LCD_D03__GPIO_1_3 0x1033
860
+
MX23_PAD_LCD_D04__GPIO_1_4 0x1043
861
+
MX23_PAD_LCD_D05__GPIO_1_5 0x1053
862
+
MX23_PAD_LCD_D06__GPIO_1_6 0x1063
863
+
MX23_PAD_LCD_D07__GPIO_1_7 0x1073
864
+
MX23_PAD_LCD_D08__GPIO_1_8 0x1083
865
+
MX23_PAD_LCD_D09__GPIO_1_9 0x1093
866
+
MX23_PAD_LCD_D10__GPIO_1_10 0x10a3
867
+
MX23_PAD_LCD_D11__GPIO_1_11 0x10b3
868
+
MX23_PAD_LCD_D12__GPIO_1_12 0x10c3
869
+
MX23_PAD_LCD_D13__GPIO_1_13 0x10d3
870
+
MX23_PAD_LCD_D14__GPIO_1_14 0x10e3
871
+
MX23_PAD_LCD_D15__GPIO_1_15 0x10f3
872
+
MX23_PAD_LCD_D16__GPIO_1_16 0x1103
873
+
MX23_PAD_LCD_D17__GPIO_1_17 0x1113
874
+
MX23_PAD_LCD_RESET__GPIO_1_18 0x1123
875
+
MX23_PAD_LCD_RS__GPIO_1_19 0x1133
876
+
MX23_PAD_LCD_WR__GPIO_1_20 0x1143
877
+
MX23_PAD_LCD_CS__GPIO_1_21 0x1153
878
+
MX23_PAD_LCD_DOTCK__GPIO_1_22 0x1163
879
+
MX23_PAD_LCD_ENABLE__GPIO_1_23 0x1173
880
+
MX23_PAD_LCD_HSYNC__GPIO_1_24 0x1183
881
+
MX23_PAD_LCD_VSYNC__GPIO_1_25 0x1193
882
+
MX23_PAD_PWM0__GPIO_1_26 0x11a3
883
+
MX23_PAD_PWM1__GPIO_1_27 0x11b3
884
+
MX23_PAD_PWM2__GPIO_1_28 0x11c3
885
+
MX23_PAD_PWM3__GPIO_1_29 0x11d3
886
+
MX23_PAD_PWM4__GPIO_1_30 0x11e3
887
+
MX23_PAD_SSP1_CMD__GPIO_2_0 0x2003
888
+
MX23_PAD_SSP1_DETECT__GPIO_2_1 0x2013
889
+
MX23_PAD_SSP1_DATA0__GPIO_2_2 0x2023
890
+
MX23_PAD_SSP1_DATA1__GPIO_2_3 0x2033
891
+
MX23_PAD_SSP1_DATA2__GPIO_2_4 0x2043
892
+
MX23_PAD_SSP1_DATA3__GPIO_2_5 0x2053
893
+
MX23_PAD_SSP1_SCK__GPIO_2_6 0x2063
894
+
MX23_PAD_ROTARYA__GPIO_2_7 0x2073
895
+
MX23_PAD_ROTARYB__GPIO_2_8 0x2083
896
+
MX23_PAD_EMI_A00__GPIO_2_9 0x2093
897
+
MX23_PAD_EMI_A01__GPIO_2_10 0x20a3
898
+
MX23_PAD_EMI_A02__GPIO_2_11 0x20b3
899
+
MX23_PAD_EMI_A03__GPIO_2_12 0x20c3
900
+
MX23_PAD_EMI_A04__GPIO_2_13 0x20d3
901
+
MX23_PAD_EMI_A05__GPIO_2_14 0x20e3
902
+
MX23_PAD_EMI_A06__GPIO_2_15 0x20f3
903
+
MX23_PAD_EMI_A07__GPIO_2_16 0x2103
904
+
MX23_PAD_EMI_A08__GPIO_2_17 0x2113
905
+
MX23_PAD_EMI_A09__GPIO_2_18 0x2123
906
+
MX23_PAD_EMI_A10__GPIO_2_19 0x2133
907
+
MX23_PAD_EMI_A11__GPIO_2_20 0x2143
908
+
MX23_PAD_EMI_A12__GPIO_2_21 0x2153
909
+
MX23_PAD_EMI_BA0__GPIO_2_22 0x2163
910
+
MX23_PAD_EMI_BA1__GPIO_2_23 0x2173
911
+
MX23_PAD_EMI_CASN__GPIO_2_24 0x2183
912
+
MX23_PAD_EMI_CE0N__GPIO_2_25 0x2193
913
+
MX23_PAD_EMI_CE1N__GPIO_2_26 0x21a3
914
+
MX23_PAD_GPMI_CE1N__GPIO_2_27 0x21b3
915
+
MX23_PAD_GPMI_CE0N__GPIO_2_28 0x21c3
916
+
MX23_PAD_EMI_CKE__GPIO_2_29 0x21d3
917
+
MX23_PAD_EMI_RASN__GPIO_2_30 0x21e3
918
+
MX23_PAD_EMI_WEN__GPIO_2_31 0x21f3
+4
Documentation/driver-model/devres.txt
+4
Documentation/driver-model/devres.txt
+132
-10
drivers/clk/clkdev.c
+132
-10
drivers/clk/clkdev.c
···
35
35
static struct clk_lookup *clk_find(const char *dev_id, const char *con_id)
36
36
{
37
37
struct clk_lookup *p, *cl = NULL;
38
-
int match, best = 0;
38
+
int match, best_found = 0, best_possible = 0;
39
+
40
+
if (dev_id)
41
+
best_possible += 2;
42
+
if (con_id)
43
+
best_possible += 1;
39
44
40
45
list_for_each_entry(p, &clocks, node) {
41
46
match = 0;
···
55
50
match += 1;
56
51
}
57
52
58
-
if (match > best) {
53
+
if (match > best_found) {
59
54
cl = p;
60
-
if (match != 3)
61
-
best = match;
55
+
if (match != best_possible)
56
+
best_found = match;
62
57
else
63
58
break;
64
59
}
···
94
89
}
95
90
EXPORT_SYMBOL(clk_put);
96
91
92
+
static void devm_clk_release(struct device *dev, void *res)
93
+
{
94
+
clk_put(*(struct clk **)res);
95
+
}
96
+
97
+
struct clk *devm_clk_get(struct device *dev, const char *id)
98
+
{
99
+
struct clk **ptr, *clk;
100
+
101
+
ptr = devres_alloc(devm_clk_release, sizeof(*ptr), GFP_KERNEL);
102
+
if (!ptr)
103
+
return ERR_PTR(-ENOMEM);
104
+
105
+
clk = clk_get(dev, id);
106
+
if (!IS_ERR(clk)) {
107
+
*ptr = clk;
108
+
devres_add(dev, ptr);
109
+
} else {
110
+
devres_free(ptr);
111
+
}
112
+
113
+
return clk;
114
+
}
115
+
EXPORT_SYMBOL(devm_clk_get);
116
+
117
+
static int devm_clk_match(struct device *dev, void *res, void *data)
118
+
{
119
+
struct clk **c = res;
120
+
if (!c || !*c) {
121
+
WARN_ON(!c || !*c);
122
+
return 0;
123
+
}
124
+
return *c == data;
125
+
}
126
+
127
+
void devm_clk_put(struct device *dev, struct clk *clk)
128
+
{
129
+
int ret;
130
+
131
+
ret = devres_destroy(dev, devm_clk_release, devm_clk_match, clk);
132
+
133
+
WARN_ON(ret);
134
+
}
135
+
EXPORT_SYMBOL(devm_clk_put);
136
+
97
137
void clkdev_add(struct clk_lookup *cl)
98
138
{
99
139
mutex_lock(&clocks_mutex);
···
166
116
char con_id[MAX_CON_ID];
167
117
};
168
118
169
-
struct clk_lookup * __init_refok
170
-
clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...)
119
+
static struct clk_lookup * __init_refok
120
+
vclkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt,
121
+
va_list ap)
171
122
{
172
123
struct clk_lookup_alloc *cla;
173
124
···
183
132
}
184
133
185
134
if (dev_fmt) {
186
-
va_list ap;
187
-
188
-
va_start(ap, dev_fmt);
189
135
vscnprintf(cla->dev_id, sizeof(cla->dev_id), dev_fmt, ap);
190
136
cla->cl.dev_id = cla->dev_id;
191
-
va_end(ap);
192
137
}
193
138
194
139
return &cla->cl;
140
+
}
141
+
142
+
struct clk_lookup * __init_refok
143
+
clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...)
144
+
{
145
+
struct clk_lookup *cl;
146
+
va_list ap;
147
+
148
+
va_start(ap, dev_fmt);
149
+
cl = vclkdev_alloc(clk, con_id, dev_fmt, ap);
150
+
va_end(ap);
151
+
152
+
return cl;
195
153
}
196
154
EXPORT_SYMBOL(clkdev_alloc);
197
155
···
233
173
kfree(cl);
234
174
}
235
175
EXPORT_SYMBOL(clkdev_drop);
176
+
177
+
/**
178
+
* clk_register_clkdev - register one clock lookup for a struct clk
179
+
* @clk: struct clk to associate with all clk_lookups
180
+
* @con_id: connection ID string on device
181
+
* @dev_id: format string describing device name
182
+
*
183
+
* con_id or dev_id may be NULL as a wildcard, just as in the rest of
184
+
* clkdev.
185
+
*
186
+
* To make things easier for mass registration, we detect error clks
187
+
* from a previous clk_register() call, and return the error code for
188
+
* those. This is to permit this function to be called immediately
189
+
* after clk_register().
190
+
*/
191
+
int clk_register_clkdev(struct clk *clk, const char *con_id,
192
+
const char *dev_fmt, ...)
193
+
{
194
+
struct clk_lookup *cl;
195
+
va_list ap;
196
+
197
+
if (IS_ERR(clk))
198
+
return PTR_ERR(clk);
199
+
200
+
va_start(ap, dev_fmt);
201
+
cl = vclkdev_alloc(clk, con_id, dev_fmt, ap);
202
+
va_end(ap);
203
+
204
+
if (!cl)
205
+
return -ENOMEM;
206
+
207
+
clkdev_add(cl);
208
+
209
+
return 0;
210
+
}
211
+
212
+
/**
213
+
* clk_register_clkdevs - register a set of clk_lookup for a struct clk
214
+
* @clk: struct clk to associate with all clk_lookups
215
+
* @cl: array of clk_lookup structures with con_id and dev_id pre-initialized
216
+
* @num: number of clk_lookup structures to register
217
+
*
218
+
* To make things easier for mass registration, we detect error clks
219
+
* from a previous clk_register() call, and return the error code for
220
+
* those. This is to permit this function to be called immediately
221
+
* after clk_register().
222
+
*/
223
+
int clk_register_clkdevs(struct clk *clk, struct clk_lookup *cl, size_t num)
224
+
{
225
+
unsigned i;
226
+
227
+
if (IS_ERR(clk))
228
+
return PTR_ERR(clk);
229
+
230
+
for (i = 0; i < num; i++, cl++) {
231
+
cl->clk = clk;
232
+
clkdev_add(cl);
233
+
}
234
+
235
+
return 0;
236
+
}
237
+
EXPORT_SYMBOL(clk_register_clkdevs);
+28
drivers/pinctrl/Kconfig
+28
drivers/pinctrl/Kconfig
···
26
26
help
27
27
Say Y here to add some extra checks and diagnostics to PINCTRL calls.
28
28
29
+
config PINCTRL_IMX
30
+
bool
31
+
select PINMUX
32
+
select PINCONF
33
+
34
+
config PINCTRL_IMX6Q
35
+
bool "IMX6Q pinctrl driver"
36
+
depends on OF
37
+
depends on SOC_IMX6Q
38
+
select PINCTRL_IMX
39
+
help
40
+
Say Y here to enable the imx6q pinctrl driver
41
+
29
42
config PINCTRL_PXA3xx
30
43
bool
31
44
select PINMUX
···
48
35
depends on ARCH_MMP
49
36
select PINCTRL_PXA3xx
50
37
select PINCONF
38
+
39
+
config PINCTRL_MXS
40
+
bool
41
+
42
+
config PINCTRL_IMX23
43
+
bool
44
+
select PINMUX
45
+
select PINCONF
46
+
select PINCTRL_MXS
47
+
48
+
config PINCTRL_IMX28
49
+
bool
50
+
select PINMUX
51
+
select PINCONF
52
+
select PINCTRL_MXS
51
53
52
54
config PINCTRL_PXA168
53
55
bool "PXA168 pin controller driver"
+5
drivers/pinctrl/Makefile
+5
drivers/pinctrl/Makefile
···
9
9
obj-$(CONFIG_PINCTRL) += devicetree.o
10
10
endif
11
11
obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o
12
+
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
13
+
obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
12
14
obj-$(CONFIG_PINCTRL_PXA3xx) += pinctrl-pxa3xx.o
13
15
obj-$(CONFIG_PINCTRL_MMP2) += pinctrl-mmp2.o
16
+
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
17
+
obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
18
+
obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
14
19
obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o
15
20
obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o
16
21
obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o
+47
-22
drivers/pinctrl/core.c
+47
-22
drivers/pinctrl/core.c
···
43
43
unsigned num_maps;
44
44
};
45
45
46
+
static bool pinctrl_dummy_state;
47
+
46
48
/* Mutex taken by all entry points */
47
49
DEFINE_MUTEX(pinctrl_mutex);
48
50
···
62
60
for (_i_ = 0, _map_ = &_maps_node_->maps[_i_]; \
63
61
_i_ < _maps_node_->num_maps; \
64
62
i++, _map_ = &_maps_node_->maps[_i_])
63
+
64
+
/**
65
+
* pinctrl_provide_dummies() - indicate if pinctrl provides dummy state support
66
+
*
67
+
* Usually this function is called by platforms without pinctrl driver support
68
+
* but run with some shared drivers using pinctrl APIs.
69
+
* After calling this function, the pinctrl core will return successfully
70
+
* with creating a dummy state for the driver to keep going smoothly.
71
+
*/
72
+
void pinctrl_provide_dummies(void)
73
+
{
74
+
pinctrl_dummy_state = true;
75
+
}
65
76
66
77
const char *pinctrl_dev_get_name(struct pinctrl_dev *pctldev)
67
78
{
···
291
276
*
292
277
* Find the pin controller handling a certain GPIO pin from the pinspace of
293
278
* the GPIO subsystem, return the device and the matching GPIO range. Returns
294
-
* negative if the GPIO range could not be found in any device.
279
+
* -EPROBE_DEFER if the GPIO range could not be found in any device since it
280
+
* may still have not been registered.
295
281
*/
296
282
static int pinctrl_get_device_gpio_range(unsigned gpio,
297
283
struct pinctrl_dev **outdev,
···
312
296
}
313
297
}
314
298
315
-
return -EINVAL;
299
+
return -EPROBE_DEFER;
316
300
}
317
301
318
302
/**
···
398
382
ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range);
399
383
if (ret) {
400
384
mutex_unlock(&pinctrl_mutex);
401
-
return -EINVAL;
385
+
return ret;
402
386
}
403
387
404
388
/* Convert to the pin controllers number space */
···
735
719
struct pinctrl_state *state;
736
720
737
721
state = find_state(p, name);
738
-
if (!state)
739
-
return ERR_PTR(-ENODEV);
722
+
if (!state) {
723
+
if (pinctrl_dummy_state) {
724
+
/* create dummy state */
725
+
dev_dbg(p->dev, "using pinctrl dummy state (%s)\n",
726
+
name);
727
+
state = create_state(p, name);
728
+
if (IS_ERR(state))
729
+
return state;
730
+
} else {
731
+
return ERR_PTR(-ENODEV);
732
+
}
733
+
}
740
734
741
735
return state;
742
736
}
···
937
911
case PIN_MAP_TYPE_MUX_GROUP:
938
912
ret = pinmux_validate_map(&maps[i], i);
939
913
if (ret < 0)
940
-
return 0;
914
+
return ret;
941
915
break;
942
916
case PIN_MAP_TYPE_CONFIGS_PIN:
943
917
case PIN_MAP_TYPE_CONFIGS_GROUP:
944
918
ret = pinconf_validate_map(&maps[i], i);
945
919
if (ret < 0)
946
-
return 0;
920
+
return ret;
947
921
break;
948
922
default:
949
923
pr_err("failed to register map %s (%d): invalid type given\n",
···
1417
1391
/* check core ops for sanity */
1418
1392
ret = pinctrl_check_ops(pctldev);
1419
1393
if (ret) {
1420
-
pr_err("%s pinctrl ops lacks necessary functions\n",
1421
-
pctldesc->name);
1394
+
dev_err(dev, "pinctrl ops lacks necessary functions\n");
1422
1395
goto out_err;
1423
1396
}
1424
1397
1425
1398
/* If we're implementing pinmuxing, check the ops for sanity */
1426
1399
if (pctldesc->pmxops) {
1427
1400
ret = pinmux_check_ops(pctldev);
1428
-
if (ret) {
1429
-
pr_err("%s pinmux ops lacks necessary functions\n",
1430
-
pctldesc->name);
1401
+
if (ret)
1431
1402
goto out_err;
1432
-
}
1433
1403
}
1434
1404
1435
1405
/* If we're implementing pinconfig, check the ops for sanity */
1436
1406
if (pctldesc->confops) {
1437
1407
ret = pinconf_check_ops(pctldev);
1438
-
if (ret) {
1439
-
pr_err("%s pin config ops lacks necessary functions\n",
1440
-
pctldesc->name);
1408
+
if (ret)
1441
1409
goto out_err;
1442
-
}
1443
1410
}
1444
1411
1445
1412
/* Register all the pins */
1446
-
pr_debug("try to register %d pins on %s...\n",
1447
-
pctldesc->npins, pctldesc->name);
1413
+
dev_dbg(dev, "try to register %d pins ...\n", pctldesc->npins);
1448
1414
ret = pinctrl_register_pins(pctldev, pctldesc->pins, pctldesc->npins);
1449
1415
if (ret) {
1450
-
pr_err("error during pin registration\n");
1416
+
dev_err(dev, "error during pin registration\n");
1451
1417
pinctrl_free_pindescs(pctldev, pctldesc->pins,
1452
1418
pctldesc->npins);
1453
1419
goto out_err;
···
1454
1436
struct pinctrl_state *s =
1455
1437
pinctrl_lookup_state_locked(pctldev->p,
1456
1438
PINCTRL_STATE_DEFAULT);
1457
-
if (!IS_ERR(s))
1458
-
pinctrl_select_state_locked(pctldev->p, s);
1439
+
if (IS_ERR(s)) {
1440
+
dev_dbg(dev, "failed to lookup the default state\n");
1441
+
} else {
1442
+
ret = pinctrl_select_state_locked(pctldev->p, s);
1443
+
if (ret) {
1444
+
dev_err(dev,
1445
+
"failed to select default state\n");
1446
+
}
1447
+
}
1459
1448
}
1460
1449
1461
1450
mutex_unlock(&pinctrl_mutex);
+8
-2
drivers/pinctrl/pinconf.c
+8
-2
drivers/pinctrl/pinconf.c
···
28
28
const struct pinconf_ops *ops = pctldev->desc->confops;
29
29
30
30
/* We must be able to read out pin status */
31
-
if (!ops->pin_config_get && !ops->pin_config_group_get)
31
+
if (!ops->pin_config_get && !ops->pin_config_group_get) {
32
+
dev_err(pctldev->dev,
33
+
"pinconf must be able to read out pin status\n");
32
34
return -EINVAL;
35
+
}
33
36
/* We have to be able to config the pins in SOME way */
34
-
if (!ops->pin_config_set && !ops->pin_config_group_set)
37
+
if (!ops->pin_config_set && !ops->pin_config_group_set) {
38
+
dev_err(pctldev->dev,
39
+
"pinconf has to be able to set a pins config\n");
35
40
return -EINVAL;
41
+
}
36
42
return 0;
37
43
}
38
44
+627
drivers/pinctrl/pinctrl-imx.c
+627
drivers/pinctrl/pinctrl-imx.c
···
1
+
/*
2
+
* Core driver for the imx pin controller
3
+
*
4
+
* Copyright (C) 2012 Freescale Semiconductor, Inc.
5
+
* Copyright (C) 2012 Linaro Ltd.
6
+
*
7
+
* Author: Dong Aisheng <dong.aisheng@linaro.org>
8
+
*
9
+
* This program is free software; you can redistribute it and/or modify
10
+
* it under the terms of the GNU General Public License as published by
11
+
* the Free Software Foundation; either version 2 of the License, or
12
+
* (at your option) any later version.
13
+
*/
14
+
15
+
#include <linux/err.h>
16
+
#include <linux/init.h>
17
+
#include <linux/io.h>
18
+
#include <linux/module.h>
19
+
#include <linux/of.h>
20
+
#include <linux/of_device.h>
21
+
#include <linux/pinctrl/machine.h>
22
+
#include <linux/pinctrl/pinconf.h>
23
+
#include <linux/pinctrl/pinctrl.h>
24
+
#include <linux/pinctrl/pinmux.h>
25
+
#include <linux/slab.h>
26
+
27
+
#include "core.h"
28
+
#include "pinctrl-imx.h"
29
+
30
+
#define IMX_PMX_DUMP(info, p, m, c, n) \
31
+
{ \
32
+
int i, j; \
33
+
printk("Format: Pin Mux Config\n"); \
34
+
for (i = 0; i < n; i++) { \
35
+
j = p[i]; \
36
+
printk("%s %d 0x%lx\n", \
37
+
info->pins[j].name, \
38
+
m[i], c[i]); \
39
+
} \
40
+
}
41
+
42
+
/* The bits in CONFIG cell defined in binding doc*/
43
+
#define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */
44
+
#define IMX_PAD_SION 0x40000000 /* set SION */
45
+
46
+
/**
47
+
* @dev: a pointer back to containing device
48
+
* @base: the offset to the controller in virtual memory
49
+
*/
50
+
struct imx_pinctrl {
51
+
struct device *dev;
52
+
struct pinctrl_dev *pctl;
53
+
void __iomem *base;
54
+
const struct imx_pinctrl_soc_info *info;
55
+
};
56
+
57
+
static const struct imx_pin_reg *imx_find_pin_reg(
58
+
const struct imx_pinctrl_soc_info *info,
59
+
unsigned pin, bool is_mux, unsigned mux)
60
+
{
61
+
const struct imx_pin_reg *pin_reg = NULL;
62
+
int i;
63
+
64
+
for (i = 0; i < info->npin_regs; i++) {
65
+
pin_reg = &info->pin_regs[i];
66
+
if (pin_reg->pid != pin)
67
+
continue;
68
+
if (!is_mux)
69
+
break;
70
+
else if (pin_reg->mux_mode == (mux & IMX_MUX_MASK))
71
+
break;
72
+
}
73
+
74
+
if (!pin_reg) {
75
+
dev_err(info->dev, "Pin(%s): unable to find pin reg map\n",
76
+
info->pins[pin].name);
77
+
return NULL;
78
+
}
79
+
80
+
return pin_reg;
81
+
}
82
+
83
+
static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name(
84
+
const struct imx_pinctrl_soc_info *info,
85
+
const char *name)
86
+
{
87
+
const struct imx_pin_group *grp = NULL;
88
+
int i;
89
+
90
+
for (i = 0; i < info->ngroups; i++) {
91
+
if (!strcmp(info->groups[i].name, name)) {
92
+
grp = &info->groups[i];
93
+
break;
94
+
}
95
+
}
96
+
97
+
return grp;
98
+
}
99
+
100
+
static int imx_get_groups_count(struct pinctrl_dev *pctldev)
101
+
{
102
+
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
103
+
const struct imx_pinctrl_soc_info *info = ipctl->info;
104
+
105
+
return info->ngroups;
106
+
}
107
+
108
+
static const char *imx_get_group_name(struct pinctrl_dev *pctldev,
109
+
unsigned selector)
110
+
{
111
+
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
112
+
const struct imx_pinctrl_soc_info *info = ipctl->info;
113
+
114
+
return info->groups[selector].name;
115
+
}
116
+
117
+
static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
118
+
const unsigned **pins,
119
+
unsigned *npins)
120
+
{
121
+
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
122
+
const struct imx_pinctrl_soc_info *info = ipctl->info;
123
+
124
+
if (selector >= info->ngroups)
125
+
return -EINVAL;
126
+
127
+
*pins = info->groups[selector].pins;
128
+
*npins = info->groups[selector].npins;
129
+
130
+
return 0;
131
+
}
132
+
133
+
static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
134
+
unsigned offset)
135
+
{
136
+
seq_printf(s, "%s", dev_name(pctldev->dev));
137
+
}
138
+
139
+
static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
140
+
struct device_node *np,
141
+
struct pinctrl_map **map, unsigned *num_maps)
142
+
{
143
+
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
144
+
const struct imx_pinctrl_soc_info *info = ipctl->info;
145
+
const struct imx_pin_group *grp;
146
+
struct pinctrl_map *new_map;
147
+
struct device_node *parent;
148
+
int map_num = 1;
149
+
int i;
150
+
151
+
/*
152
+
* first find the group of this node and check if we need create
153
+
* config maps for pins
154
+
*/
155
+
grp = imx_pinctrl_find_group_by_name(info, np->name);
156
+
if (!grp) {
157
+
dev_err(info->dev, "unable to find group for node %s\n",
158
+
np->name);
159
+
return -EINVAL;
160
+
}
161
+
162
+
for (i = 0; i < grp->npins; i++) {
163
+
if (!(grp->configs[i] & IMX_NO_PAD_CTL))
164
+
map_num++;
165
+
}
166
+
167
+
new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
168
+
if (!new_map)
169
+
return -ENOMEM;
170
+
171
+
*map = new_map;
172
+
*num_maps = map_num;
173
+
174
+
/* create mux map */
175
+
parent = of_get_parent(np);
176
+
if (!parent)
177
+
return -EINVAL;
178
+
new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
179
+
new_map[0].data.mux.function = parent->name;
180
+
new_map[0].data.mux.group = np->name;
181
+
of_node_put(parent);
182
+
183
+
/* create config map */
184
+
new_map++;
185
+
for (i = 0; i < grp->npins; i++) {
186
+
if (!(grp->configs[i] & IMX_NO_PAD_CTL)) {
187
+
new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
188
+
new_map[i].data.configs.group_or_pin =
189
+
pin_get_name(pctldev, grp->pins[i]);
190
+
new_map[i].data.configs.configs = &grp->configs[i];
191
+
new_map[i].data.configs.num_configs = 1;
192
+
}
193
+
}
194
+
195
+
dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
196
+
new_map->data.mux.function, new_map->data.mux.group, map_num);
197
+
198
+
return 0;
199
+
}
200
+
201
+
static void imx_dt_free_map(struct pinctrl_dev *pctldev,
202
+
struct pinctrl_map *map, unsigned num_maps)
203
+
{
204
+
int i;
205
+
206
+
for (i = 0; i < num_maps; i++)
207
+
kfree(map);
208
+
}
209
+
210
+
static struct pinctrl_ops imx_pctrl_ops = {
211
+
.get_groups_count = imx_get_groups_count,
212
+
.get_group_name = imx_get_group_name,
213
+
.get_group_pins = imx_get_group_pins,
214
+
.pin_dbg_show = imx_pin_dbg_show,
215
+
.dt_node_to_map = imx_dt_node_to_map,
216
+
.dt_free_map = imx_dt_free_map,
217
+
218
+
};
219
+
220
+
static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
221
+
unsigned group)
222
+
{
223
+
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
224
+
const struct imx_pinctrl_soc_info *info = ipctl->info;
225
+
const struct imx_pin_reg *pin_reg;
226
+
const unsigned *pins, *mux;
227
+
unsigned int npins, pin_id;
228
+
int i;
229
+
230
+
/*
231
+
* Configure the mux mode for each pin in the group for a specific
232
+
* function.
233
+
*/
234
+
pins = info->groups[group].pins;
235
+
npins = info->groups[group].npins;
236
+
mux = info->groups[group].mux_mode;
237
+
238
+
WARN_ON(!pins || !npins || !mux);
239
+
240
+
dev_dbg(ipctl->dev, "enable function %s group %s\n",
241
+
info->functions[selector].name, info->groups[group].name);
242
+
243
+
for (i = 0; i < npins; i++) {
244
+
pin_id = pins[i];
245
+
246
+
pin_reg = imx_find_pin_reg(info, pin_id, 1, mux[i]);
247
+
if (!pin_reg)
248
+
return -EINVAL;
249
+
250
+
if (!pin_reg->mux_reg) {
251
+
dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
252
+
info->pins[pin_id].name);
253
+
return -EINVAL;
254
+
}
255
+
256
+
writel(mux[i], ipctl->base + pin_reg->mux_reg);
257
+
dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
258
+
pin_reg->mux_reg, mux[i]);
259
+
260
+
/* some pins also need select input setting, set it if found */
261
+
if (pin_reg->input_reg) {
262
+
writel(pin_reg->input_val, ipctl->base + pin_reg->input_reg);
263
+
dev_dbg(ipctl->dev,
264
+
"==>select_input: offset 0x%x val 0x%x\n",
265
+
pin_reg->input_reg, pin_reg->input_val);
266
+
}
267
+
}
268
+
269
+
return 0;
270
+
}
271
+
272
+
static void imx_pmx_disable(struct pinctrl_dev *pctldev, unsigned func_selector,
273
+
unsigned group_selector)
274
+
{
275
+
/* nothing to do here */
276
+
}
277
+
278
+
static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
279
+
{
280
+
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
281
+
const struct imx_pinctrl_soc_info *info = ipctl->info;
282
+
283
+
return info->nfunctions;
284
+
}
285
+
286
+
static const char *imx_pmx_get_func_name(struct pinctrl_dev *pctldev,
287
+
unsigned selector)
288
+
{
289
+
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
290
+
const struct imx_pinctrl_soc_info *info = ipctl->info;
291
+
292
+
return info->functions[selector].name;
293
+
}
294
+
295
+
static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
296
+
const char * const **groups,
297
+
unsigned * const num_groups)
298
+
{
299
+
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
300
+
const struct imx_pinctrl_soc_info *info = ipctl->info;
301
+
302
+
*groups = info->functions[selector].groups;
303
+
*num_groups = info->functions[selector].num_groups;
304
+
305
+
return 0;
306
+
}
307
+
308
+
static struct pinmux_ops imx_pmx_ops = {
309
+
.get_functions_count = imx_pmx_get_funcs_count,
310
+
.get_function_name = imx_pmx_get_func_name,
311
+
.get_function_groups = imx_pmx_get_groups,
312
+
.enable = imx_pmx_enable,
313
+
.disable = imx_pmx_disable,
314
+
};
315
+
316
+
static int imx_pinconf_get(struct pinctrl_dev *pctldev,
317
+
unsigned pin_id, unsigned long *config)
318
+
{
319
+
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
320
+
const struct imx_pinctrl_soc_info *info = ipctl->info;
321
+
const struct imx_pin_reg *pin_reg;
322
+
323
+
pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
324
+
if (!pin_reg)
325
+
return -EINVAL;
326
+
327
+
if (!pin_reg->conf_reg) {
328
+
dev_err(info->dev, "Pin(%s) does not support config function\n",
329
+
info->pins[pin_id].name);
330
+
return -EINVAL;
331
+
}
332
+
333
+
*config = readl(ipctl->base + pin_reg->conf_reg);
334
+
335
+
return 0;
336
+
}
337
+
338
+
static int imx_pinconf_set(struct pinctrl_dev *pctldev,
339
+
unsigned pin_id, unsigned long config)
340
+
{
341
+
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
342
+
const struct imx_pinctrl_soc_info *info = ipctl->info;
343
+
const struct imx_pin_reg *pin_reg;
344
+
345
+
pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
346
+
if (!pin_reg)
347
+
return -EINVAL;
348
+
349
+
if (!pin_reg->conf_reg) {
350
+
dev_err(info->dev, "Pin(%s) does not support config function\n",
351
+
info->pins[pin_id].name);
352
+
return -EINVAL;
353
+
}
354
+
355
+
dev_dbg(ipctl->dev, "pinconf set pin %s\n",
356
+
info->pins[pin_id].name);
357
+
358
+
writel(config, ipctl->base + pin_reg->conf_reg);
359
+
dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
360
+
pin_reg->conf_reg, config);
361
+
362
+
return 0;
363
+
}
364
+
365
+
static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
366
+
struct seq_file *s, unsigned pin_id)
367
+
{
368
+
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
369
+
const struct imx_pinctrl_soc_info *info = ipctl->info;
370
+
const struct imx_pin_reg *pin_reg;
371
+
unsigned long config;
372
+
373
+
pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
374
+
if (!pin_reg || !pin_reg->conf_reg) {
375
+
seq_printf(s, "N/A");
376
+
return;
377
+
}
378
+
379
+
config = readl(ipctl->base + pin_reg->conf_reg);
380
+
seq_printf(s, "0x%lx", config);
381
+
}
382
+
383
+
static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
384
+
struct seq_file *s, unsigned group)
385
+
{
386
+
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
387
+
const struct imx_pinctrl_soc_info *info = ipctl->info;
388
+
struct imx_pin_group *grp;
389
+
unsigned long config;
390
+
const char *name;
391
+
int i, ret;
392
+
393
+
if (group > info->ngroups)
394
+
return;
395
+
396
+
seq_printf(s, "\n");
397
+
grp = &info->groups[group];
398
+
for (i = 0; i < grp->npins; i++) {
399
+
name = pin_get_name(pctldev, grp->pins[i]);
400
+
ret = imx_pinconf_get(pctldev, grp->pins[i], &config);
401
+
if (ret)
402
+
return;
403
+
seq_printf(s, "%s: 0x%lx", name, config);
404
+
}
405
+
}
406
+
407
+
struct pinconf_ops imx_pinconf_ops = {
408
+
.pin_config_get = imx_pinconf_get,
409
+
.pin_config_set = imx_pinconf_set,
410
+
.pin_config_dbg_show = imx_pinconf_dbg_show,
411
+
.pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
412
+
};
413
+
414
+
static struct pinctrl_desc imx_pinctrl_desc = {
415
+
.pctlops = &imx_pctrl_ops,
416
+
.pmxops = &imx_pmx_ops,
417
+
.confops = &imx_pinconf_ops,
418
+
.owner = THIS_MODULE,
419
+
};
420
+
421
+
/* decode pin id and mux from pin function id got from device tree*/
422
+
static int imx_pinctrl_get_pin_id_and_mux(const struct imx_pinctrl_soc_info *info,
423
+
unsigned int pin_func_id, unsigned int *pin_id,
424
+
unsigned int *mux)
425
+
{
426
+
if (pin_func_id > info->npin_regs)
427
+
return -EINVAL;
428
+
429
+
*pin_id = info->pin_regs[pin_func_id].pid;
430
+
*mux = info->pin_regs[pin_func_id].mux_mode;
431
+
432
+
return 0;
433
+
}
434
+
435
+
static int __devinit imx_pinctrl_parse_groups(struct device_node *np,
436
+
struct imx_pin_group *grp,
437
+
struct imx_pinctrl_soc_info *info,
438
+
u32 index)
439
+
{
440
+
unsigned int pin_func_id;
441
+
int ret, size;
442
+
const const __be32 *list;
443
+
int i, j;
444
+
u32 config;
445
+
446
+
dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
447
+
448
+
/* Initialise group */
449
+
grp->name = np->name;
450
+
451
+
/*
452
+
* the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
453
+
* do sanity check and calculate pins number
454
+
*/
455
+
list = of_get_property(np, "fsl,pins", &size);
456
+
/* we do not check return since it's safe node passed down */
457
+
size /= sizeof(*list);
458
+
if (!size || size % 2) {
459
+
dev_err(info->dev, "wrong pins number or pins and configs should be pairs\n");
460
+
return -EINVAL;
461
+
}
462
+
463
+
grp->npins = size / 2;
464
+
grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
465
+
GFP_KERNEL);
466
+
grp->mux_mode = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
467
+
GFP_KERNEL);
468
+
grp->configs = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned long),
469
+
GFP_KERNEL);
470
+
for (i = 0, j = 0; i < size; i += 2, j++) {
471
+
pin_func_id = be32_to_cpu(*list++);
472
+
ret = imx_pinctrl_get_pin_id_and_mux(info, pin_func_id,
473
+
&grp->pins[j], &grp->mux_mode[j]);
474
+
if (ret) {
475
+
dev_err(info->dev, "get invalid pin function id\n");
476
+
return -EINVAL;
477
+
}
478
+
/* SION bit is in mux register */
479
+
config = be32_to_cpu(*list++);
480
+
if (config & IMX_PAD_SION)
481
+
grp->mux_mode[j] |= IOMUXC_CONFIG_SION;
482
+
grp->configs[j] = config & ~IMX_PAD_SION;
483
+
}
484
+
485
+
#ifdef DEBUG
486
+
IMX_PMX_DUMP(info, grp->pins, grp->mux_mode, grp->configs, grp->npins);
487
+
#endif
488
+
return 0;
489
+
}
490
+
491
+
static int __devinit imx_pinctrl_parse_functions(struct device_node *np,
492
+
struct imx_pinctrl_soc_info *info, u32 index)
493
+
{
494
+
struct device_node *child;
495
+
struct imx_pmx_func *func;
496
+
struct imx_pin_group *grp;
497
+
int ret;
498
+
static u32 grp_index;
499
+
u32 i = 0;
500
+
501
+
dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
502
+
503
+
func = &info->functions[index];
504
+
505
+
/* Initialise function */
506
+
func->name = np->name;
507
+
func->num_groups = of_get_child_count(np);
508
+
if (func->num_groups <= 0) {
509
+
dev_err(info->dev, "no groups defined\n");
510
+
return -EINVAL;
511
+
}
512
+
func->groups = devm_kzalloc(info->dev,
513
+
func->num_groups * sizeof(char *), GFP_KERNEL);
514
+
515
+
for_each_child_of_node(np, child) {
516
+
func->groups[i] = child->name;
517
+
grp = &info->groups[grp_index++];
518
+
ret = imx_pinctrl_parse_groups(child, grp, info, i++);
519
+
if (ret)
520
+
return ret;
521
+
}
522
+
523
+
return 0;
524
+
}
525
+
526
+
static int __devinit imx_pinctrl_probe_dt(struct platform_device *pdev,
527
+
struct imx_pinctrl_soc_info *info)
528
+
{
529
+
struct device_node *np = pdev->dev.of_node;
530
+
struct device_node *child;
531
+
int ret;
532
+
u32 nfuncs = 0;
533
+
u32 i = 0;
534
+
535
+
if (!np)
536
+
return -ENODEV;
537
+
538
+
nfuncs = of_get_child_count(np);
539
+
if (nfuncs <= 0) {
540
+
dev_err(&pdev->dev, "no functions defined\n");
541
+
return -EINVAL;
542
+
}
543
+
544
+
info->nfunctions = nfuncs;
545
+
info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func),
546
+
GFP_KERNEL);
547
+
if (!info->functions)
548
+
return -ENOMEM;
549
+
550
+
info->ngroups = 0;
551
+
for_each_child_of_node(np, child)
552
+
info->ngroups += of_get_child_count(child);
553
+
info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group),
554
+
GFP_KERNEL);
555
+
if (!info->groups)
556
+
return -ENOMEM;
557
+
558
+
for_each_child_of_node(np, child) {
559
+
ret = imx_pinctrl_parse_functions(child, info, i++);
560
+
if (ret) {
561
+
dev_err(&pdev->dev, "failed to parse function\n");
562
+
return ret;
563
+
}
564
+
}
565
+
566
+
return 0;
567
+
}
568
+
569
+
int __devinit imx_pinctrl_probe(struct platform_device *pdev,
570
+
struct imx_pinctrl_soc_info *info)
571
+
{
572
+
struct imx_pinctrl *ipctl;
573
+
struct resource *res;
574
+
int ret;
575
+
576
+
if (!info || !info->pins || !info->npins
577
+
|| !info->pin_regs || !info->npin_regs) {
578
+
dev_err(&pdev->dev, "wrong pinctrl info\n");
579
+
return -EINVAL;
580
+
}
581
+
info->dev = &pdev->dev;
582
+
583
+
/* Create state holders etc for this driver */
584
+
ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
585
+
if (!ipctl)
586
+
return -ENOMEM;
587
+
588
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
589
+
if (!res)
590
+
return -ENOENT;
591
+
592
+
ipctl->base = devm_request_and_ioremap(&pdev->dev, res);
593
+
if (!ipctl->base)
594
+
return -EBUSY;
595
+
596
+
imx_pinctrl_desc.name = dev_name(&pdev->dev);
597
+
imx_pinctrl_desc.pins = info->pins;
598
+
imx_pinctrl_desc.npins = info->npins;
599
+
600
+
ret = imx_pinctrl_probe_dt(pdev, info);
601
+
if (ret) {
602
+
dev_err(&pdev->dev, "fail to probe dt properties\n");
603
+
return ret;
604
+
}
605
+
606
+
ipctl->info = info;
607
+
ipctl->dev = info->dev;
608
+
platform_set_drvdata(pdev, ipctl);
609
+
ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl);
610
+
if (!ipctl->pctl) {
611
+
dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
612
+
return -EINVAL;
613
+
}
614
+
615
+
dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
616
+
617
+
return 0;
618
+
}
619
+
620
+
int __devexit imx_pinctrl_remove(struct platform_device *pdev)
621
+
{
622
+
struct imx_pinctrl *ipctl = platform_get_drvdata(pdev);
623
+
624
+
pinctrl_unregister(ipctl->pctl);
625
+
626
+
return 0;
627
+
}
+106
drivers/pinctrl/pinctrl-imx.h
+106
drivers/pinctrl/pinctrl-imx.h
···
1
+
/*
2
+
* IMX pinmux core definitions
3
+
*
4
+
* Copyright (C) 2012 Freescale Semiconductor, Inc.
5
+
* Copyright (C) 2012 Linaro Ltd.
6
+
*
7
+
* Author: Dong Aisheng <dong.aisheng@linaro.org>
8
+
*
9
+
* This program is free software; you can redistribute it and/or modify
10
+
* it under the terms of the GNU General Public License as published by
11
+
* the Free Software Foundation; either version 2 of the License, or
12
+
* (at your option) any later version.
13
+
*/
14
+
15
+
#ifndef __DRIVERS_PINCTRL_IMX_H
16
+
#define __DRIVERS_PINCTRL_IMX_H
17
+
18
+
struct platform_device;
19
+
20
+
/**
21
+
* struct imx_pin_group - describes an IMX pin group
22
+
* @name: the name of this specific pin group
23
+
* @pins: an array of discrete physical pins used in this group, taken
24
+
* from the driver-local pin enumeration space
25
+
* @npins: the number of pins in this group array, i.e. the number of
26
+
* elements in .pins so we can iterate over that array
27
+
* @mux_mode: the mux mode for each pin in this group. The size of this
28
+
* array is the same as pins.
29
+
* @configs: the config for each pin in this group. The size of this
30
+
* array is the same as pins.
31
+
*/
32
+
struct imx_pin_group {
33
+
const char *name;
34
+
unsigned int *pins;
35
+
unsigned npins;
36
+
unsigned int *mux_mode;
37
+
unsigned long *configs;
38
+
};
39
+
40
+
/**
41
+
* struct imx_pmx_func - describes IMX pinmux functions
42
+
* @name: the name of this specific function
43
+
* @groups: corresponding pin groups
44
+
* @num_groups: the number of groups
45
+
*/
46
+
struct imx_pmx_func {
47
+
const char *name;
48
+
const char **groups;
49
+
unsigned num_groups;
50
+
};
51
+
52
+
/**
53
+
* struct imx_pin_reg - describe a pin reg map
54
+
* The last 3 members are used for select input setting
55
+
* @pid: pin id
56
+
* @mux_reg: mux register offset
57
+
* @conf_reg: config register offset
58
+
* @mux_mode: mux mode
59
+
* @input_reg: select input register offset for this mux if any
60
+
* 0 if no select input setting needed.
61
+
* @input_val: the value set to select input register
62
+
*/
63
+
struct imx_pin_reg {
64
+
u16 pid;
65
+
u16 mux_reg;
66
+
u16 conf_reg;
67
+
u8 mux_mode;
68
+
u16 input_reg;
69
+
u8 input_val;
70
+
};
71
+
72
+
struct imx_pinctrl_soc_info {
73
+
struct device *dev;
74
+
const struct pinctrl_pin_desc *pins;
75
+
unsigned int npins;
76
+
const struct imx_pin_reg *pin_regs;
77
+
unsigned int npin_regs;
78
+
struct imx_pin_group *groups;
79
+
unsigned int ngroups;
80
+
struct imx_pmx_func *functions;
81
+
unsigned int nfunctions;
82
+
};
83
+
84
+
#define NO_MUX 0x0
85
+
#define NO_PAD 0x0
86
+
87
+
#define IMX_PIN_REG(id, conf, mux, mode, input, val) \
88
+
{ \
89
+
.pid = id, \
90
+
.conf_reg = conf, \
91
+
.mux_reg = mux, \
92
+
.mux_mode = mode, \
93
+
.input_reg = input, \
94
+
.input_val = val, \
95
+
}
96
+
97
+
#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
98
+
99
+
#define PAD_CTL_MASK(len) ((1 << len) - 1)
100
+
#define IMX_MUX_MASK 0x7
101
+
#define IOMUXC_CONFIG_SION (0x1 << 4)
102
+
103
+
int imx_pinctrl_probe(struct platform_device *pdev,
104
+
struct imx_pinctrl_soc_info *info);
105
+
int imx_pinctrl_remove(struct platform_device *pdev);
106
+
#endif /* __DRIVERS_PINCTRL_IMX_H */
+305
drivers/pinctrl/pinctrl-imx23.c
+305
drivers/pinctrl/pinctrl-imx23.c
···
1
+
/*
2
+
* Copyright 2012 Freescale Semiconductor, Inc.
3
+
*
4
+
* The code contained herein is licensed under the GNU General Public
5
+
* License. You may obtain a copy of the GNU General Public License
6
+
* Version 2 or later at the following locations:
7
+
*
8
+
* http://www.opensource.org/licenses/gpl-license.html
9
+
* http://www.gnu.org/copyleft/gpl.html
10
+
*/
11
+
12
+
#include <linux/init.h>
13
+
#include <linux/module.h>
14
+
#include <linux/of_device.h>
15
+
#include <linux/pinctrl/pinctrl.h>
16
+
#include "pinctrl-mxs.h"
17
+
18
+
enum imx23_pin_enum {
19
+
GPMI_D00 = PINID(0, 0),
20
+
GPMI_D01 = PINID(0, 1),
21
+
GPMI_D02 = PINID(0, 2),
22
+
GPMI_D03 = PINID(0, 3),
23
+
GPMI_D04 = PINID(0, 4),
24
+
GPMI_D05 = PINID(0, 5),
25
+
GPMI_D06 = PINID(0, 6),
26
+
GPMI_D07 = PINID(0, 7),
27
+
GPMI_D08 = PINID(0, 8),
28
+
GPMI_D09 = PINID(0, 9),
29
+
GPMI_D10 = PINID(0, 10),
30
+
GPMI_D11 = PINID(0, 11),
31
+
GPMI_D12 = PINID(0, 12),
32
+
GPMI_D13 = PINID(0, 13),
33
+
GPMI_D14 = PINID(0, 14),
34
+
GPMI_D15 = PINID(0, 15),
35
+
GPMI_CLE = PINID(0, 16),
36
+
GPMI_ALE = PINID(0, 17),
37
+
GPMI_CE2N = PINID(0, 18),
38
+
GPMI_RDY0 = PINID(0, 19),
39
+
GPMI_RDY1 = PINID(0, 20),
40
+
GPMI_RDY2 = PINID(0, 21),
41
+
GPMI_RDY3 = PINID(0, 22),
42
+
GPMI_WPN = PINID(0, 23),
43
+
GPMI_WRN = PINID(0, 24),
44
+
GPMI_RDN = PINID(0, 25),
45
+
AUART1_CTS = PINID(0, 26),
46
+
AUART1_RTS = PINID(0, 27),
47
+
AUART1_RX = PINID(0, 28),
48
+
AUART1_TX = PINID(0, 29),
49
+
I2C_SCL = PINID(0, 30),
50
+
I2C_SDA = PINID(0, 31),
51
+
LCD_D00 = PINID(1, 0),
52
+
LCD_D01 = PINID(1, 1),
53
+
LCD_D02 = PINID(1, 2),
54
+
LCD_D03 = PINID(1, 3),
55
+
LCD_D04 = PINID(1, 4),
56
+
LCD_D05 = PINID(1, 5),
57
+
LCD_D06 = PINID(1, 6),
58
+
LCD_D07 = PINID(1, 7),
59
+
LCD_D08 = PINID(1, 8),
60
+
LCD_D09 = PINID(1, 9),
61
+
LCD_D10 = PINID(1, 10),
62
+
LCD_D11 = PINID(1, 11),
63
+
LCD_D12 = PINID(1, 12),
64
+
LCD_D13 = PINID(1, 13),
65
+
LCD_D14 = PINID(1, 14),
66
+
LCD_D15 = PINID(1, 15),
67
+
LCD_D16 = PINID(1, 16),
68
+
LCD_D17 = PINID(1, 17),
69
+
LCD_RESET = PINID(1, 18),
70
+
LCD_RS = PINID(1, 19),
71
+
LCD_WR = PINID(1, 20),
72
+
LCD_CS = PINID(1, 21),
73
+
LCD_DOTCK = PINID(1, 22),
74
+
LCD_ENABLE = PINID(1, 23),
75
+
LCD_HSYNC = PINID(1, 24),
76
+
LCD_VSYNC = PINID(1, 25),
77
+
PWM0 = PINID(1, 26),
78
+
PWM1 = PINID(1, 27),
79
+
PWM2 = PINID(1, 28),
80
+
PWM3 = PINID(1, 29),
81
+
PWM4 = PINID(1, 30),
82
+
SSP1_CMD = PINID(2, 0),
83
+
SSP1_DETECT = PINID(2, 1),
84
+
SSP1_DATA0 = PINID(2, 2),
85
+
SSP1_DATA1 = PINID(2, 3),
86
+
SSP1_DATA2 = PINID(2, 4),
87
+
SSP1_DATA3 = PINID(2, 5),
88
+
SSP1_SCK = PINID(2, 6),
89
+
ROTARYA = PINID(2, 7),
90
+
ROTARYB = PINID(2, 8),
91
+
EMI_A00 = PINID(2, 9),
92
+
EMI_A01 = PINID(2, 10),
93
+
EMI_A02 = PINID(2, 11),
94
+
EMI_A03 = PINID(2, 12),
95
+
EMI_A04 = PINID(2, 13),
96
+
EMI_A05 = PINID(2, 14),
97
+
EMI_A06 = PINID(2, 15),
98
+
EMI_A07 = PINID(2, 16),
99
+
EMI_A08 = PINID(2, 17),
100
+
EMI_A09 = PINID(2, 18),
101
+
EMI_A10 = PINID(2, 19),
102
+
EMI_A11 = PINID(2, 20),
103
+
EMI_A12 = PINID(2, 21),
104
+
EMI_BA0 = PINID(2, 22),
105
+
EMI_BA1 = PINID(2, 23),
106
+
EMI_CASN = PINID(2, 24),
107
+
EMI_CE0N = PINID(2, 25),
108
+
EMI_CE1N = PINID(2, 26),
109
+
GPMI_CE1N = PINID(2, 27),
110
+
GPMI_CE0N = PINID(2, 28),
111
+
EMI_CKE = PINID(2, 29),
112
+
EMI_RASN = PINID(2, 30),
113
+
EMI_WEN = PINID(2, 31),
114
+
EMI_D00 = PINID(3, 0),
115
+
EMI_D01 = PINID(3, 1),
116
+
EMI_D02 = PINID(3, 2),
117
+
EMI_D03 = PINID(3, 3),
118
+
EMI_D04 = PINID(3, 4),
119
+
EMI_D05 = PINID(3, 5),
120
+
EMI_D06 = PINID(3, 6),
121
+
EMI_D07 = PINID(3, 7),
122
+
EMI_D08 = PINID(3, 8),
123
+
EMI_D09 = PINID(3, 9),
124
+
EMI_D10 = PINID(3, 10),
125
+
EMI_D11 = PINID(3, 11),
126
+
EMI_D12 = PINID(3, 12),
127
+
EMI_D13 = PINID(3, 13),
128
+
EMI_D14 = PINID(3, 14),
129
+
EMI_D15 = PINID(3, 15),
130
+
EMI_DQM0 = PINID(3, 16),
131
+
EMI_DQM1 = PINID(3, 17),
132
+
EMI_DQS0 = PINID(3, 18),
133
+
EMI_DQS1 = PINID(3, 19),
134
+
EMI_CLK = PINID(3, 20),
135
+
EMI_CLKN = PINID(3, 21),
136
+
};
137
+
138
+
static const struct pinctrl_pin_desc imx23_pins[] = {
139
+
MXS_PINCTRL_PIN(GPMI_D00),
140
+
MXS_PINCTRL_PIN(GPMI_D01),
141
+
MXS_PINCTRL_PIN(GPMI_D02),
142
+
MXS_PINCTRL_PIN(GPMI_D03),
143
+
MXS_PINCTRL_PIN(GPMI_D04),
144
+
MXS_PINCTRL_PIN(GPMI_D05),
145
+
MXS_PINCTRL_PIN(GPMI_D06),
146
+
MXS_PINCTRL_PIN(GPMI_D07),
147
+
MXS_PINCTRL_PIN(GPMI_D08),
148
+
MXS_PINCTRL_PIN(GPMI_D09),
149
+
MXS_PINCTRL_PIN(GPMI_D10),
150
+
MXS_PINCTRL_PIN(GPMI_D11),
151
+
MXS_PINCTRL_PIN(GPMI_D12),
152
+
MXS_PINCTRL_PIN(GPMI_D13),
153
+
MXS_PINCTRL_PIN(GPMI_D14),
154
+
MXS_PINCTRL_PIN(GPMI_D15),
155
+
MXS_PINCTRL_PIN(GPMI_CLE),
156
+
MXS_PINCTRL_PIN(GPMI_ALE),
157
+
MXS_PINCTRL_PIN(GPMI_CE2N),
158
+
MXS_PINCTRL_PIN(GPMI_RDY0),
159
+
MXS_PINCTRL_PIN(GPMI_RDY1),
160
+
MXS_PINCTRL_PIN(GPMI_RDY2),
161
+
MXS_PINCTRL_PIN(GPMI_RDY3),
162
+
MXS_PINCTRL_PIN(GPMI_WPN),
163
+
MXS_PINCTRL_PIN(GPMI_WRN),
164
+
MXS_PINCTRL_PIN(GPMI_RDN),
165
+
MXS_PINCTRL_PIN(AUART1_CTS),
166
+
MXS_PINCTRL_PIN(AUART1_RTS),
167
+
MXS_PINCTRL_PIN(AUART1_RX),
168
+
MXS_PINCTRL_PIN(AUART1_TX),
169
+
MXS_PINCTRL_PIN(I2C_SCL),
170
+
MXS_PINCTRL_PIN(I2C_SDA),
171
+
MXS_PINCTRL_PIN(LCD_D00),
172
+
MXS_PINCTRL_PIN(LCD_D01),
173
+
MXS_PINCTRL_PIN(LCD_D02),
174
+
MXS_PINCTRL_PIN(LCD_D03),
175
+
MXS_PINCTRL_PIN(LCD_D04),
176
+
MXS_PINCTRL_PIN(LCD_D05),
177
+
MXS_PINCTRL_PIN(LCD_D06),
178
+
MXS_PINCTRL_PIN(LCD_D07),
179
+
MXS_PINCTRL_PIN(LCD_D08),
180
+
MXS_PINCTRL_PIN(LCD_D09),
181
+
MXS_PINCTRL_PIN(LCD_D10),
182
+
MXS_PINCTRL_PIN(LCD_D11),
183
+
MXS_PINCTRL_PIN(LCD_D12),
184
+
MXS_PINCTRL_PIN(LCD_D13),
185
+
MXS_PINCTRL_PIN(LCD_D14),
186
+
MXS_PINCTRL_PIN(LCD_D15),
187
+
MXS_PINCTRL_PIN(LCD_D16),
188
+
MXS_PINCTRL_PIN(LCD_D17),
189
+
MXS_PINCTRL_PIN(LCD_RESET),
190
+
MXS_PINCTRL_PIN(LCD_RS),
191
+
MXS_PINCTRL_PIN(LCD_WR),
192
+
MXS_PINCTRL_PIN(LCD_CS),
193
+
MXS_PINCTRL_PIN(LCD_DOTCK),
194
+
MXS_PINCTRL_PIN(LCD_ENABLE),
195
+
MXS_PINCTRL_PIN(LCD_HSYNC),
196
+
MXS_PINCTRL_PIN(LCD_VSYNC),
197
+
MXS_PINCTRL_PIN(PWM0),
198
+
MXS_PINCTRL_PIN(PWM1),
199
+
MXS_PINCTRL_PIN(PWM2),
200
+
MXS_PINCTRL_PIN(PWM3),
201
+
MXS_PINCTRL_PIN(PWM4),
202
+
MXS_PINCTRL_PIN(SSP1_CMD),
203
+
MXS_PINCTRL_PIN(SSP1_DETECT),
204
+
MXS_PINCTRL_PIN(SSP1_DATA0),
205
+
MXS_PINCTRL_PIN(SSP1_DATA1),
206
+
MXS_PINCTRL_PIN(SSP1_DATA2),
207
+
MXS_PINCTRL_PIN(SSP1_DATA3),
208
+
MXS_PINCTRL_PIN(SSP1_SCK),
209
+
MXS_PINCTRL_PIN(ROTARYA),
210
+
MXS_PINCTRL_PIN(ROTARYB),
211
+
MXS_PINCTRL_PIN(EMI_A00),
212
+
MXS_PINCTRL_PIN(EMI_A01),
213
+
MXS_PINCTRL_PIN(EMI_A02),
214
+
MXS_PINCTRL_PIN(EMI_A03),
215
+
MXS_PINCTRL_PIN(EMI_A04),
216
+
MXS_PINCTRL_PIN(EMI_A05),
217
+
MXS_PINCTRL_PIN(EMI_A06),
218
+
MXS_PINCTRL_PIN(EMI_A07),
219
+
MXS_PINCTRL_PIN(EMI_A08),
220
+
MXS_PINCTRL_PIN(EMI_A09),
221
+
MXS_PINCTRL_PIN(EMI_A10),
222
+
MXS_PINCTRL_PIN(EMI_A11),
223
+
MXS_PINCTRL_PIN(EMI_A12),
224
+
MXS_PINCTRL_PIN(EMI_BA0),
225
+
MXS_PINCTRL_PIN(EMI_BA1),
226
+
MXS_PINCTRL_PIN(EMI_CASN),
227
+
MXS_PINCTRL_PIN(EMI_CE0N),
228
+
MXS_PINCTRL_PIN(EMI_CE1N),
229
+
MXS_PINCTRL_PIN(GPMI_CE1N),
230
+
MXS_PINCTRL_PIN(GPMI_CE0N),
231
+
MXS_PINCTRL_PIN(EMI_CKE),
232
+
MXS_PINCTRL_PIN(EMI_RASN),
233
+
MXS_PINCTRL_PIN(EMI_WEN),
234
+
MXS_PINCTRL_PIN(EMI_D00),
235
+
MXS_PINCTRL_PIN(EMI_D01),
236
+
MXS_PINCTRL_PIN(EMI_D02),
237
+
MXS_PINCTRL_PIN(EMI_D03),
238
+
MXS_PINCTRL_PIN(EMI_D04),
239
+
MXS_PINCTRL_PIN(EMI_D05),
240
+
MXS_PINCTRL_PIN(EMI_D06),
241
+
MXS_PINCTRL_PIN(EMI_D07),
242
+
MXS_PINCTRL_PIN(EMI_D08),
243
+
MXS_PINCTRL_PIN(EMI_D09),
244
+
MXS_PINCTRL_PIN(EMI_D10),
245
+
MXS_PINCTRL_PIN(EMI_D11),
246
+
MXS_PINCTRL_PIN(EMI_D12),
247
+
MXS_PINCTRL_PIN(EMI_D13),
248
+
MXS_PINCTRL_PIN(EMI_D14),
249
+
MXS_PINCTRL_PIN(EMI_D15),
250
+
MXS_PINCTRL_PIN(EMI_DQM0),
251
+
MXS_PINCTRL_PIN(EMI_DQM1),
252
+
MXS_PINCTRL_PIN(EMI_DQS0),
253
+
MXS_PINCTRL_PIN(EMI_DQS1),
254
+
MXS_PINCTRL_PIN(EMI_CLK),
255
+
MXS_PINCTRL_PIN(EMI_CLKN),
256
+
};
257
+
258
+
static struct mxs_regs imx23_regs = {
259
+
.muxsel = 0x100,
260
+
.drive = 0x200,
261
+
.pull = 0x400,
262
+
};
263
+
264
+
static struct mxs_pinctrl_soc_data imx23_pinctrl_data = {
265
+
.regs = &imx23_regs,
266
+
.pins = imx23_pins,
267
+
.npins = ARRAY_SIZE(imx23_pins),
268
+
};
269
+
270
+
static int __devinit imx23_pinctrl_probe(struct platform_device *pdev)
271
+
{
272
+
return mxs_pinctrl_probe(pdev, &imx23_pinctrl_data);
273
+
}
274
+
275
+
static struct of_device_id imx23_pinctrl_of_match[] __devinitdata = {
276
+
{ .compatible = "fsl,imx23-pinctrl", },
277
+
{ /* sentinel */ }
278
+
};
279
+
MODULE_DEVICE_TABLE(of, imx23_pinctrl_of_match);
280
+
281
+
static struct platform_driver imx23_pinctrl_driver = {
282
+
.driver = {
283
+
.name = "imx23-pinctrl",
284
+
.owner = THIS_MODULE,
285
+
.of_match_table = imx23_pinctrl_of_match,
286
+
},
287
+
.probe = imx23_pinctrl_probe,
288
+
.remove = __devexit_p(mxs_pinctrl_remove),
289
+
};
290
+
291
+
static int __init imx23_pinctrl_init(void)
292
+
{
293
+
return platform_driver_register(&imx23_pinctrl_driver);
294
+
}
295
+
arch_initcall(imx23_pinctrl_init);
296
+
297
+
static void __exit imx23_pinctrl_exit(void)
298
+
{
299
+
platform_driver_unregister(&imx23_pinctrl_driver);
300
+
}
301
+
module_exit(imx23_pinctrl_exit);
302
+
303
+
MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
304
+
MODULE_DESCRIPTION("Freescale i.MX23 pinctrl driver");
305
+
MODULE_LICENSE("GPL v2");
+421
drivers/pinctrl/pinctrl-imx28.c
+421
drivers/pinctrl/pinctrl-imx28.c
···
1
+
/*
2
+
* Copyright 2012 Freescale Semiconductor, Inc.
3
+
*
4
+
* The code contained herein is licensed under the GNU General Public
5
+
* License. You may obtain a copy of the GNU General Public License
6
+
* Version 2 or later at the following locations:
7
+
*
8
+
* http://www.opensource.org/licenses/gpl-license.html
9
+
* http://www.gnu.org/copyleft/gpl.html
10
+
*/
11
+
12
+
#include <linux/init.h>
13
+
#include <linux/module.h>
14
+
#include <linux/of_device.h>
15
+
#include <linux/pinctrl/pinctrl.h>
16
+
#include "pinctrl-mxs.h"
17
+
18
+
enum imx28_pin_enum {
19
+
GPMI_D00 = PINID(0, 0),
20
+
GPMI_D01 = PINID(0, 1),
21
+
GPMI_D02 = PINID(0, 2),
22
+
GPMI_D03 = PINID(0, 3),
23
+
GPMI_D04 = PINID(0, 4),
24
+
GPMI_D05 = PINID(0, 5),
25
+
GPMI_D06 = PINID(0, 6),
26
+
GPMI_D07 = PINID(0, 7),
27
+
GPMI_CE0N = PINID(0, 16),
28
+
GPMI_CE1N = PINID(0, 17),
29
+
GPMI_CE2N = PINID(0, 18),
30
+
GPMI_CE3N = PINID(0, 19),
31
+
GPMI_RDY0 = PINID(0, 20),
32
+
GPMI_RDY1 = PINID(0, 21),
33
+
GPMI_RDY2 = PINID(0, 22),
34
+
GPMI_RDY3 = PINID(0, 23),
35
+
GPMI_RDN = PINID(0, 24),
36
+
GPMI_WRN = PINID(0, 25),
37
+
GPMI_ALE = PINID(0, 26),
38
+
GPMI_CLE = PINID(0, 27),
39
+
GPMI_RESETN = PINID(0, 28),
40
+
LCD_D00 = PINID(1, 0),
41
+
LCD_D01 = PINID(1, 1),
42
+
LCD_D02 = PINID(1, 2),
43
+
LCD_D03 = PINID(1, 3),
44
+
LCD_D04 = PINID(1, 4),
45
+
LCD_D05 = PINID(1, 5),
46
+
LCD_D06 = PINID(1, 6),
47
+
LCD_D07 = PINID(1, 7),
48
+
LCD_D08 = PINID(1, 8),
49
+
LCD_D09 = PINID(1, 9),
50
+
LCD_D10 = PINID(1, 10),
51
+
LCD_D11 = PINID(1, 11),
52
+
LCD_D12 = PINID(1, 12),
53
+
LCD_D13 = PINID(1, 13),
54
+
LCD_D14 = PINID(1, 14),
55
+
LCD_D15 = PINID(1, 15),
56
+
LCD_D16 = PINID(1, 16),
57
+
LCD_D17 = PINID(1, 17),
58
+
LCD_D18 = PINID(1, 18),
59
+
LCD_D19 = PINID(1, 19),
60
+
LCD_D20 = PINID(1, 20),
61
+
LCD_D21 = PINID(1, 21),
62
+
LCD_D22 = PINID(1, 22),
63
+
LCD_D23 = PINID(1, 23),
64
+
LCD_RD_E = PINID(1, 24),
65
+
LCD_WR_RWN = PINID(1, 25),
66
+
LCD_RS = PINID(1, 26),
67
+
LCD_CS = PINID(1, 27),
68
+
LCD_VSYNC = PINID(1, 28),
69
+
LCD_HSYNC = PINID(1, 29),
70
+
LCD_DOTCLK = PINID(1, 30),
71
+
LCD_ENABLE = PINID(1, 31),
72
+
SSP0_DATA0 = PINID(2, 0),
73
+
SSP0_DATA1 = PINID(2, 1),
74
+
SSP0_DATA2 = PINID(2, 2),
75
+
SSP0_DATA3 = PINID(2, 3),
76
+
SSP0_DATA4 = PINID(2, 4),
77
+
SSP0_DATA5 = PINID(2, 5),
78
+
SSP0_DATA6 = PINID(2, 6),
79
+
SSP0_DATA7 = PINID(2, 7),
80
+
SSP0_CMD = PINID(2, 8),
81
+
SSP0_DETECT = PINID(2, 9),
82
+
SSP0_SCK = PINID(2, 10),
83
+
SSP1_SCK = PINID(2, 12),
84
+
SSP1_CMD = PINID(2, 13),
85
+
SSP1_DATA0 = PINID(2, 14),
86
+
SSP1_DATA3 = PINID(2, 15),
87
+
SSP2_SCK = PINID(2, 16),
88
+
SSP2_MOSI = PINID(2, 17),
89
+
SSP2_MISO = PINID(2, 18),
90
+
SSP2_SS0 = PINID(2, 19),
91
+
SSP2_SS1 = PINID(2, 20),
92
+
SSP2_SS2 = PINID(2, 21),
93
+
SSP3_SCK = PINID(2, 24),
94
+
SSP3_MOSI = PINID(2, 25),
95
+
SSP3_MISO = PINID(2, 26),
96
+
SSP3_SS0 = PINID(2, 27),
97
+
AUART0_RX = PINID(3, 0),
98
+
AUART0_TX = PINID(3, 1),
99
+
AUART0_CTS = PINID(3, 2),
100
+
AUART0_RTS = PINID(3, 3),
101
+
AUART1_RX = PINID(3, 4),
102
+
AUART1_TX = PINID(3, 5),
103
+
AUART1_CTS = PINID(3, 6),
104
+
AUART1_RTS = PINID(3, 7),
105
+
AUART2_RX = PINID(3, 8),
106
+
AUART2_TX = PINID(3, 9),
107
+
AUART2_CTS = PINID(3, 10),
108
+
AUART2_RTS = PINID(3, 11),
109
+
AUART3_RX = PINID(3, 12),
110
+
AUART3_TX = PINID(3, 13),
111
+
AUART3_CTS = PINID(3, 14),
112
+
AUART3_RTS = PINID(3, 15),
113
+
PWM0 = PINID(3, 16),
114
+
PWM1 = PINID(3, 17),
115
+
PWM2 = PINID(3, 18),
116
+
SAIF0_MCLK = PINID(3, 20),
117
+
SAIF0_LRCLK = PINID(3, 21),
118
+
SAIF0_BITCLK = PINID(3, 22),
119
+
SAIF0_SDATA0 = PINID(3, 23),
120
+
I2C0_SCL = PINID(3, 24),
121
+
I2C0_SDA = PINID(3, 25),
122
+
SAIF1_SDATA0 = PINID(3, 26),
123
+
SPDIF = PINID(3, 27),
124
+
PWM3 = PINID(3, 28),
125
+
PWM4 = PINID(3, 29),
126
+
LCD_RESET = PINID(3, 30),
127
+
ENET0_MDC = PINID(4, 0),
128
+
ENET0_MDIO = PINID(4, 1),
129
+
ENET0_RX_EN = PINID(4, 2),
130
+
ENET0_RXD0 = PINID(4, 3),
131
+
ENET0_RXD1 = PINID(4, 4),
132
+
ENET0_TX_CLK = PINID(4, 5),
133
+
ENET0_TX_EN = PINID(4, 6),
134
+
ENET0_TXD0 = PINID(4, 7),
135
+
ENET0_TXD1 = PINID(4, 8),
136
+
ENET0_RXD2 = PINID(4, 9),
137
+
ENET0_RXD3 = PINID(4, 10),
138
+
ENET0_TXD2 = PINID(4, 11),
139
+
ENET0_TXD3 = PINID(4, 12),
140
+
ENET0_RX_CLK = PINID(4, 13),
141
+
ENET0_COL = PINID(4, 14),
142
+
ENET0_CRS = PINID(4, 15),
143
+
ENET_CLK = PINID(4, 16),
144
+
JTAG_RTCK = PINID(4, 20),
145
+
EMI_D00 = PINID(5, 0),
146
+
EMI_D01 = PINID(5, 1),
147
+
EMI_D02 = PINID(5, 2),
148
+
EMI_D03 = PINID(5, 3),
149
+
EMI_D04 = PINID(5, 4),
150
+
EMI_D05 = PINID(5, 5),
151
+
EMI_D06 = PINID(5, 6),
152
+
EMI_D07 = PINID(5, 7),
153
+
EMI_D08 = PINID(5, 8),
154
+
EMI_D09 = PINID(5, 9),
155
+
EMI_D10 = PINID(5, 10),
156
+
EMI_D11 = PINID(5, 11),
157
+
EMI_D12 = PINID(5, 12),
158
+
EMI_D13 = PINID(5, 13),
159
+
EMI_D14 = PINID(5, 14),
160
+
EMI_D15 = PINID(5, 15),
161
+
EMI_ODT0 = PINID(5, 16),
162
+
EMI_DQM0 = PINID(5, 17),
163
+
EMI_ODT1 = PINID(5, 18),
164
+
EMI_DQM1 = PINID(5, 19),
165
+
EMI_DDR_OPEN_FB = PINID(5, 20),
166
+
EMI_CLK = PINID(5, 21),
167
+
EMI_DQS0 = PINID(5, 22),
168
+
EMI_DQS1 = PINID(5, 23),
169
+
EMI_DDR_OPEN = PINID(5, 26),
170
+
EMI_A00 = PINID(6, 0),
171
+
EMI_A01 = PINID(6, 1),
172
+
EMI_A02 = PINID(6, 2),
173
+
EMI_A03 = PINID(6, 3),
174
+
EMI_A04 = PINID(6, 4),
175
+
EMI_A05 = PINID(6, 5),
176
+
EMI_A06 = PINID(6, 6),
177
+
EMI_A07 = PINID(6, 7),
178
+
EMI_A08 = PINID(6, 8),
179
+
EMI_A09 = PINID(6, 9),
180
+
EMI_A10 = PINID(6, 10),
181
+
EMI_A11 = PINID(6, 11),
182
+
EMI_A12 = PINID(6, 12),
183
+
EMI_A13 = PINID(6, 13),
184
+
EMI_A14 = PINID(6, 14),
185
+
EMI_BA0 = PINID(6, 16),
186
+
EMI_BA1 = PINID(6, 17),
187
+
EMI_BA2 = PINID(6, 18),
188
+
EMI_CASN = PINID(6, 19),
189
+
EMI_RASN = PINID(6, 20),
190
+
EMI_WEN = PINID(6, 21),
191
+
EMI_CE0N = PINID(6, 22),
192
+
EMI_CE1N = PINID(6, 23),
193
+
EMI_CKE = PINID(6, 24),
194
+
};
195
+
196
+
static const struct pinctrl_pin_desc imx28_pins[] = {
197
+
MXS_PINCTRL_PIN(GPMI_D00),
198
+
MXS_PINCTRL_PIN(GPMI_D01),
199
+
MXS_PINCTRL_PIN(GPMI_D02),
200
+
MXS_PINCTRL_PIN(GPMI_D03),
201
+
MXS_PINCTRL_PIN(GPMI_D04),
202
+
MXS_PINCTRL_PIN(GPMI_D05),
203
+
MXS_PINCTRL_PIN(GPMI_D06),
204
+
MXS_PINCTRL_PIN(GPMI_D07),
205
+
MXS_PINCTRL_PIN(GPMI_CE0N),
206
+
MXS_PINCTRL_PIN(GPMI_CE1N),
207
+
MXS_PINCTRL_PIN(GPMI_CE2N),
208
+
MXS_PINCTRL_PIN(GPMI_CE3N),
209
+
MXS_PINCTRL_PIN(GPMI_RDY0),
210
+
MXS_PINCTRL_PIN(GPMI_RDY1),
211
+
MXS_PINCTRL_PIN(GPMI_RDY2),
212
+
MXS_PINCTRL_PIN(GPMI_RDY3),
213
+
MXS_PINCTRL_PIN(GPMI_RDN),
214
+
MXS_PINCTRL_PIN(GPMI_WRN),
215
+
MXS_PINCTRL_PIN(GPMI_ALE),
216
+
MXS_PINCTRL_PIN(GPMI_CLE),
217
+
MXS_PINCTRL_PIN(GPMI_RESETN),
218
+
MXS_PINCTRL_PIN(LCD_D00),
219
+
MXS_PINCTRL_PIN(LCD_D01),
220
+
MXS_PINCTRL_PIN(LCD_D02),
221
+
MXS_PINCTRL_PIN(LCD_D03),
222
+
MXS_PINCTRL_PIN(LCD_D04),
223
+
MXS_PINCTRL_PIN(LCD_D05),
224
+
MXS_PINCTRL_PIN(LCD_D06),
225
+
MXS_PINCTRL_PIN(LCD_D07),
226
+
MXS_PINCTRL_PIN(LCD_D08),
227
+
MXS_PINCTRL_PIN(LCD_D09),
228
+
MXS_PINCTRL_PIN(LCD_D10),
229
+
MXS_PINCTRL_PIN(LCD_D11),
230
+
MXS_PINCTRL_PIN(LCD_D12),
231
+
MXS_PINCTRL_PIN(LCD_D13),
232
+
MXS_PINCTRL_PIN(LCD_D14),
233
+
MXS_PINCTRL_PIN(LCD_D15),
234
+
MXS_PINCTRL_PIN(LCD_D16),
235
+
MXS_PINCTRL_PIN(LCD_D17),
236
+
MXS_PINCTRL_PIN(LCD_D18),
237
+
MXS_PINCTRL_PIN(LCD_D19),
238
+
MXS_PINCTRL_PIN(LCD_D20),
239
+
MXS_PINCTRL_PIN(LCD_D21),
240
+
MXS_PINCTRL_PIN(LCD_D22),
241
+
MXS_PINCTRL_PIN(LCD_D23),
242
+
MXS_PINCTRL_PIN(LCD_RD_E),
243
+
MXS_PINCTRL_PIN(LCD_WR_RWN),
244
+
MXS_PINCTRL_PIN(LCD_RS),
245
+
MXS_PINCTRL_PIN(LCD_CS),
246
+
MXS_PINCTRL_PIN(LCD_VSYNC),
247
+
MXS_PINCTRL_PIN(LCD_HSYNC),
248
+
MXS_PINCTRL_PIN(LCD_DOTCLK),
249
+
MXS_PINCTRL_PIN(LCD_ENABLE),
250
+
MXS_PINCTRL_PIN(SSP0_DATA0),
251
+
MXS_PINCTRL_PIN(SSP0_DATA1),
252
+
MXS_PINCTRL_PIN(SSP0_DATA2),
253
+
MXS_PINCTRL_PIN(SSP0_DATA3),
254
+
MXS_PINCTRL_PIN(SSP0_DATA4),
255
+
MXS_PINCTRL_PIN(SSP0_DATA5),
256
+
MXS_PINCTRL_PIN(SSP0_DATA6),
257
+
MXS_PINCTRL_PIN(SSP0_DATA7),
258
+
MXS_PINCTRL_PIN(SSP0_CMD),
259
+
MXS_PINCTRL_PIN(SSP0_DETECT),
260
+
MXS_PINCTRL_PIN(SSP0_SCK),
261
+
MXS_PINCTRL_PIN(SSP1_SCK),
262
+
MXS_PINCTRL_PIN(SSP1_CMD),
263
+
MXS_PINCTRL_PIN(SSP1_DATA0),
264
+
MXS_PINCTRL_PIN(SSP1_DATA3),
265
+
MXS_PINCTRL_PIN(SSP2_SCK),
266
+
MXS_PINCTRL_PIN(SSP2_MOSI),
267
+
MXS_PINCTRL_PIN(SSP2_MISO),
268
+
MXS_PINCTRL_PIN(SSP2_SS0),
269
+
MXS_PINCTRL_PIN(SSP2_SS1),
270
+
MXS_PINCTRL_PIN(SSP2_SS2),
271
+
MXS_PINCTRL_PIN(SSP3_SCK),
272
+
MXS_PINCTRL_PIN(SSP3_MOSI),
273
+
MXS_PINCTRL_PIN(SSP3_MISO),
274
+
MXS_PINCTRL_PIN(SSP3_SS0),
275
+
MXS_PINCTRL_PIN(AUART0_RX),
276
+
MXS_PINCTRL_PIN(AUART0_TX),
277
+
MXS_PINCTRL_PIN(AUART0_CTS),
278
+
MXS_PINCTRL_PIN(AUART0_RTS),
279
+
MXS_PINCTRL_PIN(AUART1_RX),
280
+
MXS_PINCTRL_PIN(AUART1_TX),
281
+
MXS_PINCTRL_PIN(AUART1_CTS),
282
+
MXS_PINCTRL_PIN(AUART1_RTS),
283
+
MXS_PINCTRL_PIN(AUART2_RX),
284
+
MXS_PINCTRL_PIN(AUART2_TX),
285
+
MXS_PINCTRL_PIN(AUART2_CTS),
286
+
MXS_PINCTRL_PIN(AUART2_RTS),
287
+
MXS_PINCTRL_PIN(AUART3_RX),
288
+
MXS_PINCTRL_PIN(AUART3_TX),
289
+
MXS_PINCTRL_PIN(AUART3_CTS),
290
+
MXS_PINCTRL_PIN(AUART3_RTS),
291
+
MXS_PINCTRL_PIN(PWM0),
292
+
MXS_PINCTRL_PIN(PWM1),
293
+
MXS_PINCTRL_PIN(PWM2),
294
+
MXS_PINCTRL_PIN(SAIF0_MCLK),
295
+
MXS_PINCTRL_PIN(SAIF0_LRCLK),
296
+
MXS_PINCTRL_PIN(SAIF0_BITCLK),
297
+
MXS_PINCTRL_PIN(SAIF0_SDATA0),
298
+
MXS_PINCTRL_PIN(I2C0_SCL),
299
+
MXS_PINCTRL_PIN(I2C0_SDA),
300
+
MXS_PINCTRL_PIN(SAIF1_SDATA0),
301
+
MXS_PINCTRL_PIN(SPDIF),
302
+
MXS_PINCTRL_PIN(PWM3),
303
+
MXS_PINCTRL_PIN(PWM4),
304
+
MXS_PINCTRL_PIN(LCD_RESET),
305
+
MXS_PINCTRL_PIN(ENET0_MDC),
306
+
MXS_PINCTRL_PIN(ENET0_MDIO),
307
+
MXS_PINCTRL_PIN(ENET0_RX_EN),
308
+
MXS_PINCTRL_PIN(ENET0_RXD0),
309
+
MXS_PINCTRL_PIN(ENET0_RXD1),
310
+
MXS_PINCTRL_PIN(ENET0_TX_CLK),
311
+
MXS_PINCTRL_PIN(ENET0_TX_EN),
312
+
MXS_PINCTRL_PIN(ENET0_TXD0),
313
+
MXS_PINCTRL_PIN(ENET0_TXD1),
314
+
MXS_PINCTRL_PIN(ENET0_RXD2),
315
+
MXS_PINCTRL_PIN(ENET0_RXD3),
316
+
MXS_PINCTRL_PIN(ENET0_TXD2),
317
+
MXS_PINCTRL_PIN(ENET0_TXD3),
318
+
MXS_PINCTRL_PIN(ENET0_RX_CLK),
319
+
MXS_PINCTRL_PIN(ENET0_COL),
320
+
MXS_PINCTRL_PIN(ENET0_CRS),
321
+
MXS_PINCTRL_PIN(ENET_CLK),
322
+
MXS_PINCTRL_PIN(JTAG_RTCK),
323
+
MXS_PINCTRL_PIN(EMI_D00),
324
+
MXS_PINCTRL_PIN(EMI_D01),
325
+
MXS_PINCTRL_PIN(EMI_D02),
326
+
MXS_PINCTRL_PIN(EMI_D03),
327
+
MXS_PINCTRL_PIN(EMI_D04),
328
+
MXS_PINCTRL_PIN(EMI_D05),
329
+
MXS_PINCTRL_PIN(EMI_D06),
330
+
MXS_PINCTRL_PIN(EMI_D07),
331
+
MXS_PINCTRL_PIN(EMI_D08),
332
+
MXS_PINCTRL_PIN(EMI_D09),
333
+
MXS_PINCTRL_PIN(EMI_D10),
334
+
MXS_PINCTRL_PIN(EMI_D11),
335
+
MXS_PINCTRL_PIN(EMI_D12),
336
+
MXS_PINCTRL_PIN(EMI_D13),
337
+
MXS_PINCTRL_PIN(EMI_D14),
338
+
MXS_PINCTRL_PIN(EMI_D15),
339
+
MXS_PINCTRL_PIN(EMI_ODT0),
340
+
MXS_PINCTRL_PIN(EMI_DQM0),
341
+
MXS_PINCTRL_PIN(EMI_ODT1),
342
+
MXS_PINCTRL_PIN(EMI_DQM1),
343
+
MXS_PINCTRL_PIN(EMI_DDR_OPEN_FB),
344
+
MXS_PINCTRL_PIN(EMI_CLK),
345
+
MXS_PINCTRL_PIN(EMI_DQS0),
346
+
MXS_PINCTRL_PIN(EMI_DQS1),
347
+
MXS_PINCTRL_PIN(EMI_DDR_OPEN),
348
+
MXS_PINCTRL_PIN(EMI_A00),
349
+
MXS_PINCTRL_PIN(EMI_A01),
350
+
MXS_PINCTRL_PIN(EMI_A02),
351
+
MXS_PINCTRL_PIN(EMI_A03),
352
+
MXS_PINCTRL_PIN(EMI_A04),
353
+
MXS_PINCTRL_PIN(EMI_A05),
354
+
MXS_PINCTRL_PIN(EMI_A06),
355
+
MXS_PINCTRL_PIN(EMI_A07),
356
+
MXS_PINCTRL_PIN(EMI_A08),
357
+
MXS_PINCTRL_PIN(EMI_A09),
358
+
MXS_PINCTRL_PIN(EMI_A10),
359
+
MXS_PINCTRL_PIN(EMI_A11),
360
+
MXS_PINCTRL_PIN(EMI_A12),
361
+
MXS_PINCTRL_PIN(EMI_A13),
362
+
MXS_PINCTRL_PIN(EMI_A14),
363
+
MXS_PINCTRL_PIN(EMI_BA0),
364
+
MXS_PINCTRL_PIN(EMI_BA1),
365
+
MXS_PINCTRL_PIN(EMI_BA2),
366
+
MXS_PINCTRL_PIN(EMI_CASN),
367
+
MXS_PINCTRL_PIN(EMI_RASN),
368
+
MXS_PINCTRL_PIN(EMI_WEN),
369
+
MXS_PINCTRL_PIN(EMI_CE0N),
370
+
MXS_PINCTRL_PIN(EMI_CE1N),
371
+
MXS_PINCTRL_PIN(EMI_CKE),
372
+
};
373
+
374
+
static struct mxs_regs imx28_regs = {
375
+
.muxsel = 0x100,
376
+
.drive = 0x300,
377
+
.pull = 0x600,
378
+
};
379
+
380
+
static struct mxs_pinctrl_soc_data imx28_pinctrl_data = {
381
+
.regs = &imx28_regs,
382
+
.pins = imx28_pins,
383
+
.npins = ARRAY_SIZE(imx28_pins),
384
+
};
385
+
386
+
static int __devinit imx28_pinctrl_probe(struct platform_device *pdev)
387
+
{
388
+
return mxs_pinctrl_probe(pdev, &imx28_pinctrl_data);
389
+
}
390
+
391
+
static struct of_device_id imx28_pinctrl_of_match[] __devinitdata = {
392
+
{ .compatible = "fsl,imx28-pinctrl", },
393
+
{ /* sentinel */ }
394
+
};
395
+
MODULE_DEVICE_TABLE(of, imx28_pinctrl_of_match);
396
+
397
+
static struct platform_driver imx28_pinctrl_driver = {
398
+
.driver = {
399
+
.name = "imx28-pinctrl",
400
+
.owner = THIS_MODULE,
401
+
.of_match_table = imx28_pinctrl_of_match,
402
+
},
403
+
.probe = imx28_pinctrl_probe,
404
+
.remove = __devexit_p(mxs_pinctrl_remove),
405
+
};
406
+
407
+
static int __init imx28_pinctrl_init(void)
408
+
{
409
+
return platform_driver_register(&imx28_pinctrl_driver);
410
+
}
411
+
arch_initcall(imx28_pinctrl_init);
412
+
413
+
static void __exit imx28_pinctrl_exit(void)
414
+
{
415
+
platform_driver_unregister(&imx28_pinctrl_driver);
416
+
}
417
+
module_exit(imx28_pinctrl_exit);
418
+
419
+
MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
420
+
MODULE_DESCRIPTION("Freescale i.MX28 pinctrl driver");
421
+
MODULE_LICENSE("GPL v2");
+2331
drivers/pinctrl/pinctrl-imx6q.c
+2331
drivers/pinctrl/pinctrl-imx6q.c
···
1
+
/*
2
+
* imx6q pinctrl driver based on imx pinmux core
3
+
*
4
+
* Copyright (C) 2012 Freescale Semiconductor, Inc.
5
+
* Copyright (C) 2012 Linaro, Inc.
6
+
*
7
+
* Author: Dong Aisheng <dong.aisheng@linaro.org>
8
+
*
9
+
* This program is free software; you can redistribute it and/or modify
10
+
* it under the terms of the GNU General Public License as published by
11
+
* the Free Software Foundation; either version 2 of the License, or
12
+
* (at your option) any later version.
13
+
*/
14
+
15
+
#include <linux/err.h>
16
+
#include <linux/init.h>
17
+
#include <linux/io.h>
18
+
#include <linux/module.h>
19
+
#include <linux/of.h>
20
+
#include <linux/of_device.h>
21
+
#include <linux/pinctrl/pinctrl.h>
22
+
23
+
#include "pinctrl-imx.h"
24
+
25
+
enum imx6q_pads {
26
+
MX6Q_PAD_SD2_DAT1 = 0,
27
+
MX6Q_PAD_SD2_DAT2 = 1,
28
+
MX6Q_PAD_SD2_DAT0 = 2,
29
+
MX6Q_PAD_RGMII_TXC = 3,
30
+
MX6Q_PAD_RGMII_TD0 = 4,
31
+
MX6Q_PAD_RGMII_TD1 = 5,
32
+
MX6Q_PAD_RGMII_TD2 = 6,
33
+
MX6Q_PAD_RGMII_TD3 = 7,
34
+
MX6Q_PAD_RGMII_RX_CTL = 8,
35
+
MX6Q_PAD_RGMII_RD0 = 9,
36
+
MX6Q_PAD_RGMII_TX_CTL = 10,
37
+
MX6Q_PAD_RGMII_RD1 = 11,
38
+
MX6Q_PAD_RGMII_RD2 = 12,
39
+
MX6Q_PAD_RGMII_RD3 = 13,
40
+
MX6Q_PAD_RGMII_RXC = 14,
41
+
MX6Q_PAD_EIM_A25 = 15,
42
+
MX6Q_PAD_EIM_EB2 = 16,
43
+
MX6Q_PAD_EIM_D16 = 17,
44
+
MX6Q_PAD_EIM_D17 = 18,
45
+
MX6Q_PAD_EIM_D18 = 19,
46
+
MX6Q_PAD_EIM_D19 = 20,
47
+
MX6Q_PAD_EIM_D20 = 21,
48
+
MX6Q_PAD_EIM_D21 = 22,
49
+
MX6Q_PAD_EIM_D22 = 23,
50
+
MX6Q_PAD_EIM_D23 = 24,
51
+
MX6Q_PAD_EIM_EB3 = 25,
52
+
MX6Q_PAD_EIM_D24 = 26,
53
+
MX6Q_PAD_EIM_D25 = 27,
54
+
MX6Q_PAD_EIM_D26 = 28,
55
+
MX6Q_PAD_EIM_D27 = 29,
56
+
MX6Q_PAD_EIM_D28 = 30,
57
+
MX6Q_PAD_EIM_D29 = 31,
58
+
MX6Q_PAD_EIM_D30 = 32,
59
+
MX6Q_PAD_EIM_D31 = 33,
60
+
MX6Q_PAD_EIM_A24 = 34,
61
+
MX6Q_PAD_EIM_A23 = 35,
62
+
MX6Q_PAD_EIM_A22 = 36,
63
+
MX6Q_PAD_EIM_A21 = 37,
64
+
MX6Q_PAD_EIM_A20 = 38,
65
+
MX6Q_PAD_EIM_A19 = 39,
66
+
MX6Q_PAD_EIM_A18 = 40,
67
+
MX6Q_PAD_EIM_A17 = 41,
68
+
MX6Q_PAD_EIM_A16 = 42,
69
+
MX6Q_PAD_EIM_CS0 = 43,
70
+
MX6Q_PAD_EIM_CS1 = 44,
71
+
MX6Q_PAD_EIM_OE = 45,
72
+
MX6Q_PAD_EIM_RW = 46,
73
+
MX6Q_PAD_EIM_LBA = 47,
74
+
MX6Q_PAD_EIM_EB0 = 48,
75
+
MX6Q_PAD_EIM_EB1 = 49,
76
+
MX6Q_PAD_EIM_DA0 = 50,
77
+
MX6Q_PAD_EIM_DA1 = 51,
78
+
MX6Q_PAD_EIM_DA2 = 52,
79
+
MX6Q_PAD_EIM_DA3 = 53,
80
+
MX6Q_PAD_EIM_DA4 = 54,
81
+
MX6Q_PAD_EIM_DA5 = 55,
82
+
MX6Q_PAD_EIM_DA6 = 56,
83
+
MX6Q_PAD_EIM_DA7 = 57,
84
+
MX6Q_PAD_EIM_DA8 = 58,
85
+
MX6Q_PAD_EIM_DA9 = 59,
86
+
MX6Q_PAD_EIM_DA10 = 60,
87
+
MX6Q_PAD_EIM_DA11 = 61,
88
+
MX6Q_PAD_EIM_DA12 = 62,
89
+
MX6Q_PAD_EIM_DA13 = 63,
90
+
MX6Q_PAD_EIM_DA14 = 64,
91
+
MX6Q_PAD_EIM_DA15 = 65,
92
+
MX6Q_PAD_EIM_WAIT = 66,
93
+
MX6Q_PAD_EIM_BCLK = 67,
94
+
MX6Q_PAD_DI0_DISP_CLK = 68,
95
+
MX6Q_PAD_DI0_PIN15 = 69,
96
+
MX6Q_PAD_DI0_PIN2 = 70,
97
+
MX6Q_PAD_DI0_PIN3 = 71,
98
+
MX6Q_PAD_DI0_PIN4 = 72,
99
+
MX6Q_PAD_DISP0_DAT0 = 73,
100
+
MX6Q_PAD_DISP0_DAT1 = 74,
101
+
MX6Q_PAD_DISP0_DAT2 = 75,
102
+
MX6Q_PAD_DISP0_DAT3 = 76,
103
+
MX6Q_PAD_DISP0_DAT4 = 77,
104
+
MX6Q_PAD_DISP0_DAT5 = 78,
105
+
MX6Q_PAD_DISP0_DAT6 = 79,
106
+
MX6Q_PAD_DISP0_DAT7 = 80,
107
+
MX6Q_PAD_DISP0_DAT8 = 81,
108
+
MX6Q_PAD_DISP0_DAT9 = 82,
109
+
MX6Q_PAD_DISP0_DAT10 = 83,
110
+
MX6Q_PAD_DISP0_DAT11 = 84,
111
+
MX6Q_PAD_DISP0_DAT12 = 85,
112
+
MX6Q_PAD_DISP0_DAT13 = 86,
113
+
MX6Q_PAD_DISP0_DAT14 = 87,
114
+
MX6Q_PAD_DISP0_DAT15 = 88,
115
+
MX6Q_PAD_DISP0_DAT16 = 89,
116
+
MX6Q_PAD_DISP0_DAT17 = 90,
117
+
MX6Q_PAD_DISP0_DAT18 = 91,
118
+
MX6Q_PAD_DISP0_DAT19 = 92,
119
+
MX6Q_PAD_DISP0_DAT20 = 93,
120
+
MX6Q_PAD_DISP0_DAT21 = 94,
121
+
MX6Q_PAD_DISP0_DAT22 = 95,
122
+
MX6Q_PAD_DISP0_DAT23 = 96,
123
+
MX6Q_PAD_ENET_MDIO = 97,
124
+
MX6Q_PAD_ENET_REF_CLK = 98,
125
+
MX6Q_PAD_ENET_RX_ER = 99,
126
+
MX6Q_PAD_ENET_CRS_DV = 100,
127
+
MX6Q_PAD_ENET_RXD1 = 101,
128
+
MX6Q_PAD_ENET_RXD0 = 102,
129
+
MX6Q_PAD_ENET_TX_EN = 103,
130
+
MX6Q_PAD_ENET_TXD1 = 104,
131
+
MX6Q_PAD_ENET_TXD0 = 105,
132
+
MX6Q_PAD_ENET_MDC = 106,
133
+
MX6Q_PAD_DRAM_D40 = 107,
134
+
MX6Q_PAD_DRAM_D41 = 108,
135
+
MX6Q_PAD_DRAM_D42 = 109,
136
+
MX6Q_PAD_DRAM_D43 = 110,
137
+
MX6Q_PAD_DRAM_D44 = 111,
138
+
MX6Q_PAD_DRAM_D45 = 112,
139
+
MX6Q_PAD_DRAM_D46 = 113,
140
+
MX6Q_PAD_DRAM_D47 = 114,
141
+
MX6Q_PAD_DRAM_SDQS5 = 115,
142
+
MX6Q_PAD_DRAM_DQM5 = 116,
143
+
MX6Q_PAD_DRAM_D32 = 117,
144
+
MX6Q_PAD_DRAM_D33 = 118,
145
+
MX6Q_PAD_DRAM_D34 = 119,
146
+
MX6Q_PAD_DRAM_D35 = 120,
147
+
MX6Q_PAD_DRAM_D36 = 121,
148
+
MX6Q_PAD_DRAM_D37 = 122,
149
+
MX6Q_PAD_DRAM_D38 = 123,
150
+
MX6Q_PAD_DRAM_D39 = 124,
151
+
MX6Q_PAD_DRAM_DQM4 = 125,
152
+
MX6Q_PAD_DRAM_SDQS4 = 126,
153
+
MX6Q_PAD_DRAM_D24 = 127,
154
+
MX6Q_PAD_DRAM_D25 = 128,
155
+
MX6Q_PAD_DRAM_D26 = 129,
156
+
MX6Q_PAD_DRAM_D27 = 130,
157
+
MX6Q_PAD_DRAM_D28 = 131,
158
+
MX6Q_PAD_DRAM_D29 = 132,
159
+
MX6Q_PAD_DRAM_SDQS3 = 133,
160
+
MX6Q_PAD_DRAM_D30 = 134,
161
+
MX6Q_PAD_DRAM_D31 = 135,
162
+
MX6Q_PAD_DRAM_DQM3 = 136,
163
+
MX6Q_PAD_DRAM_D16 = 137,
164
+
MX6Q_PAD_DRAM_D17 = 138,
165
+
MX6Q_PAD_DRAM_D18 = 139,
166
+
MX6Q_PAD_DRAM_D19 = 140,
167
+
MX6Q_PAD_DRAM_D20 = 141,
168
+
MX6Q_PAD_DRAM_D21 = 142,
169
+
MX6Q_PAD_DRAM_D22 = 143,
170
+
MX6Q_PAD_DRAM_SDQS2 = 144,
171
+
MX6Q_PAD_DRAM_D23 = 145,
172
+
MX6Q_PAD_DRAM_DQM2 = 146,
173
+
MX6Q_PAD_DRAM_A0 = 147,
174
+
MX6Q_PAD_DRAM_A1 = 148,
175
+
MX6Q_PAD_DRAM_A2 = 149,
176
+
MX6Q_PAD_DRAM_A3 = 150,
177
+
MX6Q_PAD_DRAM_A4 = 151,
178
+
MX6Q_PAD_DRAM_A5 = 152,
179
+
MX6Q_PAD_DRAM_A6 = 153,
180
+
MX6Q_PAD_DRAM_A7 = 154,
181
+
MX6Q_PAD_DRAM_A8 = 155,
182
+
MX6Q_PAD_DRAM_A9 = 156,
183
+
MX6Q_PAD_DRAM_A10 = 157,
184
+
MX6Q_PAD_DRAM_A11 = 158,
185
+
MX6Q_PAD_DRAM_A12 = 159,
186
+
MX6Q_PAD_DRAM_A13 = 160,
187
+
MX6Q_PAD_DRAM_A14 = 161,
188
+
MX6Q_PAD_DRAM_A15 = 162,
189
+
MX6Q_PAD_DRAM_CAS = 163,
190
+
MX6Q_PAD_DRAM_CS0 = 164,
191
+
MX6Q_PAD_DRAM_CS1 = 165,
192
+
MX6Q_PAD_DRAM_RAS = 166,
193
+
MX6Q_PAD_DRAM_RESET = 167,
194
+
MX6Q_PAD_DRAM_SDBA0 = 168,
195
+
MX6Q_PAD_DRAM_SDBA1 = 169,
196
+
MX6Q_PAD_DRAM_SDCLK_0 = 170,
197
+
MX6Q_PAD_DRAM_SDBA2 = 171,
198
+
MX6Q_PAD_DRAM_SDCKE0 = 172,
199
+
MX6Q_PAD_DRAM_SDCLK_1 = 173,
200
+
MX6Q_PAD_DRAM_SDCKE1 = 174,
201
+
MX6Q_PAD_DRAM_SDODT0 = 175,
202
+
MX6Q_PAD_DRAM_SDODT1 = 176,
203
+
MX6Q_PAD_DRAM_SDWE = 177,
204
+
MX6Q_PAD_DRAM_D0 = 178,
205
+
MX6Q_PAD_DRAM_D1 = 179,
206
+
MX6Q_PAD_DRAM_D2 = 180,
207
+
MX6Q_PAD_DRAM_D3 = 181,
208
+
MX6Q_PAD_DRAM_D4 = 182,
209
+
MX6Q_PAD_DRAM_D5 = 183,
210
+
MX6Q_PAD_DRAM_SDQS0 = 184,
211
+
MX6Q_PAD_DRAM_D6 = 185,
212
+
MX6Q_PAD_DRAM_D7 = 186,
213
+
MX6Q_PAD_DRAM_DQM0 = 187,
214
+
MX6Q_PAD_DRAM_D8 = 188,
215
+
MX6Q_PAD_DRAM_D9 = 189,
216
+
MX6Q_PAD_DRAM_D10 = 190,
217
+
MX6Q_PAD_DRAM_D11 = 191,
218
+
MX6Q_PAD_DRAM_D12 = 192,
219
+
MX6Q_PAD_DRAM_D13 = 193,
220
+
MX6Q_PAD_DRAM_D14 = 194,
221
+
MX6Q_PAD_DRAM_SDQS1 = 195,
222
+
MX6Q_PAD_DRAM_D15 = 196,
223
+
MX6Q_PAD_DRAM_DQM1 = 197,
224
+
MX6Q_PAD_DRAM_D48 = 198,
225
+
MX6Q_PAD_DRAM_D49 = 199,
226
+
MX6Q_PAD_DRAM_D50 = 200,
227
+
MX6Q_PAD_DRAM_D51 = 201,
228
+
MX6Q_PAD_DRAM_D52 = 202,
229
+
MX6Q_PAD_DRAM_D53 = 203,
230
+
MX6Q_PAD_DRAM_D54 = 204,
231
+
MX6Q_PAD_DRAM_D55 = 205,
232
+
MX6Q_PAD_DRAM_SDQS6 = 206,
233
+
MX6Q_PAD_DRAM_DQM6 = 207,
234
+
MX6Q_PAD_DRAM_D56 = 208,
235
+
MX6Q_PAD_DRAM_SDQS7 = 209,
236
+
MX6Q_PAD_DRAM_D57 = 210,
237
+
MX6Q_PAD_DRAM_D58 = 211,
238
+
MX6Q_PAD_DRAM_D59 = 212,
239
+
MX6Q_PAD_DRAM_D60 = 213,
240
+
MX6Q_PAD_DRAM_DQM7 = 214,
241
+
MX6Q_PAD_DRAM_D61 = 215,
242
+
MX6Q_PAD_DRAM_D62 = 216,
243
+
MX6Q_PAD_DRAM_D63 = 217,
244
+
MX6Q_PAD_KEY_COL0 = 218,
245
+
MX6Q_PAD_KEY_ROW0 = 219,
246
+
MX6Q_PAD_KEY_COL1 = 220,
247
+
MX6Q_PAD_KEY_ROW1 = 221,
248
+
MX6Q_PAD_KEY_COL2 = 222,
249
+
MX6Q_PAD_KEY_ROW2 = 223,
250
+
MX6Q_PAD_KEY_COL3 = 224,
251
+
MX6Q_PAD_KEY_ROW3 = 225,
252
+
MX6Q_PAD_KEY_COL4 = 226,
253
+
MX6Q_PAD_KEY_ROW4 = 227,
254
+
MX6Q_PAD_GPIO_0 = 228,
255
+
MX6Q_PAD_GPIO_1 = 229,
256
+
MX6Q_PAD_GPIO_9 = 230,
257
+
MX6Q_PAD_GPIO_3 = 231,
258
+
MX6Q_PAD_GPIO_6 = 232,
259
+
MX6Q_PAD_GPIO_2 = 233,
260
+
MX6Q_PAD_GPIO_4 = 234,
261
+
MX6Q_PAD_GPIO_5 = 235,
262
+
MX6Q_PAD_GPIO_7 = 236,
263
+
MX6Q_PAD_GPIO_8 = 237,
264
+
MX6Q_PAD_GPIO_16 = 238,
265
+
MX6Q_PAD_GPIO_17 = 239,
266
+
MX6Q_PAD_GPIO_18 = 240,
267
+
MX6Q_PAD_GPIO_19 = 241,
268
+
MX6Q_PAD_CSI0_PIXCLK = 242,
269
+
MX6Q_PAD_CSI0_MCLK = 243,
270
+
MX6Q_PAD_CSI0_DATA_EN = 244,
271
+
MX6Q_PAD_CSI0_VSYNC = 245,
272
+
MX6Q_PAD_CSI0_DAT4 = 246,
273
+
MX6Q_PAD_CSI0_DAT5 = 247,
274
+
MX6Q_PAD_CSI0_DAT6 = 248,
275
+
MX6Q_PAD_CSI0_DAT7 = 249,
276
+
MX6Q_PAD_CSI0_DAT8 = 250,
277
+
MX6Q_PAD_CSI0_DAT9 = 251,
278
+
MX6Q_PAD_CSI0_DAT10 = 252,
279
+
MX6Q_PAD_CSI0_DAT11 = 253,
280
+
MX6Q_PAD_CSI0_DAT12 = 254,
281
+
MX6Q_PAD_CSI0_DAT13 = 255,
282
+
MX6Q_PAD_CSI0_DAT14 = 256,
283
+
MX6Q_PAD_CSI0_DAT15 = 257,
284
+
MX6Q_PAD_CSI0_DAT16 = 258,
285
+
MX6Q_PAD_CSI0_DAT17 = 259,
286
+
MX6Q_PAD_CSI0_DAT18 = 260,
287
+
MX6Q_PAD_CSI0_DAT19 = 261,
288
+
MX6Q_PAD_JTAG_TMS = 262,
289
+
MX6Q_PAD_JTAG_MOD = 263,
290
+
MX6Q_PAD_JTAG_TRSTB = 264,
291
+
MX6Q_PAD_JTAG_TDI = 265,
292
+
MX6Q_PAD_JTAG_TCK = 266,
293
+
MX6Q_PAD_JTAG_TDO = 267,
294
+
MX6Q_PAD_LVDS1_TX3_P = 268,
295
+
MX6Q_PAD_LVDS1_TX2_P = 269,
296
+
MX6Q_PAD_LVDS1_CLK_P = 270,
297
+
MX6Q_PAD_LVDS1_TX1_P = 271,
298
+
MX6Q_PAD_LVDS1_TX0_P = 272,
299
+
MX6Q_PAD_LVDS0_TX3_P = 273,
300
+
MX6Q_PAD_LVDS0_CLK_P = 274,
301
+
MX6Q_PAD_LVDS0_TX2_P = 275,
302
+
MX6Q_PAD_LVDS0_TX1_P = 276,
303
+
MX6Q_PAD_LVDS0_TX0_P = 277,
304
+
MX6Q_PAD_TAMPER = 278,
305
+
MX6Q_PAD_PMIC_ON_REQ = 279,
306
+
MX6Q_PAD_PMIC_STBY_REQ = 280,
307
+
MX6Q_PAD_POR_B = 281,
308
+
MX6Q_PAD_BOOT_MODE1 = 282,
309
+
MX6Q_PAD_RESET_IN_B = 283,
310
+
MX6Q_PAD_BOOT_MODE0 = 284,
311
+
MX6Q_PAD_TEST_MODE = 285,
312
+
MX6Q_PAD_SD3_DAT7 = 286,
313
+
MX6Q_PAD_SD3_DAT6 = 287,
314
+
MX6Q_PAD_SD3_DAT5 = 288,
315
+
MX6Q_PAD_SD3_DAT4 = 289,
316
+
MX6Q_PAD_SD3_CMD = 290,
317
+
MX6Q_PAD_SD3_CLK = 291,
318
+
MX6Q_PAD_SD3_DAT0 = 292,
319
+
MX6Q_PAD_SD3_DAT1 = 293,
320
+
MX6Q_PAD_SD3_DAT2 = 294,
321
+
MX6Q_PAD_SD3_DAT3 = 295,
322
+
MX6Q_PAD_SD3_RST = 296,
323
+
MX6Q_PAD_NANDF_CLE = 297,
324
+
MX6Q_PAD_NANDF_ALE = 298,
325
+
MX6Q_PAD_NANDF_WP_B = 299,
326
+
MX6Q_PAD_NANDF_RB0 = 300,
327
+
MX6Q_PAD_NANDF_CS0 = 301,
328
+
MX6Q_PAD_NANDF_CS1 = 302,
329
+
MX6Q_PAD_NANDF_CS2 = 303,
330
+
MX6Q_PAD_NANDF_CS3 = 304,
331
+
MX6Q_PAD_SD4_CMD = 305,
332
+
MX6Q_PAD_SD4_CLK = 306,
333
+
MX6Q_PAD_NANDF_D0 = 307,
334
+
MX6Q_PAD_NANDF_D1 = 308,
335
+
MX6Q_PAD_NANDF_D2 = 309,
336
+
MX6Q_PAD_NANDF_D3 = 310,
337
+
MX6Q_PAD_NANDF_D4 = 311,
338
+
MX6Q_PAD_NANDF_D5 = 312,
339
+
MX6Q_PAD_NANDF_D6 = 313,
340
+
MX6Q_PAD_NANDF_D7 = 314,
341
+
MX6Q_PAD_SD4_DAT0 = 315,
342
+
MX6Q_PAD_SD4_DAT1 = 316,
343
+
MX6Q_PAD_SD4_DAT2 = 317,
344
+
MX6Q_PAD_SD4_DAT3 = 318,
345
+
MX6Q_PAD_SD4_DAT4 = 319,
346
+
MX6Q_PAD_SD4_DAT5 = 320,
347
+
MX6Q_PAD_SD4_DAT6 = 321,
348
+
MX6Q_PAD_SD4_DAT7 = 322,
349
+
MX6Q_PAD_SD1_DAT1 = 323,
350
+
MX6Q_PAD_SD1_DAT0 = 324,
351
+
MX6Q_PAD_SD1_DAT3 = 325,
352
+
MX6Q_PAD_SD1_CMD = 326,
353
+
MX6Q_PAD_SD1_DAT2 = 327,
354
+
MX6Q_PAD_SD1_CLK = 328,
355
+
MX6Q_PAD_SD2_CLK = 329,
356
+
MX6Q_PAD_SD2_CMD = 330,
357
+
MX6Q_PAD_SD2_DAT3 = 331,
358
+
};
359
+
360
+
/* imx6q register maps */
361
+
static struct imx_pin_reg imx6q_pin_regs[] = {
362
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
363
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 1, 0x0834, 0), /* MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 */
364
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 2, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 */
365
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 3, 0x07C8, 0), /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
366
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 4, 0x08F0, 0), /* MX6Q_PAD_SD2_DAT1__KPP_COL_7 */
367
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__GPIO_1_14 */
368
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__CCM_WAIT */
369
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0 */
370
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
371
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 1, 0x0838, 0), /* MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 */
372
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 2, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 */
373
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 3, 0x07B8, 0), /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
374
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 4, 0x08F8, 0), /* MX6Q_PAD_SD2_DAT2__KPP_ROW_6 */
375
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */
376
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__CCM_STOP */
377
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1 */
378
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
379
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 1, 0x082C, 0), /* MX6Q_PAD_SD2_DAT0__ECSPI5_MISO */
380
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 3, 0x07B4, 0), /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
381
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 4, 0x08FC, 0), /* MX6Q_PAD_SD2_DAT0__KPP_ROW_7 */
382
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__GPIO_1_15 */
383
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT */
384
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__TESTO_2 */
385
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA */
386
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
387
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 2, 0x0918, 0), /* MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK */
388
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__GPIO_6_19 */
389
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 */
390
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT */
391
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY */
392
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
393
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__GPIO_6_20 */
394
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 */
395
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG */
396
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
397
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__GPIO_6_21 */
398
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 */
399
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP */
400
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA */
401
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
402
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__GPIO_6_22 */
403
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 */
404
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP */
405
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK */
406
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
407
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__GPIO_6_23 */
408
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 */
409
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA */
410
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 1, 0x0858, 0), /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
411
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 */
412
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 */
413
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY */
414
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 1, 0x0848, 0), /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
415
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__GPIO_6_25 */
416
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 */
417
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE */
418
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
419
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 */
420
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 */
421
+
IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 7, 0x083C, 0), /* MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT */
422
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL */
423
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 1, 0x084C, 0), /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
424
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__GPIO_6_27 */
425
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 */
426
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__SJC_FAIL */
427
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA */
428
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 1, 0x0850, 0), /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
429
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__GPIO_6_28 */
430
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 */
431
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK */
432
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 1, 0x0854, 0), /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
433
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__GPIO_6_29 */
434
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 */
435
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE */
436
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 1, 0x0844, 0), /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
437
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__GPIO_6_30 */
438
+
IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 */
439
+
IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 */
440
+
IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A25__ECSPI4_SS1 */
441
+
IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 2, 0x0000, 0), /* MX6Q_PAD_EIM_A25__ECSPI2_RDY */
442
+
IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 */
443
+
IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS */
444
+
IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A25__GPIO_5_2 */
445
+
IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 6, 0x088C, 0), /* MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE */
446
+
IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0 */
447
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 */
448
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 1, 0x0800, 0), /* MX6Q_PAD_EIM_EB2__ECSPI1_SS0 */
449
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 2, 0x07EC, 0), /* MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK */
450
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 3, 0x08D4, 0), /* MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 */
451
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 4, 0x0890, 0), /* MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL */
452
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__GPIO_2_30 */
453
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 6, 0x08A0, 0), /* MX6Q_PAD_EIM_EB2__I2C2_SCL */
454
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 */
455
+
IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 */
456
+
IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 1, 0x07F4, 0), /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
457
+
IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 */
458
+
IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 3, 0x08D0, 0), /* MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 */
459
+
IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 4, 0x0894, 0), /* MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA */
460
+
IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D16__GPIO_3_16 */
461
+
IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 6, 0x08A4, 0), /* MX6Q_PAD_EIM_D16__I2C2_SDA */
462
+
IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 */
463
+
IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 1, 0x07F8, 0), /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
464
+
IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 */
465
+
IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 3, 0x08E0, 0), /* MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK */
466
+
IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT */
467
+
IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D17__GPIO_3_17 */
468
+
IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 6, 0x08A8, 0), /* MX6Q_PAD_EIM_D17__I2C3_SCL */
469
+
IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1 */
470
+
IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 */
471
+
IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 1, 0x07FC, 0), /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
472
+
IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 */
473
+
IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 3, 0x08CC, 0), /* MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 */
474
+
IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS */
475
+
IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D18__GPIO_3_18 */
476
+
IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 6, 0x08AC, 0), /* MX6Q_PAD_EIM_D18__I2C3_SDA */
477
+
IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2 */
478
+
IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 */
479
+
IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 1, 0x0804, 0), /* MX6Q_PAD_EIM_D19__ECSPI1_SS1 */
480
+
IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 */
481
+
IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 3, 0x08C8, 0), /* MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 */
482
+
IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 4, 0x091C, 0), /* MX6Q_PAD_EIM_D19__UART1_CTS */
483
+
IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
484
+
IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D19__EPIT1_EPITO */
485
+
IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D19__PL301_PER1_HRESP */
486
+
IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 */
487
+
IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 1, 0x0824, 0), /* MX6Q_PAD_EIM_D20__ECSPI4_SS0 */
488
+
IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 */
489
+
IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 3, 0x08C4, 0), /* MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 */
490
+
IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 4, 0x091C, 1), /* MX6Q_PAD_EIM_D20__UART1_RTS */
491
+
IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D20__GPIO_3_20 */
492
+
IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D20__EPIT2_EPITO */
493
+
IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 */
494
+
IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D21__ECSPI4_SCLK */
495
+
IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 */
496
+
IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 3, 0x08B4, 0), /* MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 */
497
+
IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 4, 0x0944, 0), /* MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC */
498
+
IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D21__GPIO_3_21 */
499
+
IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 6, 0x0898, 0), /* MX6Q_PAD_EIM_D21__I2C1_SCL */
500
+
IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 7, 0x0914, 0), /* MX6Q_PAD_EIM_D21__SPDIF_IN1 */
501
+
IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 */
502
+
IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D22__ECSPI4_MISO */
503
+
IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 */
504
+
IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 3, 0x08B0, 0), /* MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 */
505
+
IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR */
506
+
IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
507
+
IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D22__SPDIF_OUT1 */
508
+
IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D22__PL301_PER1_HWRITE */
509
+
IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 */
510
+
IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS */
511
+
IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 2, 0x092C, 0), /* MX6Q_PAD_EIM_D23__UART3_CTS */
512
+
IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D23__UART1_DCD */
513
+
IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 4, 0x08D8, 0), /* MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN */
514
+
IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
515
+
IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 */
516
+
IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 */
517
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 */
518
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__ECSPI4_RDY */
519
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 2, 0x092C, 1), /* MX6Q_PAD_EIM_EB3__UART3_RTS */
520
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__UART1_RI */
521
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 4, 0x08DC, 0), /* MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC */
522
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__GPIO_2_31 */
523
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 */
524
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 */
525
+
IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 */
526
+
IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D24__ECSPI4_SS2 */
527
+
IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D24__UART3_TXD */
528
+
IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 3, 0x0808, 0), /* MX6Q_PAD_EIM_D24__ECSPI1_SS2 */
529
+
IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D24__ECSPI2_SS2 */
530
+
IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D24__GPIO_3_24 */
531
+
IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 6, 0x07D8, 0), /* MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS */
532
+
IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D24__UART1_DTR */
533
+
IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 */
534
+
IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D25__ECSPI4_SS3 */
535
+
IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 2, 0x0930, 1), /* MX6Q_PAD_EIM_D25__UART3_RXD */
536
+
IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 3, 0x080C, 0), /* MX6Q_PAD_EIM_D25__ECSPI1_SS3 */
537
+
IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D25__ECSPI2_SS3 */
538
+
IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
539
+
IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 6, 0x07D4, 0), /* MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC */
540
+
IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D25__UART1_DSR */
541
+
IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 */
542
+
IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 */
543
+
IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 */
544
+
IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 3, 0x08C0, 0), /* MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 */
545
+
IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D26__UART2_TXD */
546
+
IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D26__GPIO_3_26 */
547
+
IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_SISG_2 */
548
+
IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 */
549
+
IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 */
550
+
IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 */
551
+
IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 */
552
+
IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 3, 0x08BC, 0), /* MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 */
553
+
IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 4, 0x0928, 1), /* MX6Q_PAD_EIM_D27__UART2_RXD */
554
+
IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D27__GPIO_3_27 */
555
+
IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_SISG_3 */
556
+
IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 */
557
+
IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 */
558
+
IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 1, 0x089C, 0), /* MX6Q_PAD_EIM_D28__I2C1_SDA */
559
+
IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D28__ECSPI4_MOSI */
560
+
IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 3, 0x08B8, 0), /* MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 */
561
+
IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 4, 0x0924, 0), /* MX6Q_PAD_EIM_D28__UART2_CTS */
562
+
IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D28__GPIO_3_28 */
563
+
IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG */
564
+
IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 */
565
+
IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 */
566
+
IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 */
567
+
IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 2, 0x0824, 1), /* MX6Q_PAD_EIM_D29__ECSPI4_SS0 */
568
+
IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 4, 0x0924, 1), /* MX6Q_PAD_EIM_D29__UART2_RTS */
569
+
IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D29__GPIO_3_29 */
570
+
IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 6, 0x08E4, 0), /* MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC */
571
+
IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 */
572
+
IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 */
573
+
IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 */
574
+
IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 */
575
+
IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 */
576
+
IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 4, 0x092C, 2), /* MX6Q_PAD_EIM_D30__UART3_CTS */
577
+
IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D30__GPIO_3_30 */
578
+
IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 6, 0x0948, 0), /* MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC */
579
+
IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D30__PL301_PER1_HPROT_0 */
580
+
IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 */
581
+
IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 */
582
+
IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 */
583
+
IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 */
584
+
IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 4, 0x092C, 3), /* MX6Q_PAD_EIM_D31__UART3_RTS */
585
+
IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D31__GPIO_3_31 */
586
+
IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR */
587
+
IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D31__PL301_PER1_HPROT_1 */
588
+
IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 */
589
+
IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 */
590
+
IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 2, 0x08D4, 1), /* MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 */
591
+
IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU2_SISG_2 */
592
+
IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU1_SISG_2 */
593
+
IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A24__GPIO_5_4 */
594
+
IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A24__PL301_PER1_HPROT_2 */
595
+
IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 */
596
+
IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 */
597
+
IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 */
598
+
IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 2, 0x08D0, 1), /* MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 */
599
+
IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU2_SISG_3 */
600
+
IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU1_SISG_3 */
601
+
IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A23__GPIO_6_6 */
602
+
IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A23__PL301_PER1_HPROT_3 */
603
+
IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 */
604
+
IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 */
605
+
IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 */
606
+
IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 2, 0x08CC, 1), /* MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 */
607
+
IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A22__GPIO_2_16 */
608
+
IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 */
609
+
IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 */
610
+
IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 */
611
+
IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 */
612
+
IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 2, 0x08C8, 1), /* MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 */
613
+
IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A21__RESERVED_RESERVED */
614
+
IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 */
615
+
IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A21__GPIO_2_17 */
616
+
IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 */
617
+
IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 */
618
+
IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 */
619
+
IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 */
620
+
IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 2, 0x08C4, 1), /* MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 */
621
+
IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A20__RESERVED_RESERVED */
622
+
IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 */
623
+
IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A20__GPIO_2_18 */
624
+
IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 */
625
+
IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 */
626
+
IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 */
627
+
IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 */
628
+
IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 2, 0x08C0, 1), /* MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 */
629
+
IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A19__RESERVED_RESERVED */
630
+
IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 */
631
+
IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A19__GPIO_2_19 */
632
+
IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 */
633
+
IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 */
634
+
IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 */
635
+
IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 */
636
+
IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 2, 0x08BC, 1), /* MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 */
637
+
IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A18__RESERVED_RESERVED */
638
+
IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 */
639
+
IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A18__GPIO_2_20 */
640
+
IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 */
641
+
IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 */
642
+
IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 */
643
+
IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 */
644
+
IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 2, 0x08B8, 1), /* MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 */
645
+
IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A17__RESERVED_RESERVED */
646
+
IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 */
647
+
IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A17__GPIO_2_21 */
648
+
IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 */
649
+
IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 */
650
+
IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 */
651
+
IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK */
652
+
IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 2, 0x08E0, 1), /* MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK */
653
+
IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 */
654
+
IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A16__GPIO_2_22 */
655
+
IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 */
656
+
IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 */
657
+
IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 */
658
+
IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 */
659
+
IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 2, 0x0810, 0), /* MX6Q_PAD_EIM_CS0__ECSPI2_SCLK */
660
+
IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 */
661
+
IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__GPIO_2_23 */
662
+
IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 */
663
+
IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 */
664
+
IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 */
665
+
IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 2, 0x0818, 0), /* MX6Q_PAD_EIM_CS1__ECSPI2_MOSI */
666
+
IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 */
667
+
IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__GPIO_2_24 */
668
+
IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 */
669
+
IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 0, 0x0000, 0), /* MX6Q_PAD_EIM_OE__WEIM_WEIM_OE */
670
+
IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 1, 0x0000, 0), /* MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 */
671
+
IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 2, 0x0814, 0), /* MX6Q_PAD_EIM_OE__ECSPI2_MISO */
672
+
IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 4, 0x0000, 0), /* MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 */
673
+
IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 5, 0x0000, 0), /* MX6Q_PAD_EIM_OE__GPIO_2_25 */
674
+
IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 6, 0x0000, 0), /* MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 */
675
+
IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 0, 0x0000, 0), /* MX6Q_PAD_EIM_RW__WEIM_WEIM_RW */
676
+
IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 1, 0x0000, 0), /* MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 */
677
+
IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 2, 0x081C, 0), /* MX6Q_PAD_EIM_RW__ECSPI2_SS0 */
678
+
IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 4, 0x0000, 0), /* MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 */
679
+
IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 5, 0x0000, 0), /* MX6Q_PAD_EIM_RW__GPIO_2_26 */
680
+
IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 6, 0x0000, 0), /* MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 */
681
+
IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 7, 0x0000, 0), /* MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 */
682
+
IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 0, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA */
683
+
IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 1, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 */
684
+
IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 2, 0x0820, 0), /* MX6Q_PAD_EIM_LBA__ECSPI2_SS1 */
685
+
IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 5, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__GPIO_2_27 */
686
+
IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 6, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 */
687
+
IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 7, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 */
688
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 */
689
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 */
690
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 2, 0x08B4, 1), /* MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 */
691
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 */
692
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 4, 0x07F0, 0), /* MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY */
693
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__GPIO_2_28 */
694
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 */
695
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 */
696
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 */
697
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 */
698
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 2, 0x08B0, 1), /* MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 */
699
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 */
700
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__GPIO_2_29 */
701
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 */
702
+
IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 */
703
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 */
704
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 */
705
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 */
706
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 */
707
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__GPIO_3_0 */
708
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 */
709
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 */
710
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 */
711
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 */
712
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 */
713
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 */
714
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__USBPHY1_TX_LS_MODE */
715
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__GPIO_3_1 */
716
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 */
717
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 */
718
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 */
719
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 */
720
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 */
721
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 */
722
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__USBPHY1_TX_HS_MODE */
723
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__GPIO_3_2 */
724
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 */
725
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 */
726
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 */
727
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 */
728
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 */
729
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 */
730
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__USBPHY1_TX_HIZ */
731
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__GPIO_3_3 */
732
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 */
733
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 */
734
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 */
735
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 */
736
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 */
737
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 */
738
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN */
739
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__GPIO_3_4 */
740
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 */
741
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 */
742
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 */
743
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 */
744
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 */
745
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 */
746
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP */
747
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__GPIO_3_5 */
748
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 */
749
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 */
750
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 */
751
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 */
752
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 */
753
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 */
754
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN */
755
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__GPIO_3_6 */
756
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 */
757
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 */
758
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 */
759
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 */
760
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 */
761
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 */
762
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__GPIO_3_7 */
763
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 */
764
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 */
765
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 */
766
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 */
767
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 */
768
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 */
769
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__GPIO_3_8 */
770
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 */
771
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 */
772
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 */
773
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 */
774
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 */
775
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 */
776
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__GPIO_3_9 */
777
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 */
778
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 */
779
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 */
780
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 */
781
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 2, 0x08D8, 1), /* MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN */
782
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 */
783
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__GPIO_3_10 */
784
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 */
785
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 */
786
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 */
787
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 */
788
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 2, 0x08DC, 1), /* MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC */
789
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 */
790
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 */
791
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__GPIO_3_11 */
792
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 */
793
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 */
794
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 */
795
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 */
796
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 2, 0x08E4, 1), /* MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC */
797
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 */
798
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 */
799
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__GPIO_3_12 */
800
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 */
801
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 */
802
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 */
803
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS */
804
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 2, 0x07EC, 1), /* MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK */
805
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 */
806
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 */
807
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__GPIO_3_13 */
808
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 */
809
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 */
810
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 */
811
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS */
812
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK */
813
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 */
814
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 */
815
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__GPIO_3_14 */
816
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 */
817
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 */
818
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 */
819
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 */
820
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 */
821
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 */
822
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__GPIO_3_15 */
823
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 */
824
+
IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 */
825
+
IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 0, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT */
826
+
IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 1, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B */
827
+
IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 5, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__GPIO_5_0 */
828
+
IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 6, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 */
829
+
IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 7, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 */
830
+
IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 0, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK */
831
+
IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 1, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 */
832
+
IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 5, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__GPIO_6_31 */
833
+
IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 6, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 */
834
+
IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 0, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DSP_CLK */
835
+
IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 1, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DSP_CLK */
836
+
IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 3, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 */
837
+
IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 4, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 */
838
+
IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 5, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 */
839
+
IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 6, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 */
840
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 */
841
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 */
842
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC */
843
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 */
844
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 */
845
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__GPIO_4_17 */
846
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 */
847
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 */
848
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 */
849
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD */
850
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 */
851
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 */
852
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__GPIO_4_18 */
853
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2 */
854
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9 */
855
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 */
856
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 */
857
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS */
858
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 */
859
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 */
860
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__GPIO_4_19 */
861
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 */
862
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__PL301_PER1_HADDR_10 */
863
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 */
864
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 */
865
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD */
866
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 3, 0x094C, 0), /* MX6Q_PAD_DI0_PIN4__USDHC1_WP */
867
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD */
868
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__GPIO_4_20 */
869
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 */
870
+
IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11 */
871
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 */
872
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 */
873
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK */
874
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 */
875
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN */
876
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__GPIO_4_21 */
877
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 */
878
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 */
879
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 */
880
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI */
881
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 */
882
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL */
883
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__GPIO_4_22 */
884
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6 */
885
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12 */
886
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 */
887
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 */
888
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO */
889
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 */
890
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE */
891
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__GPIO_4_23 */
892
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7 */
893
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13 */
894
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 */
895
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 */
896
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 */
897
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 */
898
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR */
899
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__GPIO_4_24 */
900
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 */
901
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14 */
902
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 */
903
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 */
904
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 */
905
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 */
906
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB */
907
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__GPIO_4_25 */
908
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 */
909
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15 */
910
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 */
911
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 */
912
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 */
913
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS */
914
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS */
915
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__GPIO_4_26 */
916
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10 */
917
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16 */
918
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 */
919
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 */
920
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 */
921
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC */
922
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT */
923
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__GPIO_4_27 */
924
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11 */
925
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17 */
926
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 */
927
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 */
928
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY */
929
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 */
930
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 */
931
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__GPIO_4_28 */
932
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12 */
933
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18 */
934
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 */
935
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 */
936
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__PWM1_PWMO */
937
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B */
938
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 */
939
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__GPIO_4_29 */
940
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13 */
941
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19 */
942
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 */
943
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 */
944
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__PWM2_PWMO */
945
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B */
946
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 */
947
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__GPIO_4_30 */
948
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14 */
949
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20 */
950
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 */
951
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 */
952
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6 */
953
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 */
954
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__GPIO_4_31 */
955
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15 */
956
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21 */
957
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 */
958
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 */
959
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 */
960
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 */
961
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__GPIO_5_5 */
962
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16 */
963
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22 */
964
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 */
965
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 */
966
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED */
967
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 */
968
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__GPIO_5_6 */
969
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17 */
970
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23 */
971
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 */
972
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 */
973
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 3, 0x07D8, 1), /* MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS */
974
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 */
975
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__GPIO_5_7 */
976
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18 */
977
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24 */
978
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 */
979
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 */
980
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 3, 0x07D4, 1), /* MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC */
981
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 */
982
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__GPIO_5_8 */
983
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19 */
984
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 */
985
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 */
986
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 2, 0x0804, 1), /* MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 */
987
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 3, 0x0820, 1), /* MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 */
988
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 */
989
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__GPIO_5_9 */
990
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20 */
991
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25 */
992
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 */
993
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 */
994
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 2, 0x0818, 1), /* MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI */
995
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 3, 0x07DC, 0), /* MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC */
996
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 4, 0x090C, 0), /* MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 */
997
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__GPIO_5_10 */
998
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21 */
999
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26 */
1000
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 */
1001
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 */
1002
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 2, 0x0814, 1), /* MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO */
1003
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 3, 0x07D0, 0), /* MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD */
1004
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 4, 0x0910, 0), /* MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 */
1005
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__GPIO_5_11 */
1006
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22 */
1007
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27 */
1008
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 */
1009
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 */
1010
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 2, 0x081C, 1), /* MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 */
1011
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 3, 0x07E0, 0), /* MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS */
1012
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 4, 0x07C0, 0), /* MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS */
1013
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__GPIO_5_12 */
1014
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23 */
1015
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 */
1016
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 */
1017
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 */
1018
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 2, 0x0810, 1), /* MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK */
1019
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 3, 0x07CC, 0), /* MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD */
1020
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 4, 0x07BC, 0), /* MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC */
1021
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__GPIO_5_13 */
1022
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24 */
1023
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 */
1024
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 */
1025
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 */
1026
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 2, 0x07F4, 1), /* MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK */
1027
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 3, 0x07C4, 0), /* MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC */
1028
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 */
1029
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__GPIO_5_14 */
1030
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25 */
1031
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28 */
1032
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 */
1033
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 */
1034
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 2, 0x07FC, 1), /* MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI */
1035
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 3, 0x07B8, 1), /* MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD */
1036
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 */
1037
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__GPIO_5_15 */
1038
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26 */
1039
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29 */
1040
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 */
1041
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 */
1042
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 2, 0x07F8, 1), /* MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO */
1043
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 3, 0x07C8, 1), /* MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS */
1044
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 */
1045
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__GPIO_5_16 */
1046
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27 */
1047
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30 */
1048
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 */
1049
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 */
1050
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 2, 0x0800, 1), /* MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 */
1051
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 3, 0x07B4, 1), /* MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD */
1052
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 */
1053
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__GPIO_5_17 */
1054
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__MMDC_DEBUG_28 */
1055
+
IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__PL301_PER1_HADR31 */
1056
+
IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 0, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED */
1057
+
IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 1, 0x0840, 0), /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
1058
+
IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 2, 0x086C, 0), /* MX6Q_PAD_ENET_MDIO__ESAI1_SCKR */
1059
+
IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 3, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 */
1060
+
IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 4, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__ENET_1588_EVT1_OUT */
1061
+
IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__GPIO_1_22 */
1062
+
IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK */
1063
+
IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 0, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__RESERVED_RSRVED */
1064
+
IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 1, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
1065
+
IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 2, 0x085C, 0), /* MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR */
1066
+
IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 3, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 */
1067
+
IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 */
1068
+
IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK */
1069
+
IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__USBPHY1_RX_SQH */
1070
+
IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 1, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__ENET_RX_ER */
1071
+
IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 2, 0x0864, 0), /* MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR */
1072
+
IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 3, 0x0914, 1), /* MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 */
1073
+
IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 4, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT */
1074
+
IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__GPIO_1_24 */
1075
+
IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__PHY_TDI */
1076
+
IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD */
1077
+
IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 0, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__RESERVED_RSRVED */
1078
+
IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 1, 0x0858, 1), /* MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN */
1079
+
IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 2, 0x0870, 0), /* MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT */
1080
+
IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 3, 0x0918, 1), /* MX6Q_PAD_ENET_CRS_DV__SPDIF_EXTCLK */
1081
+
IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 5, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 */
1082
+
IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 6, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__PHY_TDO */
1083
+
IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 7, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD */
1084
+
IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 0, 0x0908, 0), /* MX6Q_PAD_ENET_RXD1__MLB_MLBSIG */
1085
+
IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 1, 0x084C, 1), /* MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 */
1086
+
IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 2, 0x0860, 0), /* MX6Q_PAD_ENET_RXD1__ESAI1_FST */
1087
+
IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 4, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__ENET_1588_EVT3_OUT */
1088
+
IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__GPIO_1_26 */
1089
+
IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__PHY_TCK */
1090
+
IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__USBPHY1_RX_DISCON */
1091
+
IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 0, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT */
1092
+
IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 1, 0x0848, 1), /* MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 */
1093
+
IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 2, 0x0868, 0), /* MX6Q_PAD_ENET_RXD0__ESAI1_HCKT */
1094
+
IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 3, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 */
1095
+
IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__GPIO_1_27 */
1096
+
IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__PHY_TMS */
1097
+
IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV */
1098
+
IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 0, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__RESERVED_RSRVED */
1099
+
IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__ENET_TX_EN */
1100
+
IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 2, 0x0880, 0), /* MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 */
1101
+
IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__GPIO_1_28 */
1102
+
IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI */
1103
+
IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__USBPHY2_RX_SQH */
1104
+
IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 0, 0x0900, 0), /* MX6Q_PAD_ENET_TXD1__MLB_MLBCLK */
1105
+
IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 */
1106
+
IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 2, 0x087C, 0), /* MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 */
1107
+
IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 4, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN */
1108
+
IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__GPIO_1_29 */
1109
+
IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO */
1110
+
IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD */
1111
+
IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 0, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__RESERVED_RSRVED */
1112
+
IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 */
1113
+
IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 2, 0x0884, 0), /* MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 */
1114
+
IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__GPIO_1_30 */
1115
+
IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK */
1116
+
IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD */
1117
+
IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 0, 0x0904, 0), /* MX6Q_PAD_ENET_MDC__MLB_MLBDAT */
1118
+
IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 1, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__ENET_MDC */
1119
+
IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 2, 0x0888, 0), /* MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 */
1120
+
IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 4, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN */
1121
+
IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__GPIO_1_31 */
1122
+
IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__SATA_PHY_TMS */
1123
+
IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__USBPHY2_RX_DISCON */
1124
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D40, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 */
1125
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D41, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 */
1126
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D42, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 */
1127
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D43, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 */
1128
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D44, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 */
1129
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D45, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 */
1130
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D46, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 */
1131
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D47, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 */
1132
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS5, 0x050C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 */
1133
+
IMX_PIN_REG(MX6Q_PAD_DRAM_DQM5, 0x0510, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 */
1134
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D32, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 */
1135
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D33, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 */
1136
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D34, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 */
1137
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D35, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 */
1138
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D36, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 */
1139
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D37, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 */
1140
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D38, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 */
1141
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D39, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 */
1142
+
IMX_PIN_REG(MX6Q_PAD_DRAM_DQM4, 0x0514, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 */
1143
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS4, 0x0518, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 */
1144
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D24, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 */
1145
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D25, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 */
1146
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D26, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 */
1147
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D27, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 */
1148
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D28, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 */
1149
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D29, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 */
1150
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS3, 0x051C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 */
1151
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D30, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 */
1152
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D31, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 */
1153
+
IMX_PIN_REG(MX6Q_PAD_DRAM_DQM3, 0x0520, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 */
1154
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D16, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 */
1155
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D17, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 */
1156
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D18, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 */
1157
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D19, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 */
1158
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D20, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 */
1159
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D21, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 */
1160
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D22, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 */
1161
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS2, 0x0524, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 */
1162
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D23, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 */
1163
+
IMX_PIN_REG(MX6Q_PAD_DRAM_DQM2, 0x0528, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 */
1164
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A0, 0x052C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 */
1165
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A1, 0x0530, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 */
1166
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A2, 0x0534, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 */
1167
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A3, 0x0538, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 */
1168
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A4, 0x053C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 */
1169
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A5, 0x0540, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 */
1170
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A6, 0x0544, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 */
1171
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A7, 0x0548, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 */
1172
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A8, 0x054C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 */
1173
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A9, 0x0550, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 */
1174
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A10, 0x0554, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 */
1175
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A11, 0x0558, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 */
1176
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A12, 0x055C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 */
1177
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A13, 0x0560, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 */
1178
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A14, 0x0564, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 */
1179
+
IMX_PIN_REG(MX6Q_PAD_DRAM_A15, 0x0568, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 */
1180
+
IMX_PIN_REG(MX6Q_PAD_DRAM_CAS, 0x056C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS */
1181
+
IMX_PIN_REG(MX6Q_PAD_DRAM_CS0, 0x0570, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 */
1182
+
IMX_PIN_REG(MX6Q_PAD_DRAM_CS1, 0x0574, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 */
1183
+
IMX_PIN_REG(MX6Q_PAD_DRAM_RAS, 0x0578, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS */
1184
+
IMX_PIN_REG(MX6Q_PAD_DRAM_RESET, 0x057C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET */
1185
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA0, 0x0580, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 */
1186
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA1, 0x0584, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 */
1187
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDCLK_0, 0x0588, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 */
1188
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA2, 0x058C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 */
1189
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDCKE0, 0x0590, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 */
1190
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDCLK_1, 0x0594, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 */
1191
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDCKE1, 0x0598, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 */
1192
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDODT0, 0x059C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 */
1193
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDODT1, 0x05A0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 */
1194
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDWE, 0x05A4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE */
1195
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D0, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 */
1196
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D1, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 */
1197
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D2, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 */
1198
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D3, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 */
1199
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D4, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 */
1200
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D5, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 */
1201
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS0, 0x05A8, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 */
1202
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D6, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 */
1203
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D7, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 */
1204
+
IMX_PIN_REG(MX6Q_PAD_DRAM_DQM0, 0x05AC, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 */
1205
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D8, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 */
1206
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D9, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 */
1207
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D10, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 */
1208
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D11, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 */
1209
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D12, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 */
1210
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D13, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 */
1211
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D14, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 */
1212
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS1, 0x05B0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 */
1213
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D15, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 */
1214
+
IMX_PIN_REG(MX6Q_PAD_DRAM_DQM1, 0x05B4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 */
1215
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D48, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 */
1216
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D49, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 */
1217
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D50, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 */
1218
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D51, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 */
1219
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D52, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 */
1220
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D53, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 */
1221
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D54, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 */
1222
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D55, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 */
1223
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS6, 0x05B8, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 */
1224
+
IMX_PIN_REG(MX6Q_PAD_DRAM_DQM6, 0x05BC, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 */
1225
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D56, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 */
1226
+
IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS7, 0x05C0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 */
1227
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D57, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 */
1228
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D58, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 */
1229
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D59, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 */
1230
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D60, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 */
1231
+
IMX_PIN_REG(MX6Q_PAD_DRAM_DQM7, 0x05C4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 */
1232
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D61, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 */
1233
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D62, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 */
1234
+
IMX_PIN_REG(MX6Q_PAD_DRAM_D63, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 */
1235
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 0, 0x07F4, 2), /* MX6Q_PAD_KEY_COL0__ECSPI1_SCLK */
1236
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 1, 0x0854, 1), /* MX6Q_PAD_KEY_COL0__ENET_RDATA_3 */
1237
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 2, 0x07DC, 1), /* MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
1238
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__KPP_COL_0 */
1239
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__UART4_TXD */
1240
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__GPIO_4_6 */
1241
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT */
1242
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST */
1243
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 0, 0x07FC, 2), /* MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI */
1244
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 */
1245
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 2, 0x07D0, 1), /* MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
1246
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__KPP_ROW_0 */
1247
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 4, 0x0938, 1), /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
1248
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__GPIO_4_7 */
1249
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT */
1250
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__PL301_PER1_HADR_0 */
1251
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 0, 0x07F8, 2), /* MX6Q_PAD_KEY_COL1__ECSPI1_MISO */
1252
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 1, 0x0840, 1), /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
1253
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 2, 0x07E0, 1), /* MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
1254
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__KPP_COL_1 */
1255
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__UART5_TXD */
1256
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__GPIO_4_8 */
1257
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__USDHC1_VSELECT */
1258
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1 */
1259
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 0, 0x0800, 2), /* MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 */
1260
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__ENET_COL */
1261
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 2, 0x07CC, 1), /* MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
1262
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__KPP_ROW_1 */
1263
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 4, 0x0940, 1), /* MX6Q_PAD_KEY_ROW1__UART5_RXD */
1264
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__GPIO_4_9 */
1265
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT */
1266
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__PL301_PER1_HADDR_2 */
1267
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 0, 0x0804, 2), /* MX6Q_PAD_KEY_COL2__ECSPI1_SS1 */
1268
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 1, 0x0850, 1), /* MX6Q_PAD_KEY_COL2__ENET_RDATA_2 */
1269
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 2, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__CAN1_TXCAN */
1270
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__KPP_COL_2 */
1271
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__ENET_MDC */
1272
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__GPIO_4_10 */
1273
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP */
1274
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__PL301_PER1_HADDR_3 */
1275
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 0, 0x0808, 1), /* MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 */
1276
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 */
1277
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 2, 0x07E4, 0), /* MX6Q_PAD_KEY_ROW2__CAN1_RXCAN */
1278
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__KPP_ROW_2 */
1279
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 4, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT */
1280
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__GPIO_4_11 */
1281
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 6, 0x088C, 1), /* MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE */
1282
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__PL301_PER1_HADR_4 */
1283
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 0, 0x080C, 1), /* MX6Q_PAD_KEY_COL3__ECSPI1_SS3 */
1284
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 1, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__ENET_CRS */
1285
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 2, 0x0890, 1), /* MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL */
1286
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__KPP_COL_3 */
1287
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 4, 0x08A0, 1), /* MX6Q_PAD_KEY_COL3__I2C2_SCL */
1288
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__GPIO_4_12 */
1289
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 6, 0x0914, 2), /* MX6Q_PAD_KEY_COL3__SPDIF_IN1 */
1290
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__PL301_PER1_HADR_5 */
1291
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 0, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT */
1292
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 1, 0x07B0, 0), /* MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK */
1293
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 2, 0x0894, 1), /* MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA */
1294
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__KPP_ROW_3 */
1295
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 4, 0x08A4, 1), /* MX6Q_PAD_KEY_ROW3__I2C2_SDA */
1296
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__GPIO_4_13 */
1297
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT */
1298
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__PL301_PER1_HADR_6 */
1299
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 0, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__CAN2_TXCAN */
1300
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 1, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__IPU1_SISG_4 */
1301
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 2, 0x0944, 1), /* MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC */
1302
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__KPP_COL_4 */
1303
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 4, 0x093C, 0), /* MX6Q_PAD_KEY_COL4__UART5_RTS */
1304
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__GPIO_4_14 */
1305
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__MMDC_DEBUG_49 */
1306
+
IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__PL301_PER1_HADDR_7 */
1307
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 0, 0x07E8, 0), /* MX6Q_PAD_KEY_ROW4__CAN2_RXCAN */
1308
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 */
1309
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 2, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR */
1310
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__KPP_ROW_4 */
1311
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 4, 0x093C, 1), /* MX6Q_PAD_KEY_ROW4__UART5_CTS */
1312
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__GPIO_4_15 */
1313
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__MMDC_DEBUG_50 */
1314
+
IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__PL301_PER1_HADR_8 */
1315
+
IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 0, 0x0000, 0), /* MX6Q_PAD_GPIO_0__CCM_CLKO */
1316
+
IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 2, 0x08E8, 0), /* MX6Q_PAD_GPIO_0__KPP_COL_5 */
1317
+
IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 3, 0x07B0, 1), /* MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK */
1318
+
IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_0__EPIT1_EPITO */
1319
+
IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_0__GPIO_1_0 */
1320
+
IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR */
1321
+
IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 */
1322
+
IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 0, 0x086C, 1), /* MX6Q_PAD_GPIO_1__ESAI1_SCKR */
1323
+
IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_1__WDOG2_WDOG_B */
1324
+
IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 2, 0x08F4, 0), /* MX6Q_PAD_GPIO_1__KPP_ROW_5 */
1325
+
IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_1__PWM2_PWMO */
1326
+
IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_1__GPIO_1_1 */
1327
+
IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_1__USDHC1_CD */
1328
+
IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_1__SRC_TESTER_ACK */
1329
+
IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 0, 0x085C, 1), /* MX6Q_PAD_GPIO_9__ESAI1_FSR */
1330
+
IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_9__WDOG1_WDOG_B */
1331
+
IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 2, 0x08EC, 0), /* MX6Q_PAD_GPIO_9__KPP_COL_6 */
1332
+
IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_9__CCM_REF_EN_B */
1333
+
IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_9__PWM1_PWMO */
1334
+
IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_9__GPIO_1_9 */
1335
+
IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 6, 0x094C, 1), /* MX6Q_PAD_GPIO_9__USDHC1_WP */
1336
+
IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_9__SRC_EARLY_RST */
1337
+
IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 0, 0x0864, 1), /* MX6Q_PAD_GPIO_3__ESAI1_HCKR */
1338
+
IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 */
1339
+
IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 2, 0x08A8, 1), /* MX6Q_PAD_GPIO_3__I2C3_SCL */
1340
+
IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_3__ANATOP_24M_OUT */
1341
+
IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_3__CCM_CLKO2 */
1342
+
IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_3__GPIO_1_3 */
1343
+
IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 6, 0x0948, 1), /* MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC */
1344
+
IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 7, 0x0900, 1), /* MX6Q_PAD_GPIO_3__MLB_MLBCLK */
1345
+
IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 0, 0x0870, 1), /* MX6Q_PAD_GPIO_6__ESAI1_SCKT */
1346
+
IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 */
1347
+
IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 2, 0x08AC, 1), /* MX6Q_PAD_GPIO_6__I2C3_SDA */
1348
+
IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 */
1349
+
IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB */
1350
+
IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_6__GPIO_1_6 */
1351
+
IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_6__USDHC2_LCTL */
1352
+
IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 7, 0x0908, 1), /* MX6Q_PAD_GPIO_6__MLB_MLBSIG */
1353
+
IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 0, 0x0860, 1), /* MX6Q_PAD_GPIO_2__ESAI1_FST */
1354
+
IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 */
1355
+
IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 2, 0x08F8, 1), /* MX6Q_PAD_GPIO_2__KPP_ROW_6 */
1356
+
IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 */
1357
+
IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 */
1358
+
IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_2__GPIO_1_2 */
1359
+
IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_2__USDHC2_WP */
1360
+
IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 7, 0x0904, 1), /* MX6Q_PAD_GPIO_2__MLB_MLBDAT */
1361
+
IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 0, 0x0868, 1), /* MX6Q_PAD_GPIO_4__ESAI1_HCKT */
1362
+
IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 */
1363
+
IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 2, 0x08F0, 1), /* MX6Q_PAD_GPIO_4__KPP_COL_7 */
1364
+
IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 */
1365
+
IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 */
1366
+
IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_4__GPIO_1_4 */
1367
+
IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_4__USDHC2_CD */
1368
+
IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA */
1369
+
IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 0, 0x087C, 1), /* MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 */
1370
+
IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 */
1371
+
IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 2, 0x08FC, 1), /* MX6Q_PAD_GPIO_5__KPP_ROW_7 */
1372
+
IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CCM_CLKO */
1373
+
IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 */
1374
+
IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_5__GPIO_1_5 */
1375
+
IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 6, 0x08A8, 2), /* MX6Q_PAD_GPIO_5__I2C3_SCL */
1376
+
IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CHEETAH_EVENTI */
1377
+
IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 0, 0x0884, 1), /* MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 */
1378
+
IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_7__ECSPI5_RDY */
1379
+
IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_7__EPIT1_EPITO */
1380
+
IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_7__CAN1_TXCAN */
1381
+
IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_7__UART2_TXD */
1382
+
IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_7__GPIO_1_7 */
1383
+
IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_7__SPDIF_PLOCK */
1384
+
IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE */
1385
+
IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 0, 0x0888, 1), /* MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 */
1386
+
IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT */
1387
+
IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_8__EPIT2_EPITO */
1388
+
IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 3, 0x07E4, 1), /* MX6Q_PAD_GPIO_8__CAN1_RXCAN */
1389
+
IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 4, 0x0928, 3), /* MX6Q_PAD_GPIO_8__UART2_RXD */
1390
+
IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_8__GPIO_1_8 */
1391
+
IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_8__SPDIF_SRCLK */
1392
+
IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK */
1393
+
IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 0, 0x0880, 1), /* MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 */
1394
+
IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN */
1395
+
IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 2, 0x083C, 1), /* MX6Q_PAD_GPIO_16__ENET_ETHERNET_REF_OUT */
1396
+
IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_16__USDHC1_LCTL */
1397
+
IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 4, 0x0914, 3), /* MX6Q_PAD_GPIO_16__SPDIF_IN1 */
1398
+
IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_16__GPIO_7_11 */
1399
+
IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 6, 0x08AC, 2), /* MX6Q_PAD_GPIO_16__I2C3_SDA */
1400
+
IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_16__SJC_DE_B */
1401
+
IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 0, 0x0874, 0), /* MX6Q_PAD_GPIO_17__ESAI1_TX0 */
1402
+
IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN */
1403
+
IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 2, 0x07F0, 1), /* MX6Q_PAD_GPIO_17__CCM_PMIC_RDY */
1404
+
IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 3, 0x090C, 1), /* MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 */
1405
+
IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_17__SPDIF_OUT1 */
1406
+
IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_17__GPIO_7_12 */
1407
+
IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_17__SJC_JTAG_ACT */
1408
+
IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 0, 0x0878, 0), /* MX6Q_PAD_GPIO_18__ESAI1_TX1 */
1409
+
IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 1, 0x0844, 1), /* MX6Q_PAD_GPIO_18__ENET_RX_CLK */
1410
+
IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_18__USDHC3_VSELECT */
1411
+
IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 3, 0x0910, 1), /* MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 */
1412
+
IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 4, 0x07B0, 2), /* MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK */
1413
+
IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_18__GPIO_7_13 */
1414
+
IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 */
1415
+
IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST */
1416
+
IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 0, 0x08E8, 1), /* MX6Q_PAD_GPIO_19__KPP_COL_5 */
1417
+
IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT */
1418
+
IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_19__SPDIF_OUT1 */
1419
+
IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_19__CCM_CLKO */
1420
+
IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ECSPI1_RDY */
1421
+
IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_19__GPIO_4_5 */
1422
+
IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ENET_TX_ER */
1423
+
IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_19__SRC_INT_BOOT */
1424
+
IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK */
1425
+
IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 */
1426
+
IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 */
1427
+
IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 */
1428
+
IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 */
1429
+
IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO */
1430
+
IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC */
1431
+
IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 */
1432
+
IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__CCM_CLKO */
1433
+
IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 */
1434
+
IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__GPIO_5_19 */
1435
+
IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 */
1436
+
IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL */
1437
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN */
1438
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 */
1439
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 */
1440
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 */
1441
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 */
1442
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 */
1443
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK */
1444
+
IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC */
1445
+
IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 */
1446
+
IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 */
1447
+
IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 */
1448
+
IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 */
1449
+
IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__MMDC_DEBUG_32 */
1450
+
IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 */
1451
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 */
1452
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 */
1453
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 2, 0x07F4, 3), /* MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK */
1454
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 3, 0x08E8, 2), /* MX6Q_PAD_CSI0_DAT4__KPP_COL_5 */
1455
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC */
1456
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__GPIO_5_22 */
1457
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__MMDC_DEBUG_43 */
1458
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 */
1459
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 */
1460
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 */
1461
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 2, 0x07FC, 3), /* MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI */
1462
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 3, 0x08F4, 1), /* MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 */
1463
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD */
1464
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__GPIO_5_23 */
1465
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 */
1466
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 */
1467
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 */
1468
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 */
1469
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 2, 0x07F8, 3), /* MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO */
1470
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 3, 0x08EC, 1), /* MX6Q_PAD_CSI0_DAT6__KPP_COL_6 */
1471
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS */
1472
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__GPIO_5_24 */
1473
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 */
1474
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 */
1475
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 */
1476
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 */
1477
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 2, 0x0800, 3), /* MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 */
1478
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 3, 0x08F8, 2), /* MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 */
1479
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD */
1480
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__GPIO_5_25 */
1481
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 */
1482
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 */
1483
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 */
1484
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 */
1485
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 2, 0x0810, 2), /* MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK */
1486
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 3, 0x08F0, 2), /* MX6Q_PAD_CSI0_DAT8__KPP_COL_7 */
1487
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 4, 0x089C, 1), /* MX6Q_PAD_CSI0_DAT8__I2C1_SDA */
1488
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__GPIO_5_26 */
1489
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 */
1490
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 */
1491
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 */
1492
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 */
1493
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 2, 0x0818, 2), /* MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI */
1494
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 3, 0x08FC, 2), /* MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 */
1495
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 4, 0x0898, 1), /* MX6Q_PAD_CSI0_DAT9__I2C1_SCL */
1496
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__GPIO_5_27 */
1497
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 */
1498
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 */
1499
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 */
1500
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC */
1501
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 2, 0x0814, 2), /* MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO */
1502
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
1503
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 */
1504
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__GPIO_5_28 */
1505
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 */
1506
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 */
1507
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 */
1508
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS */
1509
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 2, 0x081C, 2), /* MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 */
1510
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 3, 0x0920, 1), /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
1511
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 */
1512
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__GPIO_5_29 */
1513
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 */
1514
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 */
1515
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 */
1516
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 */
1517
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 */
1518
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__UART4_TXD */
1519
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 */
1520
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__GPIO_5_30 */
1521
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 */
1522
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 */
1523
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 */
1524
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 */
1525
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 */
1526
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 3, 0x0938, 3), /* MX6Q_PAD_CSI0_DAT13__UART4_RXD */
1527
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 */
1528
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__GPIO_5_31 */
1529
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 */
1530
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 */
1531
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 */
1532
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 */
1533
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 */
1534
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__UART5_TXD */
1535
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 */
1536
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__GPIO_6_0 */
1537
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 */
1538
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 */
1539
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 */
1540
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 */
1541
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 */
1542
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 3, 0x0940, 3), /* MX6Q_PAD_CSI0_DAT15__UART5_RXD */
1543
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 */
1544
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__GPIO_6_1 */
1545
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 */
1546
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 */
1547
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 */
1548
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 */
1549
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 */
1550
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 3, 0x0934, 0), /* MX6Q_PAD_CSI0_DAT16__UART4_RTS */
1551
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 */
1552
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__GPIO_6_2 */
1553
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 */
1554
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 */
1555
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 */
1556
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 */
1557
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 */
1558
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 3, 0x0934, 1), /* MX6Q_PAD_CSI0_DAT17__UART4_CTS */
1559
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 */
1560
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__GPIO_6_3 */
1561
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 */
1562
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 */
1563
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 */
1564
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 */
1565
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 */
1566
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 3, 0x093C, 2), /* MX6Q_PAD_CSI0_DAT18__UART5_RTS */
1567
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 */
1568
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__GPIO_6_4 */
1569
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 */
1570
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 */
1571
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 */
1572
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 */
1573
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 */
1574
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 3, 0x093C, 3), /* MX6Q_PAD_CSI0_DAT19__UART5_CTS */
1575
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 */
1576
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__GPIO_6_5 */
1577
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 */
1578
+
IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__ANATOP_TESTO_9 */
1579
+
IMX_PIN_REG(MX6Q_PAD_JTAG_TMS, 0x0678, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TMS__SJC_TMS */
1580
+
IMX_PIN_REG(MX6Q_PAD_JTAG_MOD, 0x067C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_MOD__SJC_MOD */
1581
+
IMX_PIN_REG(MX6Q_PAD_JTAG_TRSTB, 0x0680, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB */
1582
+
IMX_PIN_REG(MX6Q_PAD_JTAG_TDI, 0x0684, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TDI__SJC_TDI */
1583
+
IMX_PIN_REG(MX6Q_PAD_JTAG_TCK, 0x0688, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TCK__SJC_TCK */
1584
+
IMX_PIN_REG(MX6Q_PAD_JTAG_TDO, 0x068C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TDO__SJC_TDO */
1585
+
IMX_PIN_REG(MX6Q_PAD_LVDS1_TX3_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 */
1586
+
IMX_PIN_REG(MX6Q_PAD_LVDS1_TX2_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 */
1587
+
IMX_PIN_REG(MX6Q_PAD_LVDS1_CLK_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK */
1588
+
IMX_PIN_REG(MX6Q_PAD_LVDS1_TX1_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 */
1589
+
IMX_PIN_REG(MX6Q_PAD_LVDS1_TX0_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 */
1590
+
IMX_PIN_REG(MX6Q_PAD_LVDS0_TX3_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 */
1591
+
IMX_PIN_REG(MX6Q_PAD_LVDS0_CLK_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK */
1592
+
IMX_PIN_REG(MX6Q_PAD_LVDS0_TX2_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 */
1593
+
IMX_PIN_REG(MX6Q_PAD_LVDS0_TX1_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 */
1594
+
IMX_PIN_REG(MX6Q_PAD_LVDS0_TX0_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 */
1595
+
IMX_PIN_REG(MX6Q_PAD_TAMPER, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 */
1596
+
IMX_PIN_REG(MX6Q_PAD_PMIC_ON_REQ, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM */
1597
+
IMX_PIN_REG(MX6Q_PAD_PMIC_STBY_REQ, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ */
1598
+
IMX_PIN_REG(MX6Q_PAD_POR_B, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_POR_B__SRC_POR_B */
1599
+
IMX_PIN_REG(MX6Q_PAD_BOOT_MODE1, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 */
1600
+
IMX_PIN_REG(MX6Q_PAD_RESET_IN_B, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_RESET_IN_B__SRC_RESET_B */
1601
+
IMX_PIN_REG(MX6Q_PAD_BOOT_MODE0, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 */
1602
+
IMX_PIN_REG(MX6Q_PAD_TEST_MODE, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_TEST_MODE__TCU_TEST_MODE */
1603
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
1604
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 1, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__UART1_TXD */
1605
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 */
1606
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 */
1607
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 */
1608
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__GPIO_6_17 */
1609
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 */
1610
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV */
1611
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
1612
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 1, 0x0920, 3), /* MX6Q_PAD_SD3_DAT6__UART1_RXD */
1613
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 */
1614
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 */
1615
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 */
1616
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__GPIO_6_18 */
1617
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 */
1618
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10 */
1619
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
1620
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 1, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__UART2_TXD */
1621
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 */
1622
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 */
1623
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 */
1624
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
1625
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 */
1626
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11 */
1627
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
1628
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 1, 0x0928, 5), /* MX6Q_PAD_SD3_DAT4__UART2_RXD */
1629
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 */
1630
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 */
1631
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 */
1632
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
1633
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 */
1634
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__ANATOP_TESTO_12 */
1635
+
IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
1636
+
IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 1, 0x0924, 2), /* MX6Q_PAD_SD3_CMD__UART2_CTS */
1637
+
IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__CAN1_TXCAN */
1638
+
IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 */
1639
+
IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 */
1640
+
IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__GPIO_7_2 */
1641
+
IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 */
1642
+
IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__ANATOP_TESTO_13 */
1643
+
IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
1644
+
IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 1, 0x0924, 3), /* MX6Q_PAD_SD3_CLK__UART2_RTS */
1645
+
IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 2, 0x07E4, 2), /* MX6Q_PAD_SD3_CLK__CAN1_RXCAN */
1646
+
IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 */
1647
+
IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 */
1648
+
IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__GPIO_7_3 */
1649
+
IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 */
1650
+
IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__ANATOP_TESTO_14 */
1651
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
1652
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 1, 0x091C, 2), /* MX6Q_PAD_SD3_DAT0__UART1_CTS */
1653
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__CAN2_TXCAN */
1654
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 */
1655
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 */
1656
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__GPIO_7_4 */
1657
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 */
1658
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__ANATOP_TESTO_15 */
1659
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
1660
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 1, 0x091C, 3), /* MX6Q_PAD_SD3_DAT1__UART1_RTS */
1661
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 2, 0x07E8, 1), /* MX6Q_PAD_SD3_DAT1__CAN2_RXCAN */
1662
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 */
1663
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 */
1664
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__GPIO_7_5 */
1665
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 */
1666
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__ANATOP_TESTI_0 */
1667
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
1668
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 */
1669
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 */
1670
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 */
1671
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__GPIO_7_6 */
1672
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 */
1673
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__ANATOP_TESTI_1 */
1674
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
1675
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 1, 0x092C, 4), /* MX6Q_PAD_SD3_DAT3__UART3_CTS */
1676
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 */
1677
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 */
1678
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 */
1679
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__GPIO_7_7 */
1680
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 */
1681
+
IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__ANATOP_TESTI_2 */
1682
+
IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USDHC3_RST */
1683
+
IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 1, 0x092C, 5), /* MX6Q_PAD_SD3_RST__UART3_RTS */
1684
+
IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_RST__PCIE_CTRL_MUX_30 */
1685
+
IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 */
1686
+
IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 */
1687
+
IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_RST__GPIO_7_8 */
1688
+
IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 */
1689
+
IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 */
1690
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
1691
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 */
1692
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 */
1693
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 */
1694
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 */
1695
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__GPIO_6_7 */
1696
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 */
1697
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 */
1698
+
IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
1699
+
IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USDHC4_RST */
1700
+
IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 */
1701
+
IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 */
1702
+
IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 */
1703
+
IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__GPIO_6_8 */
1704
+
IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 */
1705
+
IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 */
1706
+
IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
1707
+
IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 */
1708
+
IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 */
1709
+
IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 */
1710
+
IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 */
1711
+
IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__GPIO_6_9 */
1712
+
IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 */
1713
+
IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 */
1714
+
IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
1715
+
IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 */
1716
+
IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 */
1717
+
IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 */
1718
+
IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 */
1719
+
IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__GPIO_6_10 */
1720
+
IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 */
1721
+
IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 */
1722
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
1723
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 */
1724
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 */
1725
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
1726
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 */
1727
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
1728
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT */
1729
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT */
1730
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 */
1731
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
1732
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__PL301_PER1_HRDYOUT */
1733
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
1734
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 */
1735
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 2, 0x0874, 1), /* MX6Q_PAD_NANDF_CS2__ESAI1_TX0 */
1736
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE */
1737
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__CCM_CLKO2 */
1738
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */
1739
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 */
1740
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
1741
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 */
1742
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 2, 0x0878, 1), /* MX6Q_PAD_NANDF_CS3__ESAI1_TX1 */
1743
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 */
1744
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 */
1745
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__GPIO_6_16 */
1746
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 */
1747
+
IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__TPSMP_CLK */
1748
+
IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 0, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
1749
+
IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 1, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
1750
+
IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 2, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__UART3_TXD */
1751
+
IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 4, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__PCIE_CTRL_MUX_5 */
1752
+
IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 5, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__GPIO_7_9 */
1753
+
IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 7, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR */
1754
+
IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 0, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
1755
+
IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 1, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
1756
+
IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 2, 0x0930, 3), /* MX6Q_PAD_SD4_CLK__UART3_RXD */
1757
+
IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 4, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__PCIE_CTRL_MUX_6 */
1758
+
IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 5, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__GPIO_7_10 */
1759
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
1760
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USDHC1_DAT4 */
1761
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 */
1762
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 */
1763
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 */
1764
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
1765
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 */
1766
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 */
1767
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
1768
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USDHC1_DAT5 */
1769
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 */
1770
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 */
1771
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 */
1772
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
1773
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 */
1774
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 */
1775
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
1776
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USDHC1_DAT6 */
1777
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 */
1778
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 */
1779
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 */
1780
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
1781
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 */
1782
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 */
1783
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
1784
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USDHC1_DAT7 */
1785
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 */
1786
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 */
1787
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 */
1788
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
1789
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 */
1790
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 */
1791
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
1792
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
1793
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 */
1794
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 */
1795
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 */
1796
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__GPIO_2_4 */
1797
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 */
1798
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 */
1799
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
1800
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
1801
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 */
1802
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 */
1803
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 */
1804
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__GPIO_2_5 */
1805
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 */
1806
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 */
1807
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
1808
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
1809
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 */
1810
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 */
1811
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 */
1812
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
1813
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 */
1814
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 */
1815
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
1816
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
1817
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 */
1818
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 */
1819
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 */
1820
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
1821
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 */
1822
+
IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 */
1823
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__RAWNAND_D8 */
1824
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
1825
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
1826
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 */
1827
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 */
1828
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__GPIO_2_8 */
1829
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 */
1830
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 */
1831
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__RAWNAND_D9 */
1832
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
1833
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__PWM3_PWMO */
1834
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 */
1835
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 */
1836
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__GPIO_2_9 */
1837
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 */
1838
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 */
1839
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__RAWNAND_D10 */
1840
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
1841
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__PWM4_PWMO */
1842
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 */
1843
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 */
1844
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__GPIO_2_10 */
1845
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 */
1846
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 */
1847
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__RAWNAND_D11 */
1848
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
1849
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 */
1850
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 */
1851
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__GPIO_2_11 */
1852
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 */
1853
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 */
1854
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__RAWNAND_D12 */
1855
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
1856
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 2, 0x0928, 6), /* MX6Q_PAD_SD4_DAT4__UART2_RXD */
1857
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 */
1858
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 */
1859
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__GPIO_2_12 */
1860
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 */
1861
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 */
1862
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__RAWNAND_D13 */
1863
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
1864
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 2, 0x0924, 4), /* MX6Q_PAD_SD4_DAT5__UART2_RTS */
1865
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 */
1866
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 */
1867
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__GPIO_2_13 */
1868
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 */
1869
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 */
1870
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__RAWNAND_D14 */
1871
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
1872
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 2, 0x0924, 5), /* MX6Q_PAD_SD4_DAT6__UART2_CTS */
1873
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 */
1874
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 */
1875
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__GPIO_2_14 */
1876
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 */
1877
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 */
1878
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__RAWNAND_D15 */
1879
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
1880
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__UART2_TXD */
1881
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 */
1882
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 */
1883
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__GPIO_2_15 */
1884
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 */
1885
+
IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 */
1886
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 */
1887
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 1, 0x0834, 1), /* MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 */
1888
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__PWM3_PWMO */
1889
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 */
1890
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 */
1891
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__GPIO_1_17 */
1892
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 */
1893
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__ANATOP_TESTO_8 */
1894
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 */
1895
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 1, 0x082C, 1), /* MX6Q_PAD_SD1_DAT0__ECSPI5_MISO */
1896
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS */
1897
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 */
1898
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 */
1899
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__GPIO_1_16 */
1900
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 */
1901
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__ANATOP_TESTO_7 */
1902
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 */
1903
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 1, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 */
1904
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 */
1905
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__PWM1_PWMO */
1906
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B */
1907
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__GPIO_1_21 */
1908
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB */
1909
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__ANATOP_TESTO_6 */
1910
+
IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 0, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__USDHC1_CMD */
1911
+
IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 1, 0x0830, 0), /* MX6Q_PAD_SD1_CMD__ECSPI5_MOSI */
1912
+
IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 2, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__PWM4_PWMO */
1913
+
IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 3, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 */
1914
+
IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 5, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__GPIO_1_18 */
1915
+
IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 7, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__ANATOP_TESTO_5 */
1916
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 */
1917
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 1, 0x0838, 1), /* MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 */
1918
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 */
1919
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__PWM2_PWMO */
1920
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B */
1921
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__GPIO_1_19 */
1922
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB */
1923
+
IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__ANATOP_TESTO_4 */
1924
+
IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 0, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__USDHC1_CLK */
1925
+
IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 1, 0x0828, 0), /* MX6Q_PAD_SD1_CLK__ECSPI5_SCLK */
1926
+
IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 2, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT */
1927
+
IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 3, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__GPT_CLKIN */
1928
+
IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 5, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__GPIO_1_20 */
1929
+
IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 6, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__PHY_DTB_0 */
1930
+
IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 7, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 */
1931
+
IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 0, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
1932
+
IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 1, 0x0828, 1), /* MX6Q_PAD_SD2_CLK__ECSPI5_SCLK */
1933
+
IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 2, 0x08E8, 3), /* MX6Q_PAD_SD2_CLK__KPP_COL_5 */
1934
+
IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 3, 0x07C0, 1), /* MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS */
1935
+
IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 4, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__PCIE_CTRL_MUX_9 */
1936
+
IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 5, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__GPIO_1_10 */
1937
+
IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 6, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__PHY_DTB_1 */
1938
+
IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 7, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 */
1939
+
IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 0, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
1940
+
IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 1, 0x0830, 1), /* MX6Q_PAD_SD2_CMD__ECSPI5_MOSI */
1941
+
IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 2, 0x08F4, 2), /* MX6Q_PAD_SD2_CMD__KPP_ROW_5 */
1942
+
IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 3, 0x07BC, 1), /* MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC */
1943
+
IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 4, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__PCIE_CTRL_MUX_10 */
1944
+
IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 5, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__GPIO_1_11 */
1945
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
1946
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 1, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 */
1947
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 2, 0x08EC, 2), /* MX6Q_PAD_SD2_DAT3__KPP_COL_6 */
1948
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 3, 0x07C4, 1), /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
1949
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 4, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 */
1950
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__GPIO_1_12 */
1951
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__SJC_DONE */
1952
+
IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 */
1953
+
};
1954
+
1955
+
/* Pad names for the pinmux subsystem */
1956
+
static const struct pinctrl_pin_desc imx6q_pinctrl_pads[] = {
1957
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT1),
1958
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT2),
1959
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT0),
1960
+
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TXC),
1961
+
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD0),
1962
+
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD1),
1963
+
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD2),
1964
+
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD3),
1965
+
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RX_CTL),
1966
+
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD0),
1967
+
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TX_CTL),
1968
+
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD1),
1969
+
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD2),
1970
+
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD3),
1971
+
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RXC),
1972
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A25),
1973
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB2),
1974
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D16),
1975
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D17),
1976
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D18),
1977
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D19),
1978
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D20),
1979
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D21),
1980
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D22),
1981
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D23),
1982
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB3),
1983
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D24),
1984
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D25),
1985
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D26),
1986
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D27),
1987
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D28),
1988
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D29),
1989
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D30),
1990
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D31),
1991
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A24),
1992
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A23),
1993
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A22),
1994
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A21),
1995
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A20),
1996
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A19),
1997
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A18),
1998
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A17),
1999
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A16),
2000
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS0),
2001
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS1),
2002
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_OE),
2003
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_RW),
2004
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_LBA),
2005
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB0),
2006
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB1),
2007
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA0),
2008
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA1),
2009
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA2),
2010
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA3),
2011
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA4),
2012
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA5),
2013
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA6),
2014
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA7),
2015
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA8),
2016
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA9),
2017
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA10),
2018
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA11),
2019
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA12),
2020
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA13),
2021
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA14),
2022
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA15),
2023
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_WAIT),
2024
+
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_BCLK),
2025
+
IMX_PINCTRL_PIN(MX6Q_PAD_DI0_DISP_CLK),
2026
+
IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN15),
2027
+
IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN2),
2028
+
IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN3),
2029
+
IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN4),
2030
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT0),
2031
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT1),
2032
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT2),
2033
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT3),
2034
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT4),
2035
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT5),
2036
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT6),
2037
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT7),
2038
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT8),
2039
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT9),
2040
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT10),
2041
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT11),
2042
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT12),
2043
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT13),
2044
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT14),
2045
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT15),
2046
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT16),
2047
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT17),
2048
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT18),
2049
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT19),
2050
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT20),
2051
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT21),
2052
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT22),
2053
+
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT23),
2054
+
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDIO),
2055
+
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_REF_CLK),
2056
+
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RX_ER),
2057
+
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_CRS_DV),
2058
+
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD1),
2059
+
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD0),
2060
+
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TX_EN),
2061
+
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD1),
2062
+
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD0),
2063
+
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDC),
2064
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D40),
2065
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D41),
2066
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D42),
2067
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D43),
2068
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D44),
2069
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D45),
2070
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D46),
2071
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D47),
2072
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS5),
2073
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM5),
2074
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D32),
2075
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D33),
2076
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D34),
2077
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D35),
2078
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D36),
2079
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D37),
2080
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D38),
2081
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D39),
2082
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM4),
2083
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS4),
2084
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D24),
2085
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D25),
2086
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D26),
2087
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D27),
2088
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D28),
2089
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D29),
2090
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS3),
2091
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D30),
2092
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D31),
2093
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM3),
2094
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D16),
2095
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D17),
2096
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D18),
2097
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D19),
2098
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D20),
2099
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D21),
2100
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D22),
2101
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS2),
2102
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D23),
2103
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM2),
2104
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A0),
2105
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A1),
2106
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A2),
2107
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A3),
2108
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A4),
2109
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A5),
2110
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A6),
2111
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A7),
2112
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A8),
2113
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A9),
2114
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A10),
2115
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A11),
2116
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A12),
2117
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A13),
2118
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A14),
2119
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A15),
2120
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CAS),
2121
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CS0),
2122
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CS1),
2123
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_RAS),
2124
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_RESET),
2125
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA0),
2126
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA1),
2127
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCLK_0),
2128
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA2),
2129
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCKE0),
2130
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCLK_1),
2131
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCKE1),
2132
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDODT0),
2133
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDODT1),
2134
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDWE),
2135
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D0),
2136
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D1),
2137
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D2),
2138
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D3),
2139
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D4),
2140
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D5),
2141
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS0),
2142
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D6),
2143
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D7),
2144
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM0),
2145
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D8),
2146
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D9),
2147
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D10),
2148
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D11),
2149
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D12),
2150
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D13),
2151
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D14),
2152
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS1),
2153
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D15),
2154
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM1),
2155
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D48),
2156
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D49),
2157
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D50),
2158
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D51),
2159
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D52),
2160
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D53),
2161
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D54),
2162
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D55),
2163
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS6),
2164
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM6),
2165
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D56),
2166
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS7),
2167
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D57),
2168
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D58),
2169
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D59),
2170
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D60),
2171
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM7),
2172
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D61),
2173
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D62),
2174
+
IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D63),
2175
+
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL0),
2176
+
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW0),
2177
+
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL1),
2178
+
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW1),
2179
+
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL2),
2180
+
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW2),
2181
+
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL3),
2182
+
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW3),
2183
+
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL4),
2184
+
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW4),
2185
+
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_0),
2186
+
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_1),
2187
+
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_9),
2188
+
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_3),
2189
+
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_6),
2190
+
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_2),
2191
+
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_4),
2192
+
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_5),
2193
+
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_7),
2194
+
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_8),
2195
+
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_16),
2196
+
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_17),
2197
+
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_18),
2198
+
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_19),
2199
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_PIXCLK),
2200
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_MCLK),
2201
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DATA_EN),
2202
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_VSYNC),
2203
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT4),
2204
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT5),
2205
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT6),
2206
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT7),
2207
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT8),
2208
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT9),
2209
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT10),
2210
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT11),
2211
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT12),
2212
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT13),
2213
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT14),
2214
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT15),
2215
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT16),
2216
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT17),
2217
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT18),
2218
+
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT19),
2219
+
IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TMS),
2220
+
IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_MOD),
2221
+
IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TRSTB),
2222
+
IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TDI),
2223
+
IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TCK),
2224
+
IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TDO),
2225
+
IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX3_P),
2226
+
IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX2_P),
2227
+
IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_CLK_P),
2228
+
IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX1_P),
2229
+
IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX0_P),
2230
+
IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX3_P),
2231
+
IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_CLK_P),
2232
+
IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX2_P),
2233
+
IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX1_P),
2234
+
IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX0_P),
2235
+
IMX_PINCTRL_PIN(MX6Q_PAD_TAMPER),
2236
+
IMX_PINCTRL_PIN(MX6Q_PAD_PMIC_ON_REQ),
2237
+
IMX_PINCTRL_PIN(MX6Q_PAD_PMIC_STBY_REQ),
2238
+
IMX_PINCTRL_PIN(MX6Q_PAD_POR_B),
2239
+
IMX_PINCTRL_PIN(MX6Q_PAD_BOOT_MODE1),
2240
+
IMX_PINCTRL_PIN(MX6Q_PAD_RESET_IN_B),
2241
+
IMX_PINCTRL_PIN(MX6Q_PAD_BOOT_MODE0),
2242
+
IMX_PINCTRL_PIN(MX6Q_PAD_TEST_MODE),
2243
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT7),
2244
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT6),
2245
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT5),
2246
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT4),
2247
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CMD),
2248
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CLK),
2249
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT0),
2250
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT1),
2251
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT2),
2252
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT3),
2253
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_RST),
2254
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CLE),
2255
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_ALE),
2256
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_WP_B),
2257
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_RB0),
2258
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS0),
2259
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS1),
2260
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS2),
2261
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS3),
2262
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CMD),
2263
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CLK),
2264
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D0),
2265
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D1),
2266
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D2),
2267
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D3),
2268
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D4),
2269
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D5),
2270
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D6),
2271
+
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D7),
2272
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT0),
2273
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT1),
2274
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT2),
2275
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT3),
2276
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT4),
2277
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT5),
2278
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT6),
2279
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT7),
2280
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT1),
2281
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT0),
2282
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT3),
2283
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CMD),
2284
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT2),
2285
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CLK),
2286
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CLK),
2287
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CMD),
2288
+
IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT3),
2289
+
};
2290
+
2291
+
static struct imx_pinctrl_soc_info imx6q_pinctrl_info = {
2292
+
.pins = imx6q_pinctrl_pads,
2293
+
.npins = ARRAY_SIZE(imx6q_pinctrl_pads),
2294
+
.pin_regs = imx6q_pin_regs,
2295
+
.npin_regs = ARRAY_SIZE(imx6q_pin_regs),
2296
+
};
2297
+
2298
+
static struct of_device_id imx6q_pinctrl_of_match[] __devinitdata = {
2299
+
{ .compatible = "fsl,imx6q-iomuxc", },
2300
+
{ /* sentinel */ }
2301
+
};
2302
+
2303
+
static int __devinit imx6q_pinctrl_probe(struct platform_device *pdev)
2304
+
{
2305
+
return imx_pinctrl_probe(pdev, &imx6q_pinctrl_info);
2306
+
}
2307
+
2308
+
static struct platform_driver imx6q_pinctrl_driver = {
2309
+
.driver = {
2310
+
.name = "imx6q-pinctrl",
2311
+
.owner = THIS_MODULE,
2312
+
.of_match_table = of_match_ptr(imx6q_pinctrl_of_match),
2313
+
},
2314
+
.probe = imx6q_pinctrl_probe,
2315
+
.remove = __devexit_p(imx_pinctrl_remove),
2316
+
};
2317
+
2318
+
static int __init imx6q_pinctrl_init(void)
2319
+
{
2320
+
return platform_driver_register(&imx6q_pinctrl_driver);
2321
+
}
2322
+
arch_initcall(imx6q_pinctrl_init);
2323
+
2324
+
static void __exit imx6q_pinctrl_exit(void)
2325
+
{
2326
+
platform_driver_unregister(&imx6q_pinctrl_driver);
2327
+
}
2328
+
module_exit(imx6q_pinctrl_exit);
2329
+
MODULE_AUTHOR("Dong Aisheng <dong.aisheng@linaro.org>");
2330
+
MODULE_DESCRIPTION("Freescale IMX6Q pinctrl driver");
2331
+
MODULE_LICENSE("GPL v2");
+508
drivers/pinctrl/pinctrl-mxs.c
+508
drivers/pinctrl/pinctrl-mxs.c
···
1
+
/*
2
+
* Copyright 2012 Freescale Semiconductor, Inc.
3
+
*
4
+
* The code contained herein is licensed under the GNU General Public
5
+
* License. You may obtain a copy of the GNU General Public License
6
+
* Version 2 or later at the following locations:
7
+
*
8
+
* http://www.opensource.org/licenses/gpl-license.html
9
+
* http://www.gnu.org/copyleft/gpl.html
10
+
*/
11
+
12
+
#include <linux/err.h>
13
+
#include <linux/init.h>
14
+
#include <linux/io.h>
15
+
#include <linux/module.h>
16
+
#include <linux/of.h>
17
+
#include <linux/of_address.h>
18
+
#include <linux/pinctrl/machine.h>
19
+
#include <linux/pinctrl/pinconf.h>
20
+
#include <linux/pinctrl/pinctrl.h>
21
+
#include <linux/pinctrl/pinmux.h>
22
+
#include <linux/platform_device.h>
23
+
#include <linux/slab.h>
24
+
#include "core.h"
25
+
#include "pinctrl-mxs.h"
26
+
27
+
#define SUFFIX_LEN 4
28
+
29
+
struct mxs_pinctrl_data {
30
+
struct device *dev;
31
+
struct pinctrl_dev *pctl;
32
+
void __iomem *base;
33
+
struct mxs_pinctrl_soc_data *soc;
34
+
};
35
+
36
+
static int mxs_get_groups_count(struct pinctrl_dev *pctldev)
37
+
{
38
+
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
39
+
40
+
return d->soc->ngroups;
41
+
}
42
+
43
+
static const char *mxs_get_group_name(struct pinctrl_dev *pctldev,
44
+
unsigned group)
45
+
{
46
+
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
47
+
48
+
return d->soc->groups[group].name;
49
+
}
50
+
51
+
static int mxs_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
52
+
const unsigned **pins, unsigned *num_pins)
53
+
{
54
+
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
55
+
56
+
*pins = d->soc->groups[group].pins;
57
+
*num_pins = d->soc->groups[group].npins;
58
+
59
+
return 0;
60
+
}
61
+
62
+
static void mxs_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
63
+
unsigned offset)
64
+
{
65
+
seq_printf(s, " %s", dev_name(pctldev->dev));
66
+
}
67
+
68
+
static int mxs_dt_node_to_map(struct pinctrl_dev *pctldev,
69
+
struct device_node *np,
70
+
struct pinctrl_map **map, unsigned *num_maps)
71
+
{
72
+
struct pinctrl_map *new_map;
73
+
char *group;
74
+
unsigned new_num;
75
+
unsigned long config = 0;
76
+
unsigned long *pconfig;
77
+
int length = strlen(np->name) + SUFFIX_LEN;
78
+
u32 val;
79
+
int ret;
80
+
81
+
ret = of_property_read_u32(np, "fsl,drive-strength", &val);
82
+
if (!ret)
83
+
config = val | MA_PRESENT;
84
+
ret = of_property_read_u32(np, "fsl,voltage", &val);
85
+
if (!ret)
86
+
config |= val << VOL_SHIFT | VOL_PRESENT;
87
+
ret = of_property_read_u32(np, "fsl,pull-up", &val);
88
+
if (!ret)
89
+
config |= val << PULL_SHIFT | PULL_PRESENT;
90
+
91
+
new_num = config ? 2 : 1;
92
+
new_map = kzalloc(sizeof(*new_map) * new_num, GFP_KERNEL);
93
+
if (!new_map)
94
+
return -ENOMEM;
95
+
96
+
new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
97
+
new_map[0].data.mux.function = np->name;
98
+
99
+
/* Compose group name */
100
+
group = kzalloc(length, GFP_KERNEL);
101
+
if (!group)
102
+
return -ENOMEM;
103
+
of_property_read_u32(np, "reg", &val);
104
+
snprintf(group, length, "%s.%d", np->name, val);
105
+
new_map[0].data.mux.group = group;
106
+
107
+
if (config) {
108
+
pconfig = kmemdup(&config, sizeof(config), GFP_KERNEL);
109
+
if (!pconfig) {
110
+
ret = -ENOMEM;
111
+
goto free;
112
+
}
113
+
114
+
new_map[1].type = PIN_MAP_TYPE_CONFIGS_GROUP;
115
+
new_map[1].data.configs.group_or_pin = group;
116
+
new_map[1].data.configs.configs = pconfig;
117
+
new_map[1].data.configs.num_configs = 1;
118
+
}
119
+
120
+
*map = new_map;
121
+
*num_maps = new_num;
122
+
123
+
return 0;
124
+
125
+
free:
126
+
kfree(new_map);
127
+
return ret;
128
+
}
129
+
130
+
static void mxs_dt_free_map(struct pinctrl_dev *pctldev,
131
+
struct pinctrl_map *map, unsigned num_maps)
132
+
{
133
+
int i;
134
+
135
+
for (i = 0; i < num_maps; i++) {
136
+
if (map[i].type == PIN_MAP_TYPE_MUX_GROUP)
137
+
kfree(map[i].data.mux.group);
138
+
if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
139
+
kfree(map[i].data.configs.configs);
140
+
}
141
+
142
+
kfree(map);
143
+
}
144
+
145
+
static struct pinctrl_ops mxs_pinctrl_ops = {
146
+
.get_groups_count = mxs_get_groups_count,
147
+
.get_group_name = mxs_get_group_name,
148
+
.get_group_pins = mxs_get_group_pins,
149
+
.pin_dbg_show = mxs_pin_dbg_show,
150
+
.dt_node_to_map = mxs_dt_node_to_map,
151
+
.dt_free_map = mxs_dt_free_map,
152
+
};
153
+
154
+
static int mxs_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
155
+
{
156
+
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
157
+
158
+
return d->soc->nfunctions;
159
+
}
160
+
161
+
static const char *mxs_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
162
+
unsigned function)
163
+
{
164
+
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
165
+
166
+
return d->soc->functions[function].name;
167
+
}
168
+
169
+
static int mxs_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
170
+
unsigned group,
171
+
const char * const **groups,
172
+
unsigned * const num_groups)
173
+
{
174
+
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
175
+
176
+
*groups = d->soc->functions[group].groups;
177
+
*num_groups = d->soc->functions[group].ngroups;
178
+
179
+
return 0;
180
+
}
181
+
182
+
static int mxs_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned selector,
183
+
unsigned group)
184
+
{
185
+
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
186
+
struct mxs_group *g = &d->soc->groups[group];
187
+
void __iomem *reg;
188
+
u8 bank, shift;
189
+
u16 pin;
190
+
int i;
191
+
192
+
for (i = 0; i < g->npins; i++) {
193
+
bank = PINID_TO_BANK(g->pins[i]);
194
+
pin = PINID_TO_PIN(g->pins[i]);
195
+
reg = d->base + d->soc->regs->muxsel;
196
+
reg += bank * 0x20 + pin / 16 * 0x10;
197
+
shift = pin % 16 * 2;
198
+
199
+
writel(0x3 << shift, reg + CLR);
200
+
writel(g->muxsel[i] << shift, reg + SET);
201
+
}
202
+
203
+
return 0;
204
+
}
205
+
206
+
static void mxs_pinctrl_disable(struct pinctrl_dev *pctldev,
207
+
unsigned function, unsigned group)
208
+
{
209
+
/* Nothing to do here */
210
+
}
211
+
212
+
static struct pinmux_ops mxs_pinmux_ops = {
213
+
.get_functions_count = mxs_pinctrl_get_funcs_count,
214
+
.get_function_name = mxs_pinctrl_get_func_name,
215
+
.get_function_groups = mxs_pinctrl_get_func_groups,
216
+
.enable = mxs_pinctrl_enable,
217
+
.disable = mxs_pinctrl_disable,
218
+
};
219
+
220
+
static int mxs_pinconf_get(struct pinctrl_dev *pctldev,
221
+
unsigned pin, unsigned long *config)
222
+
{
223
+
return -ENOTSUPP;
224
+
}
225
+
226
+
static int mxs_pinconf_set(struct pinctrl_dev *pctldev,
227
+
unsigned pin, unsigned long config)
228
+
{
229
+
return -ENOTSUPP;
230
+
}
231
+
232
+
static int mxs_pinconf_group_get(struct pinctrl_dev *pctldev,
233
+
unsigned group, unsigned long *config)
234
+
{
235
+
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
236
+
237
+
*config = d->soc->groups[group].config;
238
+
239
+
return 0;
240
+
}
241
+
242
+
static int mxs_pinconf_group_set(struct pinctrl_dev *pctldev,
243
+
unsigned group, unsigned long config)
244
+
{
245
+
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
246
+
struct mxs_group *g = &d->soc->groups[group];
247
+
void __iomem *reg;
248
+
u8 ma, vol, pull, bank, shift;
249
+
u16 pin;
250
+
int i;
251
+
252
+
ma = CONFIG_TO_MA(config);
253
+
vol = CONFIG_TO_VOL(config);
254
+
pull = CONFIG_TO_PULL(config);
255
+
256
+
for (i = 0; i < g->npins; i++) {
257
+
bank = PINID_TO_BANK(g->pins[i]);
258
+
pin = PINID_TO_PIN(g->pins[i]);
259
+
260
+
/* drive */
261
+
reg = d->base + d->soc->regs->drive;
262
+
reg += bank * 0x40 + pin / 8 * 0x10;
263
+
264
+
/* mA */
265
+
if (config & MA_PRESENT) {
266
+
shift = pin % 8 * 4;
267
+
writel(0x3 << shift, reg + CLR);
268
+
writel(ma << shift, reg + SET);
269
+
}
270
+
271
+
/* vol */
272
+
if (config & VOL_PRESENT) {
273
+
shift = pin % 8 * 4 + 2;
274
+
if (vol)
275
+
writel(1 << shift, reg + SET);
276
+
else
277
+
writel(1 << shift, reg + CLR);
278
+
}
279
+
280
+
/* pull */
281
+
if (config & PULL_PRESENT) {
282
+
reg = d->base + d->soc->regs->pull;
283
+
reg += bank * 0x10;
284
+
shift = pin;
285
+
if (pull)
286
+
writel(1 << shift, reg + SET);
287
+
else
288
+
writel(1 << shift, reg + CLR);
289
+
}
290
+
}
291
+
292
+
/* cache the config value for mxs_pinconf_group_get() */
293
+
g->config = config;
294
+
295
+
return 0;
296
+
}
297
+
298
+
static void mxs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
299
+
struct seq_file *s, unsigned pin)
300
+
{
301
+
/* Not support */
302
+
}
303
+
304
+
static void mxs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
305
+
struct seq_file *s, unsigned group)
306
+
{
307
+
unsigned long config;
308
+
309
+
if (!mxs_pinconf_group_get(pctldev, group, &config))
310
+
seq_printf(s, "0x%lx", config);
311
+
}
312
+
313
+
struct pinconf_ops mxs_pinconf_ops = {
314
+
.pin_config_get = mxs_pinconf_get,
315
+
.pin_config_set = mxs_pinconf_set,
316
+
.pin_config_group_get = mxs_pinconf_group_get,
317
+
.pin_config_group_set = mxs_pinconf_group_set,
318
+
.pin_config_dbg_show = mxs_pinconf_dbg_show,
319
+
.pin_config_group_dbg_show = mxs_pinconf_group_dbg_show,
320
+
};
321
+
322
+
static struct pinctrl_desc mxs_pinctrl_desc = {
323
+
.pctlops = &mxs_pinctrl_ops,
324
+
.pmxops = &mxs_pinmux_ops,
325
+
.confops = &mxs_pinconf_ops,
326
+
.owner = THIS_MODULE,
327
+
};
328
+
329
+
static int __devinit mxs_pinctrl_parse_group(struct platform_device *pdev,
330
+
struct device_node *np, int idx,
331
+
const char **out_name)
332
+
{
333
+
struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
334
+
struct mxs_group *g = &d->soc->groups[idx];
335
+
struct property *prop;
336
+
const char *propname = "fsl,pinmux-ids";
337
+
char *group;
338
+
int length = strlen(np->name) + SUFFIX_LEN;
339
+
int i;
340
+
u32 val;
341
+
342
+
group = devm_kzalloc(&pdev->dev, length, GFP_KERNEL);
343
+
if (!group)
344
+
return -ENOMEM;
345
+
of_property_read_u32(np, "reg", &val);
346
+
snprintf(group, length, "%s.%d", np->name, val);
347
+
g->name = group;
348
+
349
+
prop = of_find_property(np, propname, &length);
350
+
if (!prop)
351
+
return -EINVAL;
352
+
g->npins = length / sizeof(u32);
353
+
354
+
g->pins = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->pins),
355
+
GFP_KERNEL);
356
+
if (!g->pins)
357
+
return -ENOMEM;
358
+
359
+
g->muxsel = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->muxsel),
360
+
GFP_KERNEL);
361
+
if (!g->muxsel)
362
+
return -ENOMEM;
363
+
364
+
of_property_read_u32_array(np, propname, g->pins, g->npins);
365
+
for (i = 0; i < g->npins; i++) {
366
+
g->muxsel[i] = MUXID_TO_MUXSEL(g->pins[i]);
367
+
g->pins[i] = MUXID_TO_PINID(g->pins[i]);
368
+
}
369
+
370
+
*out_name = g->name;
371
+
372
+
return 0;
373
+
}
374
+
375
+
static int __devinit mxs_pinctrl_probe_dt(struct platform_device *pdev,
376
+
struct mxs_pinctrl_data *d)
377
+
{
378
+
struct mxs_pinctrl_soc_data *soc = d->soc;
379
+
struct device_node *np = pdev->dev.of_node;
380
+
struct device_node *child;
381
+
struct mxs_function *f;
382
+
const char *fn, *fnull = "";
383
+
int i = 0, idxf = 0, idxg = 0;
384
+
int ret;
385
+
u32 val;
386
+
387
+
child = of_get_next_child(np, NULL);
388
+
if (!child) {
389
+
dev_err(&pdev->dev, "no group is defined\n");
390
+
return -ENOENT;
391
+
}
392
+
393
+
/* Count total functions and groups */
394
+
fn = fnull;
395
+
for_each_child_of_node(np, child) {
396
+
/* Skip pure pinconf node */
397
+
if (of_property_read_u32(child, "reg", &val))
398
+
continue;
399
+
if (strcmp(fn, child->name)) {
400
+
fn = child->name;
401
+
soc->nfunctions++;
402
+
}
403
+
soc->ngroups++;
404
+
}
405
+
406
+
soc->functions = devm_kzalloc(&pdev->dev, soc->nfunctions *
407
+
sizeof(*soc->functions), GFP_KERNEL);
408
+
if (!soc->functions)
409
+
return -ENOMEM;
410
+
411
+
soc->groups = devm_kzalloc(&pdev->dev, soc->ngroups *
412
+
sizeof(*soc->groups), GFP_KERNEL);
413
+
if (!soc->groups)
414
+
return -ENOMEM;
415
+
416
+
/* Count groups for each function */
417
+
fn = fnull;
418
+
f = &soc->functions[idxf];
419
+
for_each_child_of_node(np, child) {
420
+
if (of_property_read_u32(child, "reg", &val))
421
+
continue;
422
+
if (strcmp(fn, child->name)) {
423
+
f = &soc->functions[idxf++];
424
+
f->name = fn = child->name;
425
+
}
426
+
f->ngroups++;
427
+
};
428
+
429
+
/* Get groups for each function */
430
+
idxf = 0;
431
+
fn = fnull;
432
+
for_each_child_of_node(np, child) {
433
+
if (of_property_read_u32(child, "reg", &val))
434
+
continue;
435
+
if (strcmp(fn, child->name)) {
436
+
f = &soc->functions[idxf++];
437
+
f->groups = devm_kzalloc(&pdev->dev, f->ngroups *
438
+
sizeof(*f->groups),
439
+
GFP_KERNEL);
440
+
if (!f->groups)
441
+
return -ENOMEM;
442
+
fn = child->name;
443
+
i = 0;
444
+
}
445
+
ret = mxs_pinctrl_parse_group(pdev, child, idxg++,
446
+
&f->groups[i++]);
447
+
if (ret)
448
+
return ret;
449
+
}
450
+
451
+
return 0;
452
+
}
453
+
454
+
int __devinit mxs_pinctrl_probe(struct platform_device *pdev,
455
+
struct mxs_pinctrl_soc_data *soc)
456
+
{
457
+
struct device_node *np = pdev->dev.of_node;
458
+
struct mxs_pinctrl_data *d;
459
+
int ret;
460
+
461
+
d = devm_kzalloc(&pdev->dev, sizeof(*d), GFP_KERNEL);
462
+
if (!d)
463
+
return -ENOMEM;
464
+
465
+
d->dev = &pdev->dev;
466
+
d->soc = soc;
467
+
468
+
d->base = of_iomap(np, 0);
469
+
if (!d->base)
470
+
return -EADDRNOTAVAIL;
471
+
472
+
mxs_pinctrl_desc.pins = d->soc->pins;
473
+
mxs_pinctrl_desc.npins = d->soc->npins;
474
+
mxs_pinctrl_desc.name = dev_name(&pdev->dev);
475
+
476
+
platform_set_drvdata(pdev, d);
477
+
478
+
ret = mxs_pinctrl_probe_dt(pdev, d);
479
+
if (ret) {
480
+
dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
481
+
goto err;
482
+
}
483
+
484
+
d->pctl = pinctrl_register(&mxs_pinctrl_desc, &pdev->dev, d);
485
+
if (!d->pctl) {
486
+
dev_err(&pdev->dev, "Couldn't register MXS pinctrl driver\n");
487
+
ret = -EINVAL;
488
+
goto err;
489
+
}
490
+
491
+
return 0;
492
+
493
+
err:
494
+
iounmap(d->base);
495
+
return ret;
496
+
}
497
+
EXPORT_SYMBOL_GPL(mxs_pinctrl_probe);
498
+
499
+
int __devexit mxs_pinctrl_remove(struct platform_device *pdev)
500
+
{
501
+
struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
502
+
503
+
pinctrl_unregister(d->pctl);
504
+
iounmap(d->base);
505
+
506
+
return 0;
507
+
}
508
+
EXPORT_SYMBOL_GPL(mxs_pinctrl_remove);
+91
drivers/pinctrl/pinctrl-mxs.h
+91
drivers/pinctrl/pinctrl-mxs.h
···
1
+
/*
2
+
* Copyright 2012 Freescale Semiconductor, Inc.
3
+
*
4
+
* The code contained herein is licensed under the GNU General Public
5
+
* License. You may obtain a copy of the GNU General Public License
6
+
* Version 2 or later at the following locations:
7
+
*
8
+
* http://www.opensource.org/licenses/gpl-license.html
9
+
* http://www.gnu.org/copyleft/gpl.html
10
+
*/
11
+
12
+
#ifndef __PINCTRL_MXS_H
13
+
#define __PINCTRL_MXS_H
14
+
15
+
#include <linux/platform_device.h>
16
+
#include <linux/pinctrl/pinctrl.h>
17
+
18
+
#define SET 0x4
19
+
#define CLR 0x8
20
+
#define TOG 0xc
21
+
22
+
#define MXS_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
23
+
#define PINID(bank, pin) ((bank) * 32 + (pin))
24
+
25
+
/*
26
+
* pinmux-id bit field definitions
27
+
*
28
+
* bank: 15..12 (4)
29
+
* pin: 11..4 (8)
30
+
* muxsel: 3..0 (4)
31
+
*/
32
+
#define MUXID_TO_PINID(m) PINID((m) >> 12 & 0xf, (m) >> 4 & 0xff)
33
+
#define MUXID_TO_MUXSEL(m) ((m) & 0xf)
34
+
35
+
#define PINID_TO_BANK(p) ((p) >> 5)
36
+
#define PINID_TO_PIN(p) ((p) % 32)
37
+
38
+
/*
39
+
* pin config bit field definitions
40
+
*
41
+
* pull-up: 6..5 (2)
42
+
* voltage: 4..3 (2)
43
+
* mA: 2..0 (3)
44
+
*
45
+
* MSB of each field is presence bit for the config.
46
+
*/
47
+
#define PULL_PRESENT (1 << 6)
48
+
#define PULL_SHIFT 5
49
+
#define VOL_PRESENT (1 << 4)
50
+
#define VOL_SHIFT 3
51
+
#define MA_PRESENT (1 << 2)
52
+
#define MA_SHIFT 0
53
+
#define CONFIG_TO_PULL(c) ((c) >> PULL_SHIFT & 0x1)
54
+
#define CONFIG_TO_VOL(c) ((c) >> VOL_SHIFT & 0x1)
55
+
#define CONFIG_TO_MA(c) ((c) >> MA_SHIFT & 0x3)
56
+
57
+
struct mxs_function {
58
+
const char *name;
59
+
const char **groups;
60
+
unsigned ngroups;
61
+
};
62
+
63
+
struct mxs_group {
64
+
const char *name;
65
+
unsigned int *pins;
66
+
unsigned npins;
67
+
u8 *muxsel;
68
+
u8 config;
69
+
};
70
+
71
+
struct mxs_regs {
72
+
u16 muxsel;
73
+
u16 drive;
74
+
u16 pull;
75
+
};
76
+
77
+
struct mxs_pinctrl_soc_data {
78
+
const struct mxs_regs *regs;
79
+
const struct pinctrl_pin_desc *pins;
80
+
unsigned npins;
81
+
struct mxs_function *functions;
82
+
unsigned nfunctions;
83
+
struct mxs_group *groups;
84
+
unsigned ngroups;
85
+
};
86
+
87
+
int mxs_pinctrl_probe(struct platform_device *pdev,
88
+
struct mxs_pinctrl_soc_data *soc);
89
+
int mxs_pinctrl_remove(struct platform_device *pdev);
90
+
91
+
#endif /* __PINCTRL_MXS_H */
+40
-20
drivers/pinctrl/pinmux.c
+40
-20
drivers/pinctrl/pinmux.c
···
42
42
!ops->get_function_name ||
43
43
!ops->get_function_groups ||
44
44
!ops->enable ||
45
-
!ops->disable)
45
+
!ops->disable) {
46
+
dev_err(pctldev->dev, "pinmux ops lacks necessary functions\n");
46
47
return -EINVAL;
47
-
48
+
}
48
49
/* Check that all functions registered have names */
49
50
nfuncs = ops->get_functions_count(pctldev);
50
51
while (selector < nfuncs) {
···
92
91
desc = pin_desc_get(pctldev, pin);
93
92
if (desc == NULL) {
94
93
dev_err(pctldev->dev,
95
-
"pin is not registered so it cannot be requested\n");
94
+
"pin %d is not registered so it cannot be requested\n",
95
+
pin);
96
96
goto out;
97
97
}
98
98
···
104
102
/* There's no need to support multiple GPIO requests */
105
103
if (desc->gpio_owner) {
106
104
dev_err(pctldev->dev,
107
-
"pin already requested\n");
105
+
"pin %s already requested by %s; cannot claim for %s\n",
106
+
desc->name, desc->gpio_owner, owner);
108
107
goto out;
109
108
}
110
109
···
113
110
} else {
114
111
if (desc->mux_usecount && strcmp(desc->mux_owner, owner)) {
115
112
dev_err(pctldev->dev,
116
-
"pin already requested\n");
113
+
"pin %s already requested by %s; cannot claim for %s\n",
114
+
desc->name, desc->mux_owner, owner);
117
115
goto out;
118
116
}
119
117
···
147
143
status = 0;
148
144
149
145
if (status) {
150
-
dev_err(pctldev->dev, "->request on device %s failed for pin %d\n",
151
-
pctldev->desc->name, pin);
146
+
dev_err(pctldev->dev, "request() failed for pin %d\n", pin);
152
147
module_put(pctldev->owner);
153
148
}
154
149
···
164
161
out:
165
162
if (status)
166
163
dev_err(pctldev->dev, "pin-%d (%s) status %d\n",
167
-
pin, owner, status);
164
+
pin, owner, status);
168
165
169
166
return status;
170
167
}
···
332
329
return -EINVAL;
333
330
}
334
331
335
-
setting->data.mux.func =
336
-
pinmux_func_name_to_selector(pctldev, map->data.mux.function);
337
-
if (setting->data.mux.func < 0)
338
-
return setting->data.mux.func;
332
+
ret = pinmux_func_name_to_selector(pctldev, map->data.mux.function);
333
+
if (ret < 0) {
334
+
dev_err(pctldev->dev, "invalid function %s in map table\n",
335
+
map->data.mux.function);
336
+
return ret;
337
+
}
338
+
setting->data.mux.func = ret;
339
339
340
340
ret = pmxops->get_function_groups(pctldev, setting->data.mux.func,
341
341
&groups, &num_groups);
342
-
if (ret < 0)
342
+
if (ret < 0) {
343
+
dev_err(pctldev->dev, "can't query groups for function %s\n",
344
+
map->data.mux.function);
343
345
return ret;
344
-
if (!num_groups)
346
+
}
347
+
if (!num_groups) {
348
+
dev_err(pctldev->dev,
349
+
"function %s can't be selected on any group\n",
350
+
map->data.mux.function);
345
351
return -EINVAL;
346
-
352
+
}
347
353
if (map->data.mux.group) {
348
354
bool found = false;
349
355
group = map->data.mux.group;
···
362
350
break;
363
351
}
364
352
}
365
-
if (!found)
353
+
if (!found) {
354
+
dev_err(pctldev->dev,
355
+
"invalid group \"%s\" for function \"%s\"\n",
356
+
group, map->data.mux.function);
366
357
return -EINVAL;
358
+
}
367
359
} else {
368
360
group = groups[0];
369
361
}
370
362
371
-
setting->data.mux.group = pinctrl_get_group_selector(pctldev, group);
372
-
if (setting->data.mux.group < 0)
373
-
return setting->data.mux.group;
363
+
ret = pinctrl_get_group_selector(pctldev, group);
364
+
if (ret < 0) {
365
+
dev_err(pctldev->dev, "invalid group %s in map table\n",
366
+
map->data.mux.group);
367
+
return ret;
368
+
}
369
+
setting->data.mux.group = ret;
374
370
375
371
ret = pctlops->get_group_pins(pctldev, setting->data.mux.group, &pins,
376
372
&num_pins);
···
394
374
ret = pin_request(pctldev, pins[i], map->dev_name, NULL);
395
375
if (ret) {
396
376
dev_err(pctldev->dev,
397
-
"could not get request pin %d on device %s\n",
377
+
"could not request pin %d on device %s\n",
398
378
pins[i], pinctrl_dev_get_name(pctldev));
399
379
/* On error release all taken pins */
400
380
i--; /* this pin just failed */
+32
include/linux/clk.h
+32
include/linux/clk.h
···
101
101
struct clk *clk_get(struct device *dev, const char *id);
102
102
103
103
/**
104
+
* devm_clk_get - lookup and obtain a managed reference to a clock producer.
105
+
* @dev: device for clock "consumer"
106
+
* @id: clock comsumer ID
107
+
*
108
+
* Returns a struct clk corresponding to the clock producer, or
109
+
* valid IS_ERR() condition containing errno. The implementation
110
+
* uses @dev and @id to determine the clock consumer, and thereby
111
+
* the clock producer. (IOW, @id may be identical strings, but
112
+
* clk_get may return different clock producers depending on @dev.)
113
+
*
114
+
* Drivers must assume that the clock source is not enabled.
115
+
*
116
+
* devm_clk_get should not be called from within interrupt context.
117
+
*
118
+
* The clock will automatically be freed when the device is unbound
119
+
* from the bus.
120
+
*/
121
+
struct clk *devm_clk_get(struct device *dev, const char *id);
122
+
123
+
/**
104
124
* clk_prepare - prepare a clock source
105
125
* @clk: clock source
106
126
*
···
226
206
*/
227
207
void clk_put(struct clk *clk);
228
208
209
+
/**
210
+
* devm_clk_put - "free" a managed clock source
211
+
* @dev: device used to acuqire the clock
212
+
* @clk: clock source acquired with devm_clk_get()
213
+
*
214
+
* Note: drivers must ensure that all clk_enable calls made on this
215
+
* clock source are balanced by clk_disable calls prior to calling
216
+
* this function.
217
+
*
218
+
* clk_put should not be called from within interrupt context.
219
+
*/
220
+
void devm_clk_put(struct device *dev, struct clk *clk);
229
221
230
222
/*
231
223
* The remaining APIs are optional for machine class support.
+3
include/linux/clkdev.h
+3
include/linux/clkdev.h
···
40
40
void clkdev_add_table(struct clk_lookup *, size_t);
41
41
int clk_add_alias(const char *, const char *, char *, struct device *);
42
42
43
+
int clk_register_clkdev(struct clk *, const char *, const char *, ...);
44
+
int clk_register_clkdevs(struct clk *, struct clk_lookup *, size_t);
45
+
43
46
#endif
+16
include/linux/of.h
+16
include/linux/of.h
···
193
193
for (child = of_get_next_child(parent, NULL); child != NULL; \
194
194
child = of_get_next_child(parent, child))
195
195
196
+
static inline int of_get_child_count(const struct device_node *np)
197
+
{
198
+
struct device_node *child;
199
+
int num = 0;
200
+
201
+
for_each_child_of_node(np, child)
202
+
num++;
203
+
204
+
return num;
205
+
}
206
+
196
207
extern struct device_node *of_find_node_with_property(
197
208
struct device_node *from, const char *prop_name);
198
209
#define for_each_node_with_property(dn, prop_name) \
···
310
299
311
300
#define for_each_child_of_node(parent, child) \
312
301
while (0)
302
+
303
+
static inline int of_get_child_count(const struct device_node *np)
304
+
{
305
+
return 0;
306
+
}
313
307
314
308
static inline int of_device_is_compatible(const struct device_node *device,
315
309
const char *name)
+5
-2
include/linux/pinctrl/machine.h
+5
-2
include/linux/pinctrl/machine.h
···
154
154
155
155
extern int pinctrl_register_mappings(struct pinctrl_map const *map,
156
156
unsigned num_maps);
157
-
157
+
extern void pinctrl_provide_dummies(void);
158
158
#else
159
159
160
160
static inline int pinctrl_register_mappings(struct pinctrl_map const *map,
···
163
163
return 0;
164
164
}
165
165
166
-
#endif /* !CONFIG_PINMUX */
166
+
static inline void pinctrl_provide_dummies(void)
167
+
{
168
+
}
169
+
#endif /* !CONFIG_PINCTRL */
167
170
#endif
-1
include/linux/pinctrl/pinconf.h
-1
include/linux/pinctrl/pinconf.h
···
25
25
* @pin_config_get: get the config of a certain pin, if the requested config
26
26
* is not available on this controller this should return -ENOTSUPP
27
27
* and if it is available but disabled it should return -EINVAL
28
-
* @pin_config_get: get the config of a certain pin
29
28
* @pin_config_set: configure an individual pin
30
29
* @pin_config_group_get: get configurations for an entire pin group
31
30
* @pin_config_group_set: configure all pins in a group
+9
include/linux/pinctrl/pinctrl.h
+9
include/linux/pinctrl/pinctrl.h
···
72
72
* group selector @pins, and the size of the array in @num_pins
73
73
* @pin_dbg_show: optional debugfs display hook that will provide per-device
74
74
* info for a certain pin in debugfs
75
+
* @dt_node_to_map: parse a device tree "pin configuration node", and create
76
+
* mapping table entries for it. These are returned through the @map and
77
+
* @num_maps output parameters. This function is optional, and may be
78
+
* omitted for pinctrl drivers that do not support device tree.
79
+
* @dt_free_map: free mapping table entries created via @dt_node_to_map. The
80
+
* top-level @map pointer must be freed, along with any dynamically
81
+
* allocated members of the mapping table entries themselves. This
82
+
* function is optional, and may be omitted for pinctrl drivers that do
83
+
* not support device tree.
75
84
*/
76
85
struct pinctrl_ops {
77
86
int (*get_groups_count) (struct pinctrl_dev *pctldev);
+1
-1
include/linux/pinctrl/pinmux.h
+1
-1
include/linux/pinctrl/pinmux.h
···
23
23
/**
24
24
* struct pinmux_ops - pinmux operations, to be implemented by pin controller
25
25
* drivers that support pinmuxing
26
-
* @request: called by the core to see if a certain pin can be made available
26
+
* @request: called by the core to see if a certain pin can be made
27
27
* available for muxing. This is called by the core to acquire the pins
28
28
* before selecting any actual mux setting across a function. The driver
29
29
* is allowed to answer "no" by returning a negative error code