net: ethernet: realtek: atp: checkpatch errors and warnings corrected

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Several warnings and errors of coding style rules corrected.
Compile tested.

Signed-off-by: Roberto Medina <robertoxmed@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

authored by

Roberto Medina and committed by

David S. Miller 11 years ago 7aef06db 432c856f

+119 -111

1 changed file

expand all

drivers

net

ethernet

realtek

atp.h

+119 -111

drivers/net/ethernet/realtek/atp.h

··· 6 6 7 7 /* The header prepended to received packets. */ 8 8 struct rx_header { 9 - ushort pad; /* Pad. */ 10 - ushort rx_count; 11 - ushort rx_status; /* Unknown bit assignments :-<. */ 12 - ushort cur_addr; /* Apparently the current buffer address(?) */ 9 + ushort pad; /* Pad. */ 10 + ushort rx_count; 11 + ushort rx_status; /* Unknown bit assignments :-<. */ 12 + ushort cur_addr; /* Apparently the current buffer address(?) */ 13 13 }; 14 14 15 15 #define PAR_DATA 0 ··· 29 29 #define RdAddr 0xC0 30 30 #define HNib 0x10 31 31 32 - enum page0_regs 33 - { 34 - /* The first six registers hold the ethernet physical station address. */ 35 - PAR0 = 0, PAR1 = 1, PAR2 = 2, PAR3 = 3, PAR4 = 4, PAR5 = 5, 36 - TxCNT0 = 6, TxCNT1 = 7, /* The transmit byte count. */ 37 - TxSTAT = 8, RxSTAT = 9, /* Tx and Rx status. */ 38 - ISR = 10, IMR = 11, /* Interrupt status and mask. */ 39 - CMR1 = 12, /* Command register 1. */ 40 - CMR2 = 13, /* Command register 2. */ 41 - MODSEL = 14, /* Mode select register. */ 42 - MAR = 14, /* Memory address register (?). */ 43 - CMR2_h = 0x1d, }; 32 + enum page0_regs { 33 + /* The first six registers hold 34 + * the ethernet physical station address. 35 + */ 36 + PAR0 = 0, PAR1 = 1, PAR2 = 2, PAR3 = 3, PAR4 = 4, PAR5 = 5, 37 + TxCNT0 = 6, TxCNT1 = 7, /* The transmit byte count. */ 38 + TxSTAT = 8, RxSTAT = 9, /* Tx and Rx status. */ 39 + ISR = 10, IMR = 11, /* Interrupt status and mask. */ 40 + CMR1 = 12, /* Command register 1. */ 41 + CMR2 = 13, /* Command register 2. */ 42 + MODSEL = 14, /* Mode select register. */ 43 + MAR = 14, /* Memory address register (?). */ 44 + CMR2_h = 0x1d, 45 + }; 44 46 45 - enum eepage_regs 46 - { PROM_CMD = 6, PROM_DATA = 7 }; /* Note that PROM_CMD is in the "high" bits. */ 47 - 47 + enum eepage_regs { 48 + PROM_CMD = 6, 49 + PROM_DATA = 7 /* Note that PROM_CMD is in the "high" bits. */ 50 + }; 48 51 49 52 #define ISR_TxOK 0x01 50 53 #define ISR_RxOK 0x04 ··· 75 72 #define CMR2h_Normal 2 /* Accept physical and broadcast address. */ 76 73 #define CMR2h_PROMISC 3 /* Promiscuous mode. */ 77 74 78 - /* An inline function used below: it differs from inb() by explicitly return an unsigned 79 - char, saving a truncation. */ 75 + /* An inline function used below: it differs from inb() by explicitly 76 + * return an unsigned char, saving a truncation. 77 + */ 80 78 static inline unsigned char inbyte(unsigned short port) 81 79 { 82 - unsigned char _v; 83 - __asm__ __volatile__ ("inb %w1,%b0" :"=a" (_v):"d" (port)); 84 - return _v; 80 + unsigned char _v; 81 + 82 + __asm__ __volatile__ ("inb %w1,%b0" : "=a" (_v) : "d" (port)); 83 + return _v; 85 84 } 86 85 87 86 /* Read register OFFSET. 88 - This command should always be terminated with read_end(). */ 87 + * This command should always be terminated with read_end(). 88 + */ 89 89 static inline unsigned char read_nibble(short port, unsigned char offset) 90 90 { 91 - unsigned char retval; 92 - outb(EOC+offset, port + PAR_DATA); 93 - outb(RdAddr+offset, port + PAR_DATA); 94 - inbyte(port + PAR_STATUS); /* Settling time delay */ 95 - retval = inbyte(port + PAR_STATUS); 96 - outb(EOC+offset, port + PAR_DATA); 91 + unsigned char retval; 97 92 98 - return retval; 93 + outb(EOC+offset, port + PAR_DATA); 94 + outb(RdAddr+offset, port + PAR_DATA); 95 + inbyte(port + PAR_STATUS); /* Settling time delay */ 96 + retval = inbyte(port + PAR_STATUS); 97 + outb(EOC+offset, port + PAR_DATA); 98 + 99 + return retval; 99 100 } 100 101 101 102 /* Functions for bulk data read. The interrupt line is always disabled. */ 102 103 /* Get a byte using read mode 0, reading data from the control lines. */ 103 104 static inline unsigned char read_byte_mode0(short ioaddr) 104 105 { 105 - unsigned char low_nib; 106 + unsigned char low_nib; 106 107 107 - outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL); 108 - inbyte(ioaddr + PAR_STATUS); 109 - low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f; 110 - outb(Ctrl_HNibRead, ioaddr + PAR_CONTROL); 111 - inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */ 112 - inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */ 113 - return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0); 108 + outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL); 109 + inbyte(ioaddr + PAR_STATUS); 110 + low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f; 111 + outb(Ctrl_HNibRead, ioaddr + PAR_CONTROL); 112 + inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */ 113 + inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */ 114 + return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0); 114 115 } 115 116 116 117 /* The same as read_byte_mode0(), but does multiple inb()s for stability. */ 117 118 static inline unsigned char read_byte_mode2(short ioaddr) 118 119 { 119 - unsigned char low_nib; 120 + unsigned char low_nib; 120 121 121 - outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL); 122 - inbyte(ioaddr + PAR_STATUS); 123 - low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f; 124 - outb(Ctrl_HNibRead, ioaddr + PAR_CONTROL); 125 - inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */ 126 - return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0); 122 + outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL); 123 + inbyte(ioaddr + PAR_STATUS); 124 + low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f; 125 + outb(Ctrl_HNibRead, ioaddr + PAR_CONTROL); 126 + inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */ 127 + return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0); 127 128 } 128 129 129 130 /* Read a byte through the data register. */ 130 131 static inline unsigned char read_byte_mode4(short ioaddr) 131 132 { 132 - unsigned char low_nib; 133 + unsigned char low_nib; 133 134 134 - outb(RdAddr | MAR, ioaddr + PAR_DATA); 135 - low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f; 136 - outb(RdAddr | HNib | MAR, ioaddr + PAR_DATA); 137 - return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0); 135 + outb(RdAddr | MAR, ioaddr + PAR_DATA); 136 + low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f; 137 + outb(RdAddr | HNib | MAR, ioaddr + PAR_DATA); 138 + return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0); 138 139 } 139 140 140 141 /* Read a byte through the data register, double reading to allow settling. */ 141 142 static inline unsigned char read_byte_mode6(short ioaddr) 142 143 { 143 - unsigned char low_nib; 144 + unsigned char low_nib; 144 145 145 - outb(RdAddr | MAR, ioaddr + PAR_DATA); 146 - inbyte(ioaddr + PAR_STATUS); 147 - low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f; 148 - outb(RdAddr | HNib | MAR, ioaddr + PAR_DATA); 149 - inbyte(ioaddr + PAR_STATUS); 150 - return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0); 146 + outb(RdAddr | MAR, ioaddr + PAR_DATA); 147 + inbyte(ioaddr + PAR_STATUS); 148 + low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f; 149 + outb(RdAddr | HNib | MAR, ioaddr + PAR_DATA); 150 + inbyte(ioaddr + PAR_STATUS); 151 + return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0); 151 152 } 152 153 153 154 static inline void 154 155 write_reg(short port, unsigned char reg, unsigned char value) 155 156 { 156 - unsigned char outval; 157 - outb(EOC | reg, port + PAR_DATA); 158 - outval = WrAddr | reg; 159 - outb(outval, port + PAR_DATA); 160 - outb(outval, port + PAR_DATA); /* Double write for PS/2. */ 157 + unsigned char outval; 161 158 162 - outval &= 0xf0; 163 - outval |= value; 164 - outb(outval, port + PAR_DATA); 165 - outval &= 0x1f; 166 - outb(outval, port + PAR_DATA); 167 - outb(outval, port + PAR_DATA); 159 + outb(EOC | reg, port + PAR_DATA); 160 + outval = WrAddr | reg; 161 + outb(outval, port + PAR_DATA); 162 + outb(outval, port + PAR_DATA); /* Double write for PS/2. */ 168 163 169 - outb(EOC | outval, port + PAR_DATA); 164 + outval &= 0xf0; 165 + outval |= value; 166 + outb(outval, port + PAR_DATA); 167 + outval &= 0x1f; 168 + outb(outval, port + PAR_DATA); 169 + outb(outval, port + PAR_DATA); 170 + 171 + outb(EOC | outval, port + PAR_DATA); 170 172 } 171 173 172 174 static inline void 173 175 write_reg_high(short port, unsigned char reg, unsigned char value) 174 176 { 175 - unsigned char outval = EOC | HNib | reg; 177 + unsigned char outval = EOC | HNib | reg; 176 178 177 - outb(outval, port + PAR_DATA); 178 - outval &= WrAddr | HNib | 0x0f; 179 - outb(outval, port + PAR_DATA); 180 - outb(outval, port + PAR_DATA); /* Double write for PS/2. */ 179 + outb(outval, port + PAR_DATA); 180 + outval &= WrAddr | HNib | 0x0f; 181 + outb(outval, port + PAR_DATA); 182 + outb(outval, port + PAR_DATA); /* Double write for PS/2. */ 181 183 182 - outval = WrAddr | HNib | value; 183 - outb(outval, port + PAR_DATA); 184 - outval &= HNib | 0x0f; /* HNib | value */ 185 - outb(outval, port + PAR_DATA); 186 - outb(outval, port + PAR_DATA); 184 + outval = WrAddr | HNib | value; 185 + outb(outval, port + PAR_DATA); 186 + outval &= HNib | 0x0f; /* HNib | value */ 187 + outb(outval, port + PAR_DATA); 188 + outb(outval, port + PAR_DATA); 187 189 188 - outb(EOC | HNib | outval, port + PAR_DATA); 190 + outb(EOC | HNib | outval, port + PAR_DATA); 189 191 } 190 192 191 193 /* Write a byte out using nibble mode. The low nibble is written first. */ 192 194 static inline void 193 195 write_reg_byte(short port, unsigned char reg, unsigned char value) 194 196 { 195 - unsigned char outval; 196 - outb(EOC | reg, port + PAR_DATA); /* Reset the address register. */ 197 - outval = WrAddr | reg; 198 - outb(outval, port + PAR_DATA); 199 - outb(outval, port + PAR_DATA); /* Double write for PS/2. */ 197 + unsigned char outval; 200 198 201 - outb((outval & 0xf0) | (value & 0x0f), port + PAR_DATA); 202 - outb(value & 0x0f, port + PAR_DATA); 203 - value >>= 4; 204 - outb(value, port + PAR_DATA); 205 - outb(0x10 | value, port + PAR_DATA); 206 - outb(0x10 | value, port + PAR_DATA); 199 + outb(EOC | reg, port + PAR_DATA); /* Reset the address register. */ 200 + outval = WrAddr | reg; 201 + outb(outval, port + PAR_DATA); 202 + outb(outval, port + PAR_DATA); /* Double write for PS/2. */ 207 203 208 - outb(EOC | value, port + PAR_DATA); /* Reset the address register. */ 204 + outb((outval & 0xf0) | (value & 0x0f), port + PAR_DATA); 205 + outb(value & 0x0f, port + PAR_DATA); 206 + value >>= 4; 207 + outb(value, port + PAR_DATA); 208 + outb(0x10 | value, port + PAR_DATA); 209 + outb(0x10 | value, port + PAR_DATA); 210 + 211 + outb(EOC | value, port + PAR_DATA); /* Reset the address register. */ 209 212 } 210 213 211 - /* 212 - * Bulk data writes to the packet buffer. The interrupt line remains enabled. 214 + /* Bulk data writes to the packet buffer. The interrupt line remains enabled. 213 215 * The first, faster method uses only the dataport (data modes 0, 2 & 4). 214 216 * The second (backup) method uses data and control regs (modes 1, 3 & 5). 215 217 * It should only be needed when there is skew between the individual data ··· 222 214 */ 223 215 static inline void write_byte_mode0(short ioaddr, unsigned char value) 224 216 { 225 - outb(value & 0x0f, ioaddr + PAR_DATA); 226 - outb((value>>4) | 0x10, ioaddr + PAR_DATA); 217 + outb(value & 0x0f, ioaddr + PAR_DATA); 218 + outb((value>>4) | 0x10, ioaddr + PAR_DATA); 227 219 } 228 220 229 221 static inline void write_byte_mode1(short ioaddr, unsigned char value) 230 222 { 231 - outb(value & 0x0f, ioaddr + PAR_DATA); 232 - outb(Ctrl_IRQEN | Ctrl_LNibWrite, ioaddr + PAR_CONTROL); 233 - outb((value>>4) | 0x10, ioaddr + PAR_DATA); 234 - outb(Ctrl_IRQEN | Ctrl_HNibWrite, ioaddr + PAR_CONTROL); 223 + outb(value & 0x0f, ioaddr + PAR_DATA); 224 + outb(Ctrl_IRQEN | Ctrl_LNibWrite, ioaddr + PAR_CONTROL); 225 + outb((value>>4) | 0x10, ioaddr + PAR_DATA); 226 + outb(Ctrl_IRQEN | Ctrl_HNibWrite, ioaddr + PAR_CONTROL); 235 227 } 236 228 237 229 /* Write 16bit VALUE to the packet buffer: the same as above just doubled. */ 238 230 static inline void write_word_mode0(short ioaddr, unsigned short value) 239 231 { 240 - outb(value & 0x0f, ioaddr + PAR_DATA); 241 - value >>= 4; 242 - outb((value & 0x0f) | 0x10, ioaddr + PAR_DATA); 243 - value >>= 4; 244 - outb(value & 0x0f, ioaddr + PAR_DATA); 245 - value >>= 4; 246 - outb((value & 0x0f) | 0x10, ioaddr + PAR_DATA); 232 + outb(value & 0x0f, ioaddr + PAR_DATA); 233 + value >>= 4; 234 + outb((value & 0x0f) | 0x10, ioaddr + PAR_DATA); 235 + value >>= 4; 236 + outb(value & 0x0f, ioaddr + PAR_DATA); 237 + value >>= 4; 238 + outb((value & 0x0f) | 0x10, ioaddr + PAR_DATA); 247 239 } 248 240 249 241 /* EEPROM_Ctrl bits. */ ··· 256 248 257 249 /* Delay between EEPROM clock transitions. */ 258 250 #define eeprom_delay(ticks) \ 259 - do { int _i = 40; while (--_i > 0) { __SLOW_DOWN_IO; }} while (0) 251 + do { int _i = 40; while (--_i > 0) { __SLOW_DOWN_IO; } } while (0) 260 252 261 253 /* The EEPROM commands include the alway-set leading bit. */ 262 254 #define EE_WRITE_CMD(offset) (((5 << 6) + (offset)) << 17) 263 - #define EE_READ(offset) (((6 << 6) + (offset)) << 17) 255 + #define EE_READ(offset) (((6 << 6) + (offset)) << 17) 264 256 #define EE_ERASE(offset) (((7 << 6) + (offset)) << 17) 265 257 #define EE_CMD_SIZE 27 /* The command+address+data size. */