···588588 WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED |589589 WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN;590590591591+ /* PG 1.0 has some problems with MCS_13, so disable it */592592+ wl->ht_cap.mcs.rx_mask[1] &= ~BIT(5);593593+591594 /* TODO: need to blocksize alignment for RX/TX separately? */592595 break;593596 default:···917914 skb->ip_summed = CHECKSUM_UNNECESSARY;918915}919916917917+/*918918+ * TODO: instead of having these two functions to get the rate mask,919919+ * we should modify the wlvif->rate_set instead920920+ */920921static u32 wl18xx_sta_get_ap_rate_mask(struct wl1271 *wl,921922 struct wl12xx_vif *wlvif)922923{···947940 return CONF_TX_RATE_USE_WIDE_CHAN;948941 } else {949942 wl1271_debug(DEBUG_ACX, "using MIMO rate mask");943943+944944+ /*945945+ * PG 1.0 has some problems with MCS_13, so disable it946946+ *947947+ * TODO: instead of hacking this in here, we should948948+ * make it more general and change a bit in the949949+ * wlvif->rate_set instead.950950+ */951951+ if (wl->chip.id == CHIP_ID_185x_PG10)952952+ return CONF_TX_MIMO_RATES & ~CONF_HW_BIT_RATE_MCS_13;953953+950954 return CONF_TX_MIMO_RATES;951955 }952956}