Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

mmc: sdhci-pci: Quirk for AMD SDHC Device 0x7906

AMD SDHC 0x7906 requires a hard reset to clear all internal state.
Otherwise it can get into a bad state where the DATA lines are always
read as zeros.

This change requires firmware that can transition the device into
D3Cold for it to work correctly. If the firmware does not support
transitioning to D3Cold then the power state transitions are a no-op.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

authored by

Raul E Rangel and committed by
Ulf Hansson
7a869f00 dcaac3f7

+50 -1
+50 -1
drivers/mmc/host/sdhci-pci-core.c
··· 21 21 #include <linux/mmc/mmc.h> 22 22 #include <linux/scatterlist.h> 23 23 #include <linux/io.h> 24 + #include <linux/iopoll.h> 24 25 #include <linux/gpio.h> 25 26 #include <linux/pm_runtime.h> 26 27 #include <linux/mmc/slot-gpio.h> ··· 1591 1590 return 0; 1592 1591 } 1593 1592 1593 + static u32 sdhci_read_present_state(struct sdhci_host *host) 1594 + { 1595 + return sdhci_readl(host, SDHCI_PRESENT_STATE); 1596 + } 1597 + 1598 + void amd_sdhci_reset(struct sdhci_host *host, u8 mask) 1599 + { 1600 + struct sdhci_pci_slot *slot = sdhci_priv(host); 1601 + struct pci_dev *pdev = slot->chip->pdev; 1602 + u32 present_state; 1603 + 1604 + /* 1605 + * SDHC 0x7906 requires a hard reset to clear all internal state. 1606 + * Otherwise it can get into a bad state where the DATA lines are always 1607 + * read as zeros. 1608 + */ 1609 + if (pdev->device == 0x7906 && (mask & SDHCI_RESET_ALL)) { 1610 + pci_clear_master(pdev); 1611 + 1612 + pci_save_state(pdev); 1613 + 1614 + pci_set_power_state(pdev, PCI_D3cold); 1615 + pr_debug("%s: power_state=%u\n", mmc_hostname(host->mmc), 1616 + pdev->current_state); 1617 + pci_set_power_state(pdev, PCI_D0); 1618 + 1619 + pci_restore_state(pdev); 1620 + 1621 + /* 1622 + * SDHCI_RESET_ALL says the card detect logic should not be 1623 + * reset, but since we need to reset the entire controller 1624 + * we should wait until the card detect logic has stabilized. 1625 + * 1626 + * This normally takes about 40ms. 1627 + */ 1628 + readx_poll_timeout( 1629 + sdhci_read_present_state, 1630 + host, 1631 + present_state, 1632 + present_state & SDHCI_CD_STABLE, 1633 + 10000, 1634 + 100000 1635 + ); 1636 + } 1637 + 1638 + return sdhci_reset(host, mask); 1639 + } 1640 + 1594 1641 static const struct sdhci_ops amd_sdhci_pci_ops = { 1595 1642 .set_clock = sdhci_set_clock, 1596 1643 .enable_dma = sdhci_pci_enable_dma, 1597 1644 .set_bus_width = sdhci_set_bus_width, 1598 - .reset = sdhci_reset, 1645 + .reset = amd_sdhci_reset, 1599 1646 .set_uhs_signaling = sdhci_set_uhs_signaling, 1600 1647 }; 1601 1648