tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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pinctrl: amd: Don't access irq_data's hwirq member directly

There is an irqd_to_hwirq() intended to get the hwirq number. Switch
all use to it.

Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/20250821144942.2463014-1-superm1@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

authored by

Mario Limonciello (AMD) and committed by
Linus Walleij 7a399ce6 54b962fa

+23 -17
+23 -17
drivers/pinctrl/pinctrl-amd.c
··· 383 383 unsigned long flags; 384 384 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 385 385 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 386 + irq_hw_number_t hwirq = irqd_to_hwirq(d); 386 387 387 - gpiochip_enable_irq(gc, d->hwirq); 388 + gpiochip_enable_irq(gc, hwirq); 388 389 389 390 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 390 - pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 391 + pin_reg = readl(gpio_dev->base + hwirq * 4); 391 392 pin_reg |= BIT(INTERRUPT_ENABLE_OFF); 392 393 pin_reg |= BIT(INTERRUPT_MASK_OFF); 393 - writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 394 + writel(pin_reg, gpio_dev->base + hwirq * 4); 394 395 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 395 396 } 396 397 ··· 401 400 unsigned long flags; 402 401 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 403 402 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 403 + irq_hw_number_t hwirq = irqd_to_hwirq(d); 404 404 405 405 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 406 - pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 406 + pin_reg = readl(gpio_dev->base + hwirq * 4); 407 407 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); 408 408 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 409 - writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 409 + writel(pin_reg, gpio_dev->base + hwirq * 4); 410 410 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 411 411 412 - gpiochip_disable_irq(gc, d->hwirq); 412 + gpiochip_disable_irq(gc, hwirq); 413 413 } 414 414 415 415 static void amd_gpio_irq_mask(struct irq_data *d) ··· 419 417 unsigned long flags; 420 418 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 421 419 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 420 + irq_hw_number_t hwirq = irqd_to_hwirq(d); 422 421 423 422 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 424 - pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 423 + pin_reg = readl(gpio_dev->base + hwirq * 4); 425 424 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 426 - writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 425 + writel(pin_reg, gpio_dev->base + hwirq * 4); 427 426 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 428 427 } 429 428 ··· 434 431 unsigned long flags; 435 432 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 436 433 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 434 + irq_hw_number_t hwirq = irqd_to_hwirq(d); 437 435 438 436 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 439 - pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 437 + pin_reg = readl(gpio_dev->base + hwirq * 4); 440 438 pin_reg |= BIT(INTERRUPT_MASK_OFF); 441 - writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 439 + writel(pin_reg, gpio_dev->base + hwirq * 4); 442 440 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 443 441 } 444 442 ··· 450 446 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 451 447 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 452 448 u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3); 449 + irq_hw_number_t hwirq = irqd_to_hwirq(d); 453 450 int err; 454 451 455 452 pm_pr_dbg("Setting wake for GPIO %lu to %s\n", 456 - d->hwirq, str_enable_disable(on)); 453 + hwirq, str_enable_disable(on)); 457 454 458 455 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 459 - pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 456 + pin_reg = readl(gpio_dev->base + hwirq * 4); 460 457 461 458 if (on) 462 459 pin_reg |= wake_mask; 463 460 else 464 461 pin_reg &= ~wake_mask; 465 462 466 - writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 463 + writel(pin_reg, gpio_dev->base + hwirq * 4); 467 464 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 468 465 469 466 if (on) ··· 500 495 unsigned long flags; 501 496 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 502 497 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 498 + irq_hw_number_t hwirq = irqd_to_hwirq(d); 503 499 504 500 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 505 - pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 501 + pin_reg = readl(gpio_dev->base + hwirq * 4); 506 502 507 503 switch (type & IRQ_TYPE_SENSE_MASK) { 508 504 case IRQ_TYPE_EDGE_RISING: ··· 569 563 pin_reg_irq_en = pin_reg; 570 564 pin_reg_irq_en |= mask; 571 565 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF); 572 - writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4); 573 - while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask) 566 + writel(pin_reg_irq_en, gpio_dev->base + hwirq * 4); 567 + while ((readl(gpio_dev->base + hwirq * 4) & mask) != mask) 574 568 continue; 575 - writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 569 + writel(pin_reg, gpio_dev->base + hwirq * 4); 576 570 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 577 571 578 572 return ret;