Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

riscv: dts: microchip: move timebase-frequency to mpfs.dtsi

The timebase-frequency on PolarFire SoC is not set by an oscillator on
the board, but rather by an internal divider, so move the property to
mpfs.dtsi.

This looks to be copy-pasta from the SiFive Unleashed as the comments
in both places were almost identical. In the Unleashed's case this looks
to actually be valid, as the clock is provided by a crystal on the PCB.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
CC: Conor Dooley <conor.dooley@microchip.com>
CC: Daire McNamara <daire.mcnamara@microchip.com>
CC: Rob Herring <robh+dt@kernel.org>
CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
CC: Paul Walmsley <paul.walmsley@sifive.com>
CC: Palmer Dabbelt <palmer@dabbelt.com>
CC: linux-riscv@lists.infradead.org
CC: devicetree@vger.kernel.org

+1 -35
-7
arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
··· 8 8 #include <dt-bindings/gpio/gpio.h> 9 9 #include <dt-bindings/leds/common.h> 10 10 11 - /* Clock frequency (in Hz) of the rtcclk */ 12 - #define RTCCLK_FREQ 1000000 13 - 14 11 / { 15 12 model = "Microchip PolarFire-SoC Icicle Kit"; 16 13 compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit", ··· 24 27 25 28 chosen { 26 29 stdout-path = "serial1:115200n8"; 27 - }; 28 - 29 - cpus { 30 - timebase-frequency = <RTCCLK_FREQ>; 31 30 }; 32 31 33 32 leds {
-7
arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts
··· 10 10 #include "mpfs.dtsi" 11 11 #include "mpfs-m100pfs-fabric.dtsi" 12 12 13 - /* Clock frequency (in Hz) of the rtcclk */ 14 - #define MTIMER_FREQ 1000000 15 - 16 13 / { 17 14 model = "Aries Embedded M100PFEVPS"; 18 15 compatible = "aries,m100pfsevp", "microchip,mpfs"; ··· 28 31 29 32 chosen { 30 33 stdout-path = "serial1:115200n8"; 31 - }; 32 - 33 - cpus { 34 - timebase-frequency = <MTIMER_FREQ>; 35 34 }; 36 35 37 36 ddrc_cache_lo: memory@80000000 {
-7
arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
··· 6 6 #include "mpfs.dtsi" 7 7 #include "mpfs-polarberry-fabric.dtsi" 8 8 9 - /* Clock frequency (in Hz) of the rtcclk */ 10 - #define MTIMER_FREQ 1000000 11 - 12 9 / { 13 10 model = "Sundance PolarBerry"; 14 11 compatible = "sundance,polarberry", "microchip,mpfs"; ··· 17 20 18 21 chosen { 19 22 stdout-path = "serial0:115200n8"; 20 - }; 21 - 22 - cpus { 23 - timebase-frequency = <MTIMER_FREQ>; 24 23 }; 25 24 26 25 ddrc_cache_lo: memory@80000000 {
-7
arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts
··· 6 6 #include "mpfs.dtsi" 7 7 #include "mpfs-sev-kit-fabric.dtsi" 8 8 9 - /* Clock frequency (in Hz) of the rtcclk */ 10 - #define MTIMER_FREQ 1000000 11 - 12 9 / { 13 10 #address-cells = <2>; 14 11 #size-cells = <2>; ··· 23 26 24 27 chosen { 25 28 stdout-path = "serial1:115200n8"; 26 - }; 27 - 28 - cpus { 29 - timebase-frequency = <MTIMER_FREQ>; 30 29 }; 31 30 32 31 reserved-memory {
-7
arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts
··· 11 11 #include "mpfs.dtsi" 12 12 #include "mpfs-tysom-m-fabric.dtsi" 13 13 14 - /* Clock frequency (in Hz) of the rtcclk */ 15 - #define MTIMER_FREQ 1000000 16 - 17 14 / { 18 15 model = "Aldec TySOM-M-MPFS250T-REV2"; 19 16 compatible = "aldec,tysom-m-mpfs250t-rev2", "microchip,mpfs"; ··· 29 32 30 33 chosen { 31 34 stdout-path = "serial1:115200n8"; 32 - }; 33 - 34 - cpus { 35 - timebase-frequency = <MTIMER_FREQ>; 36 35 }; 37 36 38 37 ddrc_cache_lo: memory@80000000 {
+1
arch/riscv/boot/dts/microchip/mpfs.dtsi
··· 13 13 cpus { 14 14 #address-cells = <1>; 15 15 #size-cells = <0>; 16 + timebase-frequency = <1000000>; 16 17 17 18 cpu0: cpu@0 { 18 19 compatible = "sifive,e51", "sifive,rocket0", "riscv";