[media] s5p-fimc: Fix output DMA handling in S5PV310 IP revisions

FIMC IP in S5Pv310 series has extended DMA status registers
and some bit fields are marked as reserved comparing to S5PC100/110.
Use correct registers for getting DMA write pointer in each SoC variant
supported by the driver.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

authored by Sylwester Nawrocki and committed by Mauro Carvalho Chehab 798174ab a8365fc2

+19 -3
+1
drivers/media/video/s5p-fimc/fimc-capture.c
··· 522 522 INIT_LIST_HEAD(&fimc->vid_cap.active_buf_q); 523 523 fimc->vid_cap.active_buf_cnt = 0; 524 524 fimc->vid_cap.frame_count = 0; 525 + fimc->vid_cap.buf_index = fimc_hw_get_frame_index(fimc); 525 526 526 527 set_bit(ST_CAPT_PEND, &fimc->state); 527 528 ret = videobuf_streamon(&fimc->vid_cap.vbq);
+2
drivers/media/video/s5p-fimc/fimc-core.c
··· 1746 1746 .pix_hoff = 1, 1747 1747 .has_inp_rot = 1, 1748 1748 .has_out_rot = 1, 1749 + .has_cistatus2 = 1, 1749 1750 .min_inp_pixsize = 16, 1750 1751 .min_out_pixsize = 16, 1751 1752 .hor_offs_align = 1, ··· 1756 1755 1757 1756 static struct samsung_fimc_variant fimc2_variant_s5pv310 = { 1758 1757 .pix_hoff = 1, 1758 + .has_cistatus2 = 1, 1759 1759 .min_inp_pixsize = 16, 1760 1760 .min_out_pixsize = 16, 1761 1761 .hor_offs_align = 1,
+13 -3
drivers/media/video/s5p-fimc/fimc-core.h
··· 371 371 * @pix_hoff: indicate whether horizontal offset is in pixels or in bytes 372 372 * @has_inp_rot: set if has input rotator 373 373 * @has_out_rot: set if has output rotator 374 + * @has_cistatus2: 1 if CISTATUS2 register is present in this IP revision 374 375 * @pix_limit: pixel size constraints for the scaler 375 376 * @min_inp_pixsize: minimum input pixel size 376 377 * @min_out_pixsize: minimum output pixel size ··· 382 381 unsigned int pix_hoff:1; 383 382 unsigned int has_inp_rot:1; 384 383 unsigned int has_out_rot:1; 384 + unsigned int has_cistatus2:1; 385 385 struct fimc_pix_limit *pix_limit; 386 386 u16 min_inp_pixsize; 387 387 u16 min_out_pixsize; ··· 558 556 return frame; 559 557 } 560 558 559 + /* Return an index to the buffer actually being written. */ 561 560 static inline u32 fimc_hw_get_frame_index(struct fimc_dev *dev) 562 561 { 563 - u32 reg = readl(dev->regs + S5P_CISTATUS); 564 - return (reg & S5P_CISTATUS_FRAMECNT_MASK) >> 565 - S5P_CISTATUS_FRAMECNT_SHIFT; 562 + u32 reg; 563 + 564 + if (dev->variant->has_cistatus2) { 565 + reg = readl(dev->regs + S5P_CISTATUS2) & 0x3F; 566 + return reg > 0 ? --reg : reg; 567 + } else { 568 + reg = readl(dev->regs + S5P_CISTATUS); 569 + return (reg & S5P_CISTATUS_FRAMECNT_MASK) >> 570 + S5P_CISTATUS_FRAMECNT_SHIFT; 571 + } 566 572 } 567 573 568 574 /* -----------------------------------------------------*/
+3
drivers/media/video/s5p-fimc/regs-fimc.h
··· 165 165 #define S5P_CISTATUS_VVALID_A (1 << 15) 166 166 #define S5P_CISTATUS_VVALID_B (1 << 14) 167 167 168 + /* Indexes to the last and the currently processed buffer. */ 169 + #define S5P_CISTATUS2 0x68 170 + 168 171 /* Image capture control */ 169 172 #define S5P_CIIMGCPT 0xc0 170 173 #define S5P_CIIMGCPT_IMGCPTEN (1 << 31)