Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

IB/mlx5: Allow posting multi packet send WQEs if hardware supports

Set the field to allow posting multi packet send WQEs if hardware
supports this feature. This doesn't mean the send WQEs will be for
multi packet unless the send WQE was prepared according to multi
packet send WQE format.

User space shall use flag MLX5_IB_ALLOW_MPW to check if hardware
supports MPW and allows MPW in SQ context.

Signed-off-by: Bodong Wang <bodong@mellanox.com>
Reviewed-by: Daniel Jurgens <danielj@mellanox.com>
Signed-off-by: Leon Romanovsky <leon@kernel.org>
Signed-off-by: Doug Ledford <dledford@redhat.com>

authored by

Bodong Wang and committed by
Doug Ledford
795b609c a550ddfc

+11 -3
+3 -2
drivers/infiniband/hw/mlx5/main.c
··· 802 802 803 803 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes, 804 804 uhw->outlen)) { 805 - resp.mlx5_ib_support_multi_pkt_send_wqes = 806 - MLX5_CAP_ETH(mdev, multi_pkt_send_wqe); 805 + if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 806 + resp.mlx5_ib_support_multi_pkt_send_wqes = 807 + MLX5_IB_ALLOW_MPW; 807 808 resp.response_length += 808 809 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 809 810 }
+2
drivers/infiniband/hw/mlx5/qp.c
··· 1083 1083 1084 1084 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1085 1085 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1086 + if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) 1087 + MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1); 1086 1088 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1087 1089 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1088 1090 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
+1 -1
include/linux/mlx5/mlx5_ifc.h
··· 2445 2445 u8 cd_master[0x1]; 2446 2446 u8 fre[0x1]; 2447 2447 u8 flush_in_error_en[0x1]; 2448 - u8 reserved_at_4[0x1]; 2448 + u8 allow_multi_pkt_send_wqe[0x1]; 2449 2449 u8 min_wqe_inline_mode[0x3]; 2450 2450 u8 state[0x4]; 2451 2451 u8 reg_umr[0x1];
+5
include/uapi/rdma/mlx5-abi.h
··· 168 168 __u32 reserved; 169 169 }; 170 170 171 + enum mlx5_ib_mpw_caps { 172 + MPW_RESERVED = 1 << 0, 173 + MLX5_IB_ALLOW_MPW = 1 << 1, 174 + }; 175 + 171 176 enum mlx5_ib_sw_parsing_offloads { 172 177 MLX5_IB_SW_PARSING = 1 << 0, 173 178 MLX5_IB_SW_PARSING_CSUM = 1 << 1,