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dt-bindings: PCI: kirin: Convert kirin-pcie.txt to yaml

Convert the file into a JSON description at the yaml format.

Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Link: https://lore.kernel.org/r/081c179ef2e0ddf11566144cd5967b15268565b4.1628061310.git.mchehab+huawei@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>

authored by

Mauro Carvalho Chehab and committed by
Rob Herring
78e29356 2de207f5

+88 -52
+86
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
··· 1 + # SPDX-License-Identifier: GPL-2.0 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: HiSilicon Kirin SoCs PCIe host DT description 8 + 9 + maintainers: 10 + - Xiaowei Song <songxiaowei@hisilicon.com> 11 + - Binghui Wang <wangbinghui@hisilicon.com> 12 + 13 + description: | 14 + Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. 15 + It shares common functions with the PCIe DesignWare core driver and 16 + inherits common properties defined in 17 + Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml. 18 + 19 + allOf: 20 + - $ref: /schemas/pci/snps,dw-pcie.yaml# 21 + 22 + properties: 23 + compatible: 24 + contains: 25 + enum: 26 + - hisilicon,kirin960-pcie 27 + 28 + reg: 29 + description: | 30 + Should contain dbi, apb, config registers location and length. 31 + For HiKey960, it should also contain phy. 32 + minItems: 3 33 + maxItems: 4 34 + 35 + reg-names: 36 + minItems: 3 37 + maxItems: 4 38 + 39 + required: 40 + - compatible 41 + - reg 42 + - reg-names 43 + 44 + unevaluatedProperties: false 45 + 46 + examples: 47 + - | 48 + #include <dt-bindings/interrupt-controller/arm-gic.h> 49 + #include <dt-bindings/clock/hi3660-clock.h> 50 + 51 + soc { 52 + #address-cells = <2>; 53 + #size-cells = <2>; 54 + 55 + pcie@f4000000 { 56 + compatible = "hisilicon,kirin960-pcie"; 57 + reg = <0x0 0xf4000000 0x0 0x1000>, 58 + <0x0 0xff3fe000 0x0 0x1000>, 59 + <0x0 0xf3f20000 0x0 0x40000>, 60 + <0x0 0xf5000000 0x0 0x2000>; 61 + reg-names = "dbi", "apb", "phy", "config"; 62 + bus-range = <0x0 0xff>; 63 + #address-cells = <3>; 64 + #size-cells = <2>; 65 + device_type = "pci"; 66 + ranges = <0x02000000 0x0 0x00000000 67 + 0x0 0xf6000000 68 + 0x0 0x02000000>; 69 + num-lanes = <1>; 70 + #interrupt-cells = <1>; 71 + interrupts = <0 283 4>; 72 + interrupt-names = "msi"; 73 + interrupt-map-mask = <0xf800 0 0 7>; 74 + interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 75 + <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 76 + <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 77 + <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 78 + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, 79 + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, 80 + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, 81 + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, 82 + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; 83 + clock-names = "pcie_phy_ref", "pcie_aux", "pcie_apb_phy", 84 + "pcie_apb_sys", "pcie_aclk"; 85 + }; 86 + };
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Documentation/devicetree/bindings/pci/kirin-pcie.txt
··· 1 - HiSilicon Kirin SoCs PCIe host DT description 2 - 3 - Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. 4 - It shares common functions with the PCIe DesignWare core driver and 5 - inherits common properties defined in 6 - Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml. 7 - 8 - Additional properties are described here: 9 - 10 - Required properties 11 - - compatible: 12 - "hisilicon,kirin960-pcie" 13 - - reg: Should contain rc_dbi, apb, phy, config registers location and length. 14 - - reg-names: Must include the following entries: 15 - "dbi": controller configuration registers; 16 - "apb": apb Ctrl register defined by Kirin; 17 - "phy": apb PHY register defined by Kirin; 18 - "config": PCIe configuration space registers. 19 - - reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal. 20 - 21 - Optional properties: 22 - 23 - Example based on kirin960: 24 - 25 - pcie@f4000000 { 26 - compatible = "hisilicon,kirin960-pcie"; 27 - reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, 28 - <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>; 29 - reg-names = "dbi","apb","phy", "config"; 30 - bus-range = <0x0 0x1>; 31 - #address-cells = <3>; 32 - #size-cells = <2>; 33 - device_type = "pci"; 34 - ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>; 35 - num-lanes = <1>; 36 - #interrupt-cells = <1>; 37 - interrupt-map-mask = <0xf800 0 0 7>; 38 - interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>, 39 - <0x0 0 0 2 &gic 0 0 0 283 4>, 40 - <0x0 0 0 3 &gic 0 0 0 284 4>, 41 - <0x0 0 0 4 &gic 0 0 0 285 4>; 42 - clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, 43 - <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, 44 - <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, 45 - <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, 46 - <&crg_ctrl HI3660_ACLK_GATE_PCIE>; 47 - clock-names = "pcie_phy_ref", "pcie_aux", 48 - "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk"; 49 - reset-gpios = <&gpio11 1 0 >; 50 - };
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Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
··· 35 35 maxItems: 5 36 36 items: 37 37 enum: [ dbi, dbi2, config, atu, app, elbi, mgmt, ctrl, parf, cfg, link, 38 - ulreg, smu, mpu ] 38 + ulreg, smu, mpu, apb, phy ] 39 39 40 40 num-lanes: 41 41 description: |
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MAINTAINERS
··· 14413 14413 M: Binghui Wang <wangbinghui@hisilicon.com> 14414 14414 L: linux-pci@vger.kernel.org 14415 14415 S: Maintained 14416 - F: Documentation/devicetree/bindings/pci/kirin-pcie.txt 14416 + F: Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml 14417 14417 F: drivers/pci/controller/dwc/pcie-kirin.c 14418 14418 14419 14419 PCIE DRIVER FOR HISILICON STB