tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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staging: vt6656: rf.c: Remove camel case from local variables

Camel case changes;
Static declaration
abyAL2230InitTable -> al2230_init_table
abyAL2230ChannelTable0 -> al2230_channel_table0
abyAL2230ChannelTable1 -> al2230_channel_table1

abyAL7230InitTable -> al7230_init_table_amode
abyAL7230ChannelTable0 -> al7230_channel_table0
abyAL7230ChannelTable1 -> al7230_channel_table1
abyAL7230ChannelTable2 -> al7230_channel_table2

abyVT3226_InitTable -> at3226_init_table
abyVT3226D0_InitTable -> at3226d0_init_table
abyVT3226_ChannelTable0 -> vt3226_channel_table0
abyVT3226_ChannelTable1 -> vt3226_channel_table1

abyVT3342A0_InitTable -> vt3342a0_init_table
abyVT3342_ChannelTable0 -> vt3342_channel_table0
abyVT3342_ChannelTable1 -> vt3342_channel_table1

Constant declaration
dwVT3226D0LoCurrentTable -> vt3226d0_lo_current_table

dwAL2230PowerTable -> al2230_power_table

Signed-off-by: Malcolm Priestley <tvboxspy@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Malcolm Priestley and committed by
Greg Kroah-Hartman 78a650dc d9652aef

+38 -38
+38 -38
drivers/staging/vt6656/rf.c
··· 64 64 #define VT3342_PWR_IDX_LEN 64 65 65 //}} 66 66 67 - u8 abyAL2230InitTable[CB_AL2230_INIT_SEQ][3] = { 67 + static u8 al2230_init_table[CB_AL2230_INIT_SEQ][3] = { 68 68 {0x03, 0xF7, 0x90}, 69 69 {0x03, 0x33, 0x31}, 70 70 {0x01, 0xB8, 0x02}, ··· 82 82 {0x00, 0x58, 0x0F} 83 83 }; 84 84 85 - u8 abyAL2230ChannelTable0[CB_MAX_CHANNEL_24G][3] = { 85 + static u8 al2230_channel_table0[CB_MAX_CHANNEL_24G][3] = { 86 86 {0x03, 0xF7, 0x90}, // channel = 1, Tf = 2412MHz 87 87 {0x03, 0xF7, 0x90}, // channel = 2, Tf = 2417MHz 88 88 {0x03, 0xE7, 0x90}, // channel = 3, Tf = 2422MHz ··· 99 99 {0x03, 0xE7, 0xC0} // channel = 14, Tf = 2412M 100 100 }; 101 101 102 - u8 abyAL2230ChannelTable1[CB_MAX_CHANNEL_24G][3] = { 102 + static u8 al2230_channel_table1[CB_MAX_CHANNEL_24G][3] = { 103 103 {0x03, 0x33, 0x31}, // channel = 1, Tf = 2412MHz 104 104 {0x0B, 0x33, 0x31}, // channel = 2, Tf = 2417MHz 105 105 {0x03, 0x33, 0x31}, // channel = 3, Tf = 2422MHz ··· 118 118 119 119 // 40MHz reference frequency 120 120 // Need to Pull PLLON(PE3) low when writing channel registers through 3-wire. 121 - u8 abyAL7230InitTable[CB_AL7230_INIT_SEQ][3] = { 121 + static u8 al7230_init_table[CB_AL7230_INIT_SEQ][3] = { 122 122 {0x20, 0x37, 0x90}, // Channel1 // Need modify for 11a 123 123 {0x13, 0x33, 0x31}, // Channel1 // Need modify for 11a 124 124 {0x84, 0x1F, 0xF2}, // Need modify for 11a: 451FE2 ··· 141 141 {0x1A, 0xBA, 0x8F} // Need modify for 11a: 12BACF 142 142 }; 143 143 144 - u8 abyAL7230InitTableAMode[CB_AL7230_INIT_SEQ][3] = { 144 + static u8 al7230_init_table_amode[CB_AL7230_INIT_SEQ][3] = { 145 145 {0x2F, 0xF5, 0x20}, // Channel184 // Need modify for 11b/g 146 146 {0x00, 0x00, 0x01}, // Channel184 // Need modify for 11b/g 147 147 {0x45, 0x1F, 0xE2}, // Need modify for 11b/g ··· 160 160 {0x12, 0xBA, 0xCF} // Need modify for 11b/g 161 161 }; 162 162 163 - u8 abyAL7230ChannelTable0[CB_MAX_CHANNEL][3] = { 163 + static u8 al7230_channel_table0[CB_MAX_CHANNEL][3] = { 164 164 {0x20, 0x37, 0x90}, // channel = 1, Tf = 2412MHz 165 165 {0x20, 0x37, 0x90}, // channel = 2, Tf = 2417MHz 166 166 {0x20, 0x37, 0x90}, // channel = 3, Tf = 2422MHz ··· 226 226 {0x2F, 0xF6, 0x10} // channel = 165, Tf = 5825MHz (56) 227 227 }; 228 228 229 - u8 abyAL7230ChannelTable1[CB_MAX_CHANNEL][3] = { 229 + static u8 al7230_channel_table1[CB_MAX_CHANNEL][3] = { 230 230 {0x13, 0x33, 0x31}, // channel = 1, Tf = 2412MHz 231 231 {0x1B, 0x33, 0x31}, // channel = 2, Tf = 2417MHz 232 232 {0x03, 0x33, 0x31}, // channel = 3, Tf = 2422MHz ··· 290 290 {0x02, 0xAA, 0xB1} // channel = 165, Tf = 5825MHz (56) 291 291 }; 292 292 293 - u8 abyAL7230ChannelTable2[CB_MAX_CHANNEL][3] = { 293 + static u8 al7230_channel_table2[CB_MAX_CHANNEL][3] = { 294 294 {0x7F, 0xD7, 0x84}, // channel = 1, Tf = 2412MHz 295 295 {0x7F, 0xD7, 0x84}, // channel = 2, Tf = 2417MHz 296 296 {0x7F, 0xD7, 0x84}, // channel = 3, Tf = 2422MHz ··· 355 355 }; 356 356 357 357 ///{{RobertYu:20051111 358 - u8 abyVT3226_InitTable[CB_VT3226_INIT_SEQ][3] = { 358 + static u8 at3226_init_table[CB_VT3226_INIT_SEQ][3] = { 359 359 {0x03, 0xFF, 0x80}, 360 360 {0x02, 0x82, 0xA1}, 361 361 {0x03, 0xC6, 0xA2}, ··· 369 369 {0x02, 0x00, 0x2A} 370 370 }; 371 371 372 - u8 abyVT3226D0_InitTable[CB_VT3226_INIT_SEQ][3] = { 372 + static u8 at3226d0_init_table[CB_VT3226_INIT_SEQ][3] = { 373 373 {0x03, 0xFF, 0x80}, 374 374 {0x03, 0x02, 0x21}, //RobertYu:20060327 375 375 {0x03, 0xC6, 0xA2}, ··· 383 383 {0x02, 0x01, 0xAA} //RobertYu:20060523 384 384 }; 385 385 386 - u8 abyVT3226_ChannelTable0[CB_MAX_CHANNEL_24G][3] = { 386 + static u8 vt3226_channel_table0[CB_MAX_CHANNEL_24G][3] = { 387 387 {0x01, 0x97, 0x83}, // channel = 1, Tf = 2412MHz 388 388 {0x01, 0x97, 0x83}, // channel = 2, Tf = 2417MHz 389 389 {0x01, 0x97, 0x93}, // channel = 3, Tf = 2422MHz ··· 400 400 {0x03, 0x37, 0xC3} // channel = 14, Tf = 2484MHz 401 401 }; 402 402 403 - u8 abyVT3226_ChannelTable1[CB_MAX_CHANNEL_24G][3] = { 403 + static u8 vt3226_channel_table1[CB_MAX_CHANNEL_24G][3] = { 404 404 {0x02, 0x66, 0x64}, // channel = 1, Tf = 2412MHz 405 405 {0x03, 0x66, 0x64}, // channel = 2, Tf = 2417MHz 406 406 {0x00, 0x66, 0x64}, // channel = 3, Tf = 2422MHz ··· 419 419 ///}}RobertYu 420 420 421 421 //{{RobertYu:20060502, TWIF 1.14, LO Current for 11b mode 422 - u32 dwVT3226D0LoCurrentTable[CB_MAX_CHANNEL_24G] = { 422 + const u32 vt3226d0_lo_current_table[CB_MAX_CHANNEL_24G] = { 423 423 0x0135C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz 424 424 0x0135C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz 425 425 0x0235C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz ··· 438 438 //}} 439 439 440 440 //{{RobertYu:20060609 441 - u8 abyVT3342A0_InitTable[CB_VT3342_INIT_SEQ][3] = { /* 11b/g mode */ 441 + static u8 vt3342a0_init_table[CB_VT3342_INIT_SEQ][3] = { /* 11b/g mode */ 442 442 {0x03, 0xFF, 0x80}, //update for mode// 443 443 {0x02, 0x08, 0x81}, 444 444 {0x00, 0xC6, 0x02}, ··· 461 461 // channel56, 5280MHz 0x00C402 for disable Frac 462 462 // other channels 0x00C602 463 463 464 - u8 abyVT3342_ChannelTable0[CB_MAX_CHANNEL][3] = { 464 + static u8 vt3342_channel_table0[CB_MAX_CHANNEL][3] = { 465 465 {0x02, 0x05, 0x03}, // channel = 1, Tf = 2412MHz 466 466 {0x01, 0x15, 0x03}, // channel = 2, Tf = 2417MHz 467 467 {0x03, 0xC5, 0x03}, // channel = 3, Tf = 2422MHz ··· 527 527 {0x00, 0x06, 0x03} // channel = 165, Tf = 5825MHz (56), TBD 528 528 }; 529 529 530 - u8 abyVT3342_ChannelTable1[CB_MAX_CHANNEL][3] = { 530 + static u8 vt3342_channel_table1[CB_MAX_CHANNEL][3] = { 531 531 {0x01, 0x99, 0x94}, // channel = 1, Tf = 2412MHz 532 532 {0x02, 0x44, 0x44}, // channel = 2, Tf = 2417MHz 533 533 {0x02, 0xEE, 0xE4}, // channel = 3, Tf = 2422MHz ··· 597 597 * 598 598 -*/ 599 599 600 - const u32 dwAL2230PowerTable[AL2230_PWR_IDX_LEN] = { 600 + const u32 al2230_power_table[AL2230_PWR_IDX_LEN] = { 601 601 0x04040900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 602 602 0x04041900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 603 603 0x04042900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, ··· 802 802 return false; 803 803 804 804 ret &= IFRFbWriteEmbedded(priv, 805 - dwAL2230PowerTable[priv->byCurPwr]); 805 + al2230_power_table[priv->byCurPwr]); 806 806 807 807 if (rate <= RATE_11M) 808 808 ret &= IFRFbWriteEmbedded(priv, 0x0001b400 + ··· 816 816 return false; 817 817 818 818 ret &= IFRFbWriteEmbedded(priv, 819 - dwAL2230PowerTable[priv->byCurPwr]); 819 + al2230_power_table[priv->byCurPwr]); 820 820 821 821 if (rate <= RATE_11M) { 822 822 ret &= IFRFbWriteEmbedded(priv, 0x040c1400 + ··· 880 880 "RFbRawSetPower> 11B mode uCurrChannel[%d]\n", 881 881 priv->vnt_mgmt.uScanChannel); 882 882 ret &= IFRFbWriteEmbedded(priv, 883 - dwVT3226D0LoCurrentTable[priv-> 883 + vt3226d0_lo_current_table[priv-> 884 884 vnt_mgmt.uScanChannel - 1]); 885 885 } else { 886 886 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO 887 887 "RFbRawSetPower> 11B mode uCurrChannel[%d]\n", 888 888 priv->vnt_mgmt.uCurrChannel); 889 889 ret &= IFRFbWriteEmbedded(priv, 890 - dwVT3226D0LoCurrentTable[priv-> 890 + vt3226d0_lo_current_table[priv-> 891 891 vnt_mgmt.uCurrChannel - 1]); 892 892 } 893 893 ··· 979 979 length1 = CB_AL2230_INIT_SEQ * 3; 980 980 length2 = CB_MAX_CHANNEL_24G * 3; 981 981 length3 = CB_MAX_CHANNEL_24G * 3; 982 - addr1 = &abyAL2230InitTable[0][0]; 983 - addr2 = &abyAL2230ChannelTable0[0][0]; 984 - addr3 = &abyAL2230ChannelTable1[0][0]; 982 + addr1 = &al2230_init_table[0][0]; 983 + addr2 = &al2230_channel_table0[0][0]; 984 + addr3 = &al2230_channel_table1[0][0]; 985 985 break; 986 986 case RF_AIROHA7230: 987 987 length1 = CB_AL7230_INIT_SEQ * 3; 988 988 length2 = CB_MAX_CHANNEL * 3; 989 989 length3 = CB_MAX_CHANNEL * 3; 990 - addr1 = &abyAL7230InitTable[0][0]; 991 - addr2 = &abyAL7230ChannelTable0[0][0]; 992 - addr3 = &abyAL7230ChannelTable1[0][0]; 990 + addr1 = &al7230_init_table[0][0]; 991 + addr2 = &al7230_channel_table0[0][0]; 992 + addr3 = &al7230_channel_table1[0][0]; 993 993 break; 994 994 case RF_VT3226: 995 995 length1 = CB_VT3226_INIT_SEQ * 3; 996 996 length2 = CB_MAX_CHANNEL_24G * 3; 997 997 length3 = CB_MAX_CHANNEL_24G * 3; 998 - addr1 = &abyVT3226_InitTable[0][0]; 999 - addr2 = &abyVT3226_ChannelTable0[0][0]; 1000 - addr3 = &abyVT3226_ChannelTable1[0][0]; 998 + addr1 = &at3226_init_table[0][0]; 999 + addr2 = &vt3226_channel_table0[0][0]; 1000 + addr3 = &vt3226_channel_table1[0][0]; 1001 1001 break; 1002 1002 case RF_VT3226D0: 1003 1003 length1 = CB_VT3226_INIT_SEQ * 3; 1004 1004 length2 = CB_MAX_CHANNEL_24G * 3; 1005 1005 length3 = CB_MAX_CHANNEL_24G * 3; 1006 - addr1 = &abyVT3226D0_InitTable[0][0]; 1007 - addr2 = &abyVT3226_ChannelTable0[0][0]; 1008 - addr3 = &abyVT3226_ChannelTable1[0][0]; 1006 + addr1 = &at3226d0_init_table[0][0]; 1007 + addr2 = &vt3226_channel_table0[0][0]; 1008 + addr3 = &vt3226_channel_table1[0][0]; 1009 1009 break; 1010 1010 case RF_VT3342A0: 1011 1011 length1 = CB_VT3342_INIT_SEQ * 3; 1012 1012 length2 = CB_MAX_CHANNEL * 3; 1013 1013 length3 = CB_MAX_CHANNEL * 3; 1014 - addr1 = &abyVT3342A0_InitTable[0][0]; 1015 - addr2 = &abyVT3342_ChannelTable0[0][0]; 1016 - addr3 = &abyVT3342_ChannelTable1[0][0]; 1014 + addr1 = &vt3342a0_init_table[0][0]; 1015 + addr2 = &vt3342_channel_table0[0][0]; 1016 + addr3 = &vt3342_channel_table1[0][0]; 1017 1017 break; 1018 1018 } 1019 1019 ··· 1062 1062 if (priv->byRFType == RF_AIROHA7230) { 1063 1063 length1 = CB_AL7230_INIT_SEQ * 3; 1064 1064 length2 = CB_MAX_CHANNEL * 3; 1065 - addr1 = &(abyAL7230InitTableAMode[0][0]); 1066 - addr2 = &(abyAL7230ChannelTable2[0][0]); 1065 + addr1 = &(al7230_init_table_amode[0][0]); 1066 + addr2 = &(al7230_channel_table2[0][0]); 1067 1067 1068 1068 memcpy(array, addr1, length1); 1069 1069